CY7C6431x CY7C6434x CY7C6435x enCoRe™ V Full Speed USB Controller enCoRe™ V Full Speed USB Controller Features ■ Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 3.0 V to 5.5 V operating voltage without USB ❐ Operating voltage with USB enabled: • 3.15 V to 3.45 V when supply voltage is around 3.3 V • 4.35 V to 5.25 V when supply voltage is around 5.0 V ❐ Commercial temperature range: 0 °C to +70 °C ❐ Industrial temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ Up to 32 KB flash program storage: • 50,000 erase and write cycles • Flexible protection modes ❐ Up to 2048 bytes SRAM data storage ❐ In-system serial programming (ISSP) ■ Complete development tools ❐ Free development tool PSoC Designer™ ❐ Full-featured, in-circuit emulator and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128-KB trace memory ■ Precision, programmable clocking ❐ Crystal-less oscillator with support for an external crystal or resonator ❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO): • 0.25% accuracy with oscillator lock to USB data, no external components required • Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep. The frequency range is 19 to 50 kHz with a 32-kHz typical value ■ ■ ■ Programmable pin configurations ❐ Up to 36 general purpose I/O (GPIO) depending on package. ❐ 25 mA sink current on all GPIO • 60mA total sink current on Even port pins and 60 mA total sink current on Odd port pins • 120 mA total sink current on all GPIOs ❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO ❐ CMOS drive mode A -5 mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 • 20 mA total source current on all GPIOs ❐ Low dropout voltage regulator for Port 1 pins: • Programmable to output 3.0, 2.5, or 1.8 V ❐ Selectable, regulated digital I/O on Port 1 ❐ Configurable input threshold for Port 1 ❐ Hot-swappable Capability on Port 1 Full-Speed USB (12 Mbps) ❐ Eight unidirectional endpoints ❐ One bidirectional control endpoint ❐ USB 2.0-compliant: TID# 40000893 ❐ Dedicated 512 bytes buffer ❐ No external crystal required Additional system resources ❐ Configurable communication speeds 2 ❐ I C slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • Implementation requires no clock stretching • Implementation during sleep modes with less than 100 A • Hardware address detection ❐ SPI master and SPI slave: • Configurable between 46.9 kHz and 12 MHz ❐ Three 16-bit timers ❐ 10-bit ADC used to monitor battery voltage or other signals with external components ❐ Watchdog and sleep timers ❐ Integrated supervisory circuit enCoRe V Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 2048 Bytes SROM 8K/16K/32K Flash Sleep and Watchdog CPU Core (M8C) Interrupt Controller 6/12/24 MHz Internal Main Oscillator ADC 3 16-Bit Timers I2C Slave/SPI Master-Slave POR and LVD System Resets Full Speed USB SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-12394 Rev. *P • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 23, 2013 CY7C6431x CY7C6434x CY7C6435x Contents Functional Overview ........................................................ 3 The enCoRe V Core .................................................... 3 Full-Speed USB ........................................................... 3 10-bit ADC ................................................................... 4 SPI ............................................................................... 4 I2C Slave ..................................................................... 5 Additional System Resources ..................................... 6 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 7 PSoC Designer Software Subsystems ........................ 7 Designing with PSoC Designer ....................................... 8 Select User Modules ................................................... 8 Configure User Modules .............................................. 8 Organize and Connect ................................................ 8 Generate, Verify, and Debug ....................................... 8 Pin Configuration ............................................................. 9 16-pin Part pinout ........................................................ 9 32-pin Part Pinout ...................................................... 10 48-pin Part Pinout ...................................................... 11 Register Reference ......................................................... 13 Register Conventions .................................................... 13 Document Number: 001-12394 Rev. *P Register Mapping Tables ............................................... 13 Electrical Specifications ................................................ 16 Absolute Maximum Ratings ....................................... 17 Operating Temperature ............................................. 17 DC Electrical Characteristics ..................................... 18 AC Electrical Characteristics ..................................... 22 Package Diagram ............................................................ 29 Packaging Dimensions .............................................. 29 Package Handling ..................................................... 31 Thermal Impedances ................................................. 31 Capacitance on Crystal Pins ..................................... 31 Solder Reflow Peak Temperature ............................. 31 Ordering Information ...................................................... 32 Ordering Code Definitions ......................................... 33 Acronyms ........................................................................ 34 Document Conventions ................................................. 34 Units of Measure ....................................................... 34 Numeric Naming ........................................................ 34 Appendix: Errata Document for enCoRe™ V – CY7C643xx ............................................. 35 CY7C643xx Errata Summary .................................... 35 Document History Page ................................................. 37 Sales, Solutions, and Legal Information ...................... 40 Worldwide Sales and Design Support ....................... 40 Products .................................................................... 40 PSoC Solutions ......................................................... 40 Page 2 of 40 CY7C6431x CY7C6434x CY7C6435x Functional Overview Figure 1. USB Transceiver Regulator The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. 1.5K The architecture for this device family, as illustrated in the enCoRe V Block Diagram on page 1, consists of two main areas: the CPU core and the system resources. Depending on the enCoRe V package, up to 36 GPIO are also included. System resources provide additional capability, such as a configurable I2C slave and SPI master-slave communication interface and various system resets supported by the M8C. Full-Speed USB The enCoRe V USB system resource adheres to the USB 2.0 Specification for full speed devices operating at 12 Mb/second with one upstream port and one USB address. enCoRe V USB consists of these components: ■ Serial interface engine (SIE) block. ■ PSoC memory arbiter (PMA) block. ■ 512 bytes of dedicated SRAM. ■ A full-speed USB Transceiver with internal regulator and two dedicated USB pins. Document Number: 001-12394 Rev. *P DP TD DM TRANSMITTER PDN RD DPO RSE0 The enCoRe V Core During USB operation, the CPU speed can be set to any setting. Be aware that USB throughput decreases with a decrease in CPU speed. For maximum throughput, the CPU clock should be made equal to the system clock. The system clock must be 24 MHz for USB operation. 5K TEN RECEIVERS This product is an enhanced version of Cypress’s successful full speed-USB peripheral controllers. Enhancements include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash, hot-swappable I/Os, I2C hardware address recognition, new very low current sleep mode, and new package options. The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor. PS2 Pull Up VOLTAGE REGULATOR 5V 3.3V DMO At the enCoRe V system level, the full-speed USB system resource interfaces to the rest of the enCoRe V by way of the M8C’s register access instructions and to the outside world by way of the two USB pins. The SIE supports nine endpoints including a bidirectional control endpoint (endpoint 0) and eight unidirectional data endpoints (endpoints 1 to 8). The unidirectional data endpoints are individually configurable as either IN or OUT. Low value series resistors REXT (22 Ω) must be added externally to the D+ and D– lines to meet the driving impedance requirement for full-speed USB. The USB Serial Interface Engine (SIE) allows the enCoRe V device to communicate with the USB host at full speed data rates (12 Mb/s). The SIE simplifies the interface to USB traffic by automatically handling the following USB processing tasks without firmware intervention: ■ Translates the encoded received data and formats the data to be transmitted on the bus. ■ Generates and checks cyclical redundancy checks (CRCs). Incoming packets failing checksum verification are ignored. ■ Checks addresses. Ignores all transactions not addressed to the device. ■ Sends appropriate ACK/NAK/Stall handshakes. ■ Identifies token type (SETUP, IN, OUT) and sets the appropriate token bit once a valid token in received. ■ Identifies Start-of-Frame (SOF) and saves the frame count. ■ Sends data to or retrieves data from the USB SRAM, by way of the PSoC Memory Arbiter (PMA). Page 3 of 40 CY7C6431x CY7C6434x CY7C6435x Firmware is required to handle various parts of the USB interface. The SIE issues interrupts after key USB events to direct firmware to appropriate tasks: ■ Fill and empty the USB data buffers in USB SRAM. ■ Enable PMA channels appropriately. ■ Coordinate enumeration by decoding USB device requests. ■ Suspend and resume coordination. ■ Verify and select data toggle values. input mux or the temperature sensor with an input voltage range of 0 V to VREFADC. In the ADC only configuration (the ADC MUX selects the Analog mux bus, not the default temperature sensor connection), an external voltage can be connected to the input of the modulator for voltage conversion. The ADC is run for a number of cycles set by the timer, depending upon the desired resolution of the ADC. A counter counts the number of trips by the comparator, which is proportional to the input voltage. The Temp Sensor block clock speed is 36 MHz and is divided down to 1 to 12 MHz for ADC operation. 10-bit ADC SPI The ADC on enCoRe V device is an independent block with a state machine interface to control accesses to the block. The ADC is housed together with the temperature sensor core and can be connected to this or the Analog mux bus. As a default operation, the ADC is connected to the temperature sensor diodes to give digital values of the temperature. The serial peripheral interconnect (SPI) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. Figure 2. ADC System Performance Block Diagram VIN TEMP SENSOR/ ADC Figure 3. Basic SPI Configuration SPI Master SPI Slave Data is output by Data is registered at the both the Master input of both devices on the and Slave on opposite edge of the clock. one edge of the clock. SCLK MOSI MISO TEMP DIODES ADC SYSTEM BUS INTERFACE BLOCK COMMAND/ STATUS A device can be a master or slave. A master outputs clock and data to the slave device and inputs slave data. A slave device inputs clock and data from the master device and outputs data for input to the master. Together, the master and slave are essentially a circular Shift register, where the master generates the clocking and initiates data transfers. A basic data transfer occurs when the master sends eight bits of data, along with eight clocks. In any transfer, both master and slave transmit and receive simultaneously. If the master only sends data, the received data from the slave is ignored. If the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. Figure 4. SPI Block Diagram SPI Block MOSI, MISO SCLK DATA_IN DATA_OUT CLK_IN CLK_OUT SCLK INT SYSCLK Interface to the M8 C ( Processor ) Core MOSI, MISO SS_ Registers The ADC User Module contains an integrator block and one comparator with positive and negative input set by the MUXes. The input to the integrator stage comes from the analog global Document Number: 001-12394 Rev. *P CONFIGURATION[7:0] CONTROL[7:0] TRANSMIT[7:0] RECEIVE[7:0] Page 4 of 40 CY7C6431x CY7C6434x CY7C6435x SPI configuration register (SPI_CFG) sets master/slave functionality, clock speed, and interrupt select. SPI control register (SPI_CR) provides four control bits and four status bits for device interfacing and synchronization. The SPIM hardware has no support for driving the Slave Select (SS_) signal. The behavior and use of this signal is dependent on the application and enCoRe V device and, if required, must be implemented in firmware. There is an additional data input in the SPIS, Slave Select (SS_), which is an active low signal. SS_ must be asserted to enable the SPIS to receive and transmit. SS_ has two high level functions: ■ To allow for the selection of a given slave in a multi-slave environment. ■ To provide additional clocking for TX data queuing in SPI modes 0 and 1. I2C Slave The I2C slave enhanced communications block is a serial-to-parallel processor, designed to interface the enCoRe V device to a two-wire I2C serial communications bus. To eliminate the need for excessive CPU intervention and overhead, the block provides I2C-specific support for status detection and generation of framing bits. By default, the I2C slave enhanced module is firmware compatible with the previous generation of I2C slave functionality. However, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. The basic I2C features include: ■ Slave, transmitter, and receiver operation. ■ Byte processing for low CPU overhead. ■ Interrupt or polling CPU interface. ■ Support for clock rates of up to 400 kHz. ■ 7- or 10-bit addressing (through firmware support). ■ SMBus operation (through firmware support). Enhanced features of the I2C Slave Enhanced Module include: ■ Support for 7-bit hardware address compare. ■ Flexible data buffering schemes. ■ A "no bus stalling" operating mode. ■ A low power bus monitoring mode. The I2C block controls the data (SDA) and the clock (SCL) to the external I2C interface through direct connections to two dedicated GPIO pins. When I2C is enabled, these GPIO pins are not available for general purpose use. The enCoRe V CPU firmware interacts with the block through I/O register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. In the default operating mode, which is firmware compatible with previous versions of I2C slave modules, the I2C bus is stalled upon every received address or byte, and the CPU is required to read the data or supply data as required before the I2C bus continues. However, this I2C Slave Enhanced module provides new data buffering capability as an enhanced feature. In the EZI2C buffering mode, the I2C slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave never stalls the bus. In this protocol, the data available in the RAM (this is managed by the CPU) is valid. Figure 5. I2C Block Diagram I2C Plus Slave I2C Core To/From GPIO Pins SCL_IN CPU Port I2C Basic Configuration I2C_BUF I2C_CFG SDA_OUT SCL_OUT I2C_EN I2C_SCR 32 Byte RAM I2C_DR HW Addr Cmp I2C_ADDR Buffer Ctl I2C_BP Plus Features Document Number: 001-12394 Rev. *P System Bus SDA_IN Buffer Module SYSCLK I2C_CP I2C_XCFG MCU_BP I2C_XSTAT MCU_CP STANDBY Page 5 of 40 CY7C6431x CY7C6434x CY7C6435x Additional System Resources Application Notes System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource. Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com. ■ Low voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (power on reset) circuit eliminates the need for a system supervisor. PSoC development kits are available online from Cypress at http://www.cypress.com and through a growing number of regional and global distributors, including Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. ■ The 5 V maximum input, 1.8, 2.5, or 3 V selectable output, LDO regulator provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. Training ■ Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts. Getting Started The quickest path to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, see the enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx Technical Reference Manual (TRM) for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at http://www.cypress.com. Development Kits Free PSoC technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to http://www.cypress.com and look for CYPros Consultants. Solutions Library Visit our growing library of solution-focused designs at http://www.cypress.com. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Document Number: 001-12394 Rev. *P Page 6 of 40 CY7C6431x CY7C6434x CY7C6435x Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. ■ Integrated source-code editor (C and assembly) Debugger ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC’s resources for a given application. Document Number: 001-12394 Rev. *P Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Page 7 of 40 CY7C6431x CY7C6434x CY7C6435x Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called user modules. User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse width modulator (PWM) user module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module Document Number: 001-12394 Rev. *P data sheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 8 of 40 CY7C6431x CY7C6434x CY7C6435x Pin Configuration The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-pin Part pinout P2[5] P0[1] P0[3] P0[7] 15 14 13 6 7 8 D+ D– VDD QFN (Top View) 12 11 10 9 5 P1[5] P1[1] 1 2 3 4 VSS P2[3] P1[7] 16 Figure 6. CY7C64315/CY7C64316 16-pin enCoRe V USB Device P0[4] XRES P1[4] P1[0] Table 1. Pin Definitions – 16-pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type I/O I/OHR I/OHR I/OHR Power USB line USB line Power I/OHR I/OHR Input I/OH I/OH I/OH I/OH I/O Name P2[3] P1[7] P1[5] P1[1][1, 2] VSS D+ D– VDD P1[0][1, 2] P1[4] XRES P0[4] P0[7] P0[3] P0[1] P2[5] Description Digital I/O, crystal input (Xin) Digital I/O, SPI SS, I2C SCL Digital I/O, SPI MISO, I2C SDA Digital I/O, ISSP CLK, I2C SCL, SPI MOSI Ground connection USB PHY USB PHY Supply Digital I/O, ISSP DATA, I2C SDA, SPI CLK Digital I/O, optional external clock input (EXTCLK) Active high external reset with internal pull-down Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O, crystal output (Xout) LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 2. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *P Page 9 of 40 CY7C6431x CY7C6434x CY7C6435x 32-pin Part Pinout P0[3] P0[5] P0[7] VDD P0[6] P0[4] P0[2] 30 29 28 27 26 25 VSS 32 31 Figure 7. CY7C64343/CY7C64345 32-pin enCoRe V USB Device P2[0] 19 P3[2] P1[3] P1[1] 7 8 18 P3[0] 17 XRES P1[0] D+ 16 20 15 ( Top View) 6 P1[6] 5 P1[5] P1[4] P2[4] P2[2] P1[2] QFN 13 14 P2[1] P1[7] 22 21 12 P2[6] 3 4 11 P0[0] 23 D– VDD 24 2 9 10 1 P2[5] P2[3] VSS P0[1] Table 2. Pin Definitions – 32-pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP Type I/OH I/O I/O I/O I/OHR I/OHR I/OHR I/OHR Power I/O I/O Power I/OHR I/OHR I/OHR I/OHR Reset I/O I/O I/O I/O I/O I/O I/OH I/OH I/OH I/OH Power I/OH I/OH I/OH Power Power Name P0[1] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1][3, 4] VSS D+ D– VDD P1[0][3, 4] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS VSS Description Digital I/O Digital I/O, crystal output (Xout) Digital I/O, crystal Input (Xin) Digital I/O Digital I/O, I2C SCL, SPI SS Digital I/O, I2C SDA, SPI MISO Digital I/O, SPI CLK Digital I/O, ISSP CLK, I2C SCL, SPI MOSI Ground USB PHY USB PHY Supply voltage Digital I/O, ISSP DATA, I2C SDA, SPI CLK Digital I/O Digital I/O, optional external clock input (EXTCLK) Digital I/O Active high external reset with internal pull down Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Supply voltage Digital I/O Digital I/O Digital I/O Ground Ensure the center pad is connected to ground LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 3. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 4. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *P Page 10 of 40 CY7C6431x CY7C6434x CY7C6435x 48-pin Part Pinout P0[0] 38 37 VDD P0[6] P0[4] P0[2] NC NC 43 42 41 40 39 P0[5] P0[7] 45 44 QFN 19 20 21 22 23 24 VSS D+ DVDD P1[0] P1[2] 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] P2[4] P2[2] P2[0] P4[2] P4[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] P1[4] 17 18 P1[1] P1[3] NC NC 15 16 (Top View) 13 14 3 4 5 6 7 8 9 10 11 12 46 47 1 2 P1[5] NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] 48 P0[1] VSS P0[3] Figure 8. CY7C64355/CY7C64356 48-pin enCoRe V USB Device Table 3. 48-pin Part Pinout (QFN) Pin No. Type Pin Name Description 1 NC NC No connection 2 I/O P2[7] Digital I/O 3 I/O P2[5] Digital I/O, crystal out (Xout) 4 I/O P2[3] Digital I/O, crystal in (Xin) 5 I/O P2[1] Digital I/O 6 I/O P4[3] Digital I/O 7 I/O P4[1] Digital I/O 8 I/O P3[7] Digital I/O 9 I/O P3[5] Digital I/O 10 I/O P3[3] Digital I/O 11 I/O P3[1] Digital I/O 12 I/OHR P1[7] Digital I/O, I2C SCL, SPI SS 13 I/OHR P1[5] Digital I/O, I2C SDA, SPI MISO 14 NC NC No connection 15 NC NC No connection 16 I/OHR P1[3] Digital I/O, SPI CLK 17 I/OHR P1[1][5, 6] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI 18 Power VSS Supply ground 19 I/O D+ USB 20 I/O D– USB 21 Power VDD Supply voltage 22 I/OHR P1[0][5, 6] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 23 I/OHR P1[2] Digital I/O Notes 5. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 6. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *P Page 11 of 40 CY7C6431x CY7C6434x CY7C6435x Table 3. 48-pin Part Pinout (QFN) (continued) Pin No. Type Pin Name Description 24 I/OHR P1[4] Digital I/O, optional external clock input (EXTCLK) 25 I/OHR P1[6] Digital I/O 26 XRES Ext Reset Active high external reset with internal pull down 27 I/O P3[0] Digital I/O 28 I/O P3[2] Digital I/O 29 I/O P3[4] Digital I/O 30 I/O P3[6] Digital I/O 31 I/O P4[0] Digital I/O 32 I/O P4[2] Digital I/O 33 I/O P2[0] Digital I/O 34 I/O P2[2] Digital I/O 35 I/O P2[4] Digital I/O 36 I/O P2[6] Digital I/O 37 I/OH P0[0] Digital I/O 38 I/OH P0[2] Digital I/O 39 I/OH P0[4] Digital I/O 40 I/OH P0[6] Digital I/O 41 Power VDD Supply voltage 42 NC NC No connection 43 NC NC No connection 44 I/OH P0[7] Digital I/O 45 I/OH P0[5] Digital I/O 46 I/OH 47 Power 48 I/OH CP Power P0[3] Digital I/O VSS Supply ground P0[1] Digital I/O VSS Ensure the center pad is connected to ground LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Document Number: 001-12394 Rev. *P Page 12 of 40 CY7C6431x CY7C6434x CY7C6435x Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the following table. The enCoRe V device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Table 4. Register Conventions Convention Description R Read register or bits W Write register or bits L Logical register or bits C Clearable register or bits # Access is bit specific Document Number: 001-12394 Rev. *P Page 13 of 40 CY7C6431x CY7C6434x CY7C6435x Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE Addr (0, Hex) Access Name 00 RW EP1_CNT0 01 RW EP1_CNT1 02 EP2_CNT0 03 EP2_CNT1 PRT1DR 04 RW EP3_CNT0 PRT1IE 05 RW EP3_CNT1 06 EP4_CNT0 07 EP4_CNT1 PRT2DR 08 RW EP5_CNT0 PRT2IE 09 RW EP5_CNT1 0A EP6_CNT0 0B EP6_CNT1 PRT3DR 0C RW EP7_CNT0 PRT3IE 0D RW EP7_CNT1 0E EP8_CNT0 0F EP8_CNT1 PRT4DR 10 RW PRT4IE 11 RW 12 13 14 15 16 17 18 PMA0_DR 19 PMA1_DR 1A PMA2_DR 1B PMA3_DR 1C PMA4_DR 1D PMA5_DR 1E PMA6_DR 1F PMA7_DR 20 21 22 23 24 PMA8_DR 25 PMA9_DR 26 PMA10_DR 27 PMA11_DR 28 PMA12_DR SPI_TXR 29 W PMA13_DR SPI_RXR 2A R PMA14_DR SPI_CR 2B # PMA15_DR 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 30 USB_SOF0 31 R USB_SOF1 32 R USB_CR0 33 RW USBIO_CR0 34 # USBIO_CR1 35 # EP0_CR 36 # EP0_CNT0 37 # EP0_DR0 38 RW EP0_DR1 39 RW EP0_DR2 3A RW EP0_DR3 3B RW EP0_DR4 3C RW EP0_DR5 3D RW EP0_DR6 3E RW EP0_DR7 3F RW Gray fields are reserved; do not access these fields. Document Number: 001-12394 Rev. *P Addr (0, Hex) Access 40 # 41 RW 42 # 43 RW 44 # 45 RW 46 # 47 RW 48 # 49 RW 4A # 4B RW 4C # 4D RW 4E # 4F RW 50 51 52 53 54 55 56 57 58 RW 59 RW 5A RW 5B RW 5C RW 5D RW 5E RW 5F RW 60 61 62 63 64 RW 65 RW 66 RW 67 RW 68 RW 69 RW 6A RW 6B RW 6C RW 6D RW 6E RW 6F RW 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. Name PT0_CFG PT0_DATA1 PT0_DATA0 PT1_CFG PT1_DATA1 PT1_DATA0 PT2_CFG PT2_DATA1 PT2_DATA0 Addr (0, Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access Name I2C_XCFG I2C_XSTAT I2C_ADDR I2C_BP I2C_CP CPU_BP CPU_CP I2C_BUF CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR INT_CLR0 INT_CLR1 INT_CLR2 INT_MSK2 INT_MSK1 INT_MSK0 INT_SW_EN INT_VC RES_WDT RW RW RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (0, Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW R RW R R RW R RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RC W RL # # Page 14 of 40 CY7C6431x CY7C6434x CY7C6435x Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 Addr (1, Hex) Access Name 00 RW PMA4_RA 01 RW PMA5_RA 02 PMA6_RA 03 PMA7_RA PRT1DM0 04 RW PMA8_WA PRT1DM1 05 RW PMA9_WA 06 PMA10_WA 07 PMA11_WA PRT2DM0 08 RW PMA12_WA PRT2DM1 09 RW PMA13_WA 0A PMA14_WA 0B PMA15_WA PRT3DM0 0C RW PMA8_RA PRT3DM1 0D RW PMA9_RA 0E PMA10_RA 0F PMA11_RA PRT4DM0 10 RW PMA12_RA PRT4DM1 11 RW PMA13_RA 12 PMA14_RA 13 PMA15_RA 14 EP1_CR0 15 EP2_CR0 16 EP3_CR0 17 EP4_CR0 18 EP5_CR0 19 EP6_CRO 1A EP7_CR0 1B EP8_CR0 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 SPI_CFG 29 RW 2A 2B 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 USB_CR1 30 # 31 32 33 PMA0_WA 34 RW PMA1_WA 35 RW PMA2_WA 36 RW PMA3_WA 37 RW PMA4_WA 38 RW PMA5_WA 39 RW PMA6_WA 3A RW PMA7_WA 3B RW PMA0_RA 3C RW PMA1_RA 3D RW PMA2_RA 3E RW PMA3_RA 3F RW Gray fields are reserved; do not access these fields. Document Number: 001-12394 Rev. *P Addr (1, Hex) Access Name Addr (1, Hex) Access Name Addr (1, Hex) 40 RW 80 C0 41 RW 81 C1 42 RW 82 C2 43 RW 83 C3 44 RW 84 C4 45 RW 85 C5 46 RW 86 C6 47 RW 87 C7 48 RW 88 C8 49 RW 89 C9 4A RW 8A CA 4B RW 8B CB 4C RW 8C CC 4D RW 8D CD 4E RW 8E CE 4F RW 8F CF 50 RW 90 D0 51 RW 91 D1 52 RW 92 ECO_ENBUS D2 53 RW 93 ECO_TRIM D3 54 # 94 D4 55 # 95 D5 56 # 96 D6 57 # 97 D7 58 # 98 MUX_CR0 D8 59 # 99 MUX_CR1 D9 5A # 9A MUX_CR2 DA 5B # 9B MUX_CR3 DB 5C 9C IO_CFG1 DC 5D 9D OUT_P1 DD 5E 9E IO_CFG2 DE 5F 9F MUX_CR4 DF 60 A0 OSC_CR0 E0 61 A1 ECO_CFG E1 62 A2 OSC_CR2 E2 63 A3 VLT_CR E3 64 A4 VLT_CMP E4 65 A5 E5 66 A6 E6 67 A7 E7 68 A8 IMO_TR E8 69 A9 ILO_TR E9 6A AA EA 6B AB SLP_CFG EB 6C RW AC SLP_CFG2 EC 6D RW AD SLP_CFG3 ED 6E RW AE EE 6F RW AF EF 70 B0 F0 71 B1 F1 72 B2 F2 73 B3 F3 74 B4 F4 75 B5 F5 76 B6 F6 77 B7 CPU_F F7 78 B8 F8 79 B9 F9 7A BA IMO_TR1 FA 7B BB FB 7C BC FC 7D USB_MISC_CR BD RW FD 7E BE FE 7F BF FF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW # RW RW R W W RW RW RW RL RW Page 15 of 40 CY7C6431x CY7C6434x CY7C6435x Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up-to-date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.5V 5.5V Vdd Voltage Vdd Voltage lid ng Va rati n e io Op eg R SLIMO Mode = 01 SLIMO Mode = 00 SLIMO Mode = 10 3.0V 3.0V 5.7 MHz 24 MHz CPU Frequency Document Number: 001-12394 Rev. *P 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz IMO Frequency Page 16 of 40 CY7C6431x CY7C6434x CY7C6435x Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol Description [9] Conditions Min Typ Max Units Higher storage temperatures reduces data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85C degrades reliability. –55 +25 +125 °C –0.5 – +6.0 V TSTG Storage temperature VDD Supply voltage relative to VSS VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tristate VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any port pin ESD Electrostatic discharge voltage Human body model ESD LU Latch up current In accordance with JESD78 standard –25 – +50 mA 2000 – – V – – 200 mA Min Typ Max Units –40 – +85 °C 0 – +70 °C Operating Temperature Table 8. Operating Temperature Symbol Description Conditions TAI Ambient industrial temperature TAC Ambient commercial temperature TJI Operational industrial die temperature [10] The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 31. The user must limit the power consumption to comply with this requirement. –40 – +100 °C Operational commercial die temperature The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 31. The user must limit the power consumption to comply with this requirement. 0 – +85 °C TJC Notes 7. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 µsec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 8. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: • Bring the device out of sleep before powering down. • Assure that VDD falls below 100 mV before powering back up. • Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. • Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the enCoRe V Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1 V/ms. Document Number: 001-12394 Rev. *P Page 17 of 40 CY7C6431x CY7C6434x CY7C6435x DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC Chip Level Specifications Symbol Description Conditions Min Typ Max Units 3.0 – 5.5 V Conditions are VDD = 3.0 V, TA = 25 C, CPU = 24 MHz, No USB/I2C/SPI. – 2.9 4.0 mA Supply current, CPU = 12 MHz Conditions are VDD = 3.0 V, TA = 25 C, CPU = 12 MHz, No USB/I2C/SPI. – 1.7 2.6 mA IDD6,3 Supply current, CPU = 6 MHz Conditions are VDD = 3.0 V, TA = 25 C, CPU = 6 MHz, No USB/I2C/SPI. – 1.2 1.8 mA ISB1,3 Standby current with POR, LVD, and sleep VDD = 3.0 V, TA = 25 C, I/O regulator timer turned off. – 1.1 1.5 A ISB0,3 Deep sleep current VDD = 3.0 V, TA = 25 C, I/O regulator turned off. – 0.1 – A VDDUSB Operating voltage USB activity, USB regulator enabled 4.35 – 5.25 V IDD24,5 Supply current, CPU = 24 MHz Conditions are VDD = 5.0 V, TA = 25 C, CPU = 24 MHz, IMO = 24 MHz USB Active, No I2C/SPI. – 7.1 – mA IDD12,5 Supply current, CPU = 12 MHz Conditions are VDD = 5.0 V, TA = 25 C, CPU = 12 MHz, IMO = 24 MHz USB Active, No I2C/SPI. – 6.2 – mA IDD6,5 Supply current, CPU = 6 MHz Conditions are VDD = 5.0 V, TA = 25 C, CPU = 6 MHz, IMO = 24 MHz USB Active, No I2C/SPI – 5.8 – mA ISB1,5 Standby current with POR, LVD, and sleep VDD = 5.0 V, TA = 25 C, I/O regulator timer turned off. – 1.1 – A ISB0,5 Deep sleep current VDD = 5.0 V, TA = 25 C, I/O regulator turned off. – 0.1 – A VDDUSB Operating voltage USB activity, USB regulator bypassed 3.15 3.3 3.60 V VDD Operating voltage [7, 8] No USB activity. IDD24,3 Supply current, CPU = 24 MHz IDD12,3 Notes 9. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrade reliability. 10. The temperature rise from ambient to junction is package specific. See Package Handling on page 31. The user must limit the power consumption to comply with this requirement. Document Number: 001-12394 Rev. *P Page 18 of 40 CY7C6431x CY7C6434x CY7C6435x Table 10. DC Characteristics – USB Interface Symbol Min Typ Max Units USB D+ pull-up resistance With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 k Vohusb Static output high 2.8 – 3.6 V Volusb Static output low – – 0.3 V Vdi Differential input sensitivity 0.2 – – V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single-ended receiver threshold 0.8 – 2.0 V Cin Transceiver capacitance Iio High Z state data Line Leakage Rps2 PS/2 Pull Up Resistance Rext External USB Series Resistor Rusbi Description Conditions On D+ or D– line –10 In series with each USB pin – 50 pF – +10 A 3 5 7 k 21.78 22.0 22.22 ADC Electrical Specifications Table 11. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units Input VIN Input voltage range 0 – VREFADC V CIIN Input capacitance – – 5 pF RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500fF* 1/(400fF* 1/(300fF* Data Clock) Data Clock) Data Clock) Reference VREFADC ADC reference voltage 1.14 – 1.26 V 2.25 – 6 MHz Conversion Rate FCLK Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data Clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data Clock) – 23.4375 – ksps S10 10-bit sample rate Data Clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data Clock) – 5.859 – ksps RES Resolution Can be set to 8-, 9-, or 10-bit DNL Differential nonlinearity DC Accuracy INL Integral nonlinearity EOffset Offset error Egain Gain error 8 – 10 bits –1 – +2 LSB –2 – +2 LSB 0 3.2 19.2 LSB 10-bit resolution 0 12.8 76.8 LSB For any resolution –5 – +5 %FSR – 2.1 2.6 mA 8-bit resolution Power IADC Operating current PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) – 24 – dB PSRR (VDD < 3.0 V) – 30 – dB Document Number: 001-12394 Rev. *P Page 19 of 40 CY7C6431x CY7C6434x CY7C6435x DC General Purpose I/O Specifications Table 12 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and package specific temperature range. Typical parameters apply to 5 V and 3.3 V at 25 °C. These are for design guidance only. Table 12. 3.0 V and 5.5 V DC GPIO Specifications Symbol RPU VOH1 VOL Description Pull-up resistor High output voltage Port 2 or 3 pins High output voltage Port 2 or 3 Pins High output voltage Port 0 or 1 pins with LDO regulator disabled High output voltage Port 0 or 1 pins with LDO regulator disabled High output voltage Port 1 pins with LDO regulator enabled for 3 V Out High output voltage Port 1 pins with LDO regulator enabled for 3 V out High output voltage Port 1 pins with LDO enabled for 2.5 V out High output voltage Port 1 pins with LDO enabled for 2.5 V out High output voltage Port 1 pins with LDO enabled for 1.8 V out High output voltage Port 1 pins with LDO enabled for 1.8 V out Low output voltage VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Pin capacitance VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 VOH10 Document Number: 001-12394 Rev. *P Conditions Min 4 IOH < 10 µA, maximum of 10 mA source VDD – 0.2 current in all I/Os. IOH = 1 mA, maximum of 20 mA source VDD – 0.9 current in all I/Os. IOH < 10 µA, maximum of 10 mA source VDD – 0.2 current in all I/Os. Typ 5.6 – Max 8 – Units k V – – V – – V IOH = 5 mA, maximum of 20 mA source VDD – 0.9 current in all I/Os. – – V IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA 2.85 3.00 3.3 V IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA source current in all I/Os 2.20 – – V IOH < 10 A, VDD > 3.0 V, maximum of 20 mA source current in all I/Os 2.35 2.50 2.75 V IOH = 2 mA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os 1.90 – – V IOH < 10 A, VDD > 3.0 V, maximum of 20 mA source current in all I/Os 1.60 1.80 2.1 V IOH = 1 mA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os 1.20 – – V IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). – – 0.75 V – 2.0 – – 0.5 – – 80 0.001 1.7 0.8 – – 1 5 V V mV µA pF Package and pin dependent. Temp = 25 C. Page 20 of 40 CY7C6431x CY7C6434x CY7C6435x DC POR and LVD Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC POR and LVD Specifications Symbol VPPOR VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Conditions VDD value for PPOR trip[11] PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units – 2.82 2.95 V – – 2.85 2.95 3.06 –– 4.62 – – 2.92 3.02 3.13 – – 4.73 – – 2.99 3.09 3.20 – – 4.83 V V V V V V V V DC Programming Specifications Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Programming Specifications Symbol Description VDDIWRITE Supply voltage for flash write operations IDDP Supply current during programming or verify VILP Input low voltage during programming or verify Conditions See appropriate DC General Purpose I/O Specifications table VIHP Input high voltage during programming or verify IILP Input current when applying Vilp to P1[0] or P1[1] during programming or verify[12] IIHP Input current when applying Vihp to P1[0] or P1[1] during programming or verify[12] VOLP Output low voltage during programming or verify VOHP Output high voltage during programming or verify FlashENPB Flash write endurance[13] FlashDR Flash data retention[14] Min 1.71 Typ – Max 5.25 Units V – 5 25 mA – – VIL V 1.71 – VDDIWRITE + 0.3 V – – 0.2 mA – – 1.5 mA – – VSS + 0.75 V VDDIWRITE – 0.9 – VDDIWRITE V 50,000 10 – 20 – – Cycles Years Notes 11. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 12. Driving internal pull down resistor. 13. Erase/write cycles per block. 14. Following maximum Flash write cycles at Tamb = 55 °C and Tj = 70 °C. Document Number: 001-12394 Rev. *P Page 21 of 40 CY7C6431x CY7C6434x CY7C6435x AC Electrical Characteristics AC Chip Level Specifications The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. AC Chip Level Specifications Symbol Description FCPU Processing frequency[15] F32K1 Internal low-speed oscillator (ILO) frequency F32K_U ILO untrimmed frequency) F32K2 ILO frequency FIMO24 Internal main oscillator (IMO) stability for 24 MHz ± 5%(12) FIMO12 IMO stability for 12 MHz[16] FIMO6 IMO stability for 6 MHz[16] DCIMO Duty cycle of IMO DCILO ILO duty cycle SRPOWER_UP Power supply slew rate TXRST External reset pulse width at power-up TXRST2 External reset pulse width after power-up[17] Conditions Trimmed[16] Untrimmed After supply voltage is valid Applies after part has booted Min 5.7 19 13 13 22.8 Typ – 32 32 32 24 Max 25.2 50 82 82 25.2 Units MHz kHz kHz kHz MHz 11.4 5.7 40 40 – 1 12 6.0 50 50 – – 12.6 6.3 60 60 250 – MHz MHz % % V/ms ms 10 – – s Table 16. AC Characteristics – USB Data Timings Min Typ Max Units Tdrate Symbol Full speed data rate Description Average bit rate Conditions 11.97 12 12.03 MHz Tdjr1 Receiver data jitter tolerance To next transition –18.5 – 18.5 ns Tdjr2 Receiver data jitter tolerance To pair transition –9 – 9 ns Tudj1 Driver differential jitter To next transition –3.5 – 3.5 ns Tudj2 Driver differential jitter To pair transition –4.0 – 4.0 ns Tfdeop Source jitter for differential transition To SE0 transition –2 – 5 ns Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential transition – – 14 ns Min Typ Max Units Table 17. AC Characteristics – USB Driver Symbol Description Conditions Tr Transition rise time 50 pF 4 – 20 ns Tf Transition fall time 50 pF 4 – 20 ns TR Rise/fall time matching 90.00 – 111.1 % Vcrs Output signal crossover voltage 1.3 – 2.0 V Notes 15. VDD = 3.0 V and TJ = 85 C, CPU speed. 16. Trimmed for 3.3 V operation using factory trim values. 17. The minimum required XRES pulse length is longer when programming the device (see Table Document Number: 001-12394 Rev. *P 20 on page 24). Page 22 of 40 CY7C6431x CY7C6434x CY7C6435x AC General Purpose I/O Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency TRise23 Rise time, strong mode Ports 2, 3 Rise time, strong mode Ports 0, 1 Fall time, strong mode All Ports TRise01 TFall Conditions Normal strong mode, Ports 0, 1 VDD = 3.0 to 3.6 V, 10% - 90% VDD = 3.0 to 3.6 V, 10% - 90% VDD = 3.0 to 3.6 V, 10% - 90% Min – Typ – Max 12 Units MHz 15 – 80 ns 10 – 50 ns 10 – 50 ns Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TFall TRise23 TRise01 AC External Clock Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC External Clock Specifications Min Typ Max Units FOSCEXT Symbol Frequency Description 0.750 – 25.2 MHz – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – s Document Number: 001-12394 Rev. *P Conditions Page 23 of 40 CY7C6431x CY7C6434x CY7C6435x AC Programming Specifications Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. AC Programming Specifications Min Typ Max Units TRSCLK Symbol Rise time of SCLK Description Conditions 1 – 20 ns TFSCLK Fall time of SCLK 1 – 20 ns TSSCLK Data setup time to falling edge of SCLK 40 – – ns THSCLK Data hold time from falling edge of SCLK 40 – – ns FSCLK Frequency of SCLK 0 – 8 MHz TERASEB Flash erase time (Block) – – 18 ms TWRITE Flash block write time – – 25 ms TDSCLK1 Data out delay from falling edge of SCLK, VDD > 3.6 V – – 60 ns TDSCLK2 Data out delay from falling edge of SCLK 3.0 V < VDD < 3.6 V – – 85 ns TXRST3 External reset pulse width after power-up Required to enter programming mode when coming out of sleep 263 – – s Figure 12. Timing Diagram - AC Programming Cycle Document Number: 001-12394 Rev. *P Page 24 of 40 CY7C6431x CY7C6434x CY7C6435x AC I2C Specifications Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 21. AC Characteristics of the I2C SDA and SCL Pins Symbol Standard Mode Description Max Min Max Units 0 100 0 400 kHz THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – s TLOWI2C LOW period of the SCL clock 4.7 – 1.3 – s THIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – s TSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – s 0 – 0 – s FSCLI2C SCL clock frequency Min Fast Mode THDDATI2C Data hold time TSUDATI2C Data setup time 250 – 100[18] – ns TSUSTOI2C Setup time for STOP condition 4.0 – 0.6 – s 4.7 – 1.3 – s – – 0 50 ns TBUFI2C Bus free time between a STOP and START condition TSPI2C Pulse width of spikes are suppressed by the input filter Figure 13. Definition of Timing for Fast/Standard Mode on the SDA TLOWI2C TSUDATI2C THDSTAI2C I2C Bus TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Note 18. A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSUDAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. Document Number: 001-12394 Rev. *P Page 25 of 40 CY7C6431x CY7C6434x CY7C6435x Table 22. SPI Master AC Specifications Symbol FSCLK Description Conditions SCLK clock frequency Min Typ Max Units – – 6 MHz DC SCLK duty cycle – 50 – % TSETUP MISO to SCLK setup time 60 – – ns THOLD SCLK to MISO hold time 40 – – ns TOUT_VAL SCLK to MOSI valid time – – 40 ns TOUT_H SCLK to MOSI hold time 40 – – ns Figure 14. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSb MSb TOUT_SU TOUT_H MOSI (output) Figure 15. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-12394 Rev. *P LSb MSb TOUT_H MSb LSb Page 26 of 40 CY7C6431x CY7C6434x CY7C6435x Table 23. SPI Slave AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description Conditions 0.0469 – 12 MHz TLOW SCLK low time 41.67 – – ns THIGH SCLK high time 41.67 – – ns TSETUP MOSI to SCLK setup time 30 – – ns THOLD SCLK to MOSI hold time 50 – – ns TSS_MISO SS low to MISO valid – – 153 ns TSCLK_MISO SCLK to MISO valid – – 125 ns TSS_HIGH SS high time 50 – – ns TSS_CLK Time from SS low to first SCLK 2/FSCLK – – ns TCLK_SS Time from last SCLK to SS high 2/FSCLK – – ns Figure 16. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TCLK_SS TSS_CLK TSS_HIGH /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) Document Number: 001-12394 Rev. *P THOLD MSb LSb Page 27 of 40 CY7C6431x CY7C6434x CY7C6435x Figure 17. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSb TSETUP MOSI (input) Document Number: 001-12394 Rev. *P LSb THOLD MSb LSb Page 28 of 40 CY7C6431x CY7C6434x CY7C6435x Package Diagram This section illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the enCoRe V emulation tools and their dimensions, refer to the development kit. Packaging Dimensions Figure 18. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116 001-09116 *H Document Number: 001-12394 Rev. *P Page 29 of 40 CY7C6431x CY7C6434x CY7C6435x Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168 001-42168 *E Figure 20. 48-pin QFN (7 × 7 × 1.00 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191 001-13191 *G Document Number: 001-12394 Rev. *P Page 30 of 40 CY7C6431x CY7C6434x CY7C6435x Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade device reliability. Table 24. Package Handling Parameter Description Minimum Typical Maximum Unit TBAKETEMP Bake temperature – 125 See package label C TBAKETIME Bake time See package label – 72 hours Thermal Impedances Table 25. Thermal Impedances per Package Typical JA[19] 32.69 C / W 19.51 C / W 17.68 C / W Package 16-pin QFN 32-pin QFN[20] 48-pin QFN[20] Capacitance on Crystal Pins Table 26. Typical Package Capacitance on Crystal Pins Package Package Capacitance 32-pin QFN 3.2 pF 48-pin QFN 3.3 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 27. Solder Reflow Peak Temperature Package Minimum Peak Temperature [21] Maximum Peak Temperature 16-pin QFN 240 C 260 C 32-pin QFN 240 C 260 C 48-pin QFN 240 C 260 C Notes 19. TJ = TA + Power x JA. 20. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane. 21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-12394 Rev. *P Page 31 of 40 CY7C6431x CY7C6434x CY7C6435x Ordering Information Table 28. Ordering Code - Commercial Parts Ordering Code Package Information Flash SRAM No. of GPIOs (KB) (KB) Target Applications CY7C64315-16LKXC 16-pin QFN (3 × 3 mm) 16 1 11 Mid-tier Full-Speed USB dongle, Remote Control Host Module, Various CY7C64315-16LKXCT 16-pin QFN (Tape and Reel), (3 × 3 mm) 16 1 11 Mid-tier Full-Speed USB dongle, Remote Control Host Module, Various CY7C64316-16LKXC 16-pin QFN (3 × 3 mm) 32 2 11 Feature-rich Full-Speed USB dongle, Remote Control Host Module, Various CY7C64316-16LKXCT 16-pin QFN (Tape and Reel), (3 × 3 mm) 32 2 11 Feature-rich Full-Speed USB dongle, Remote Control Host Module, Various CY7C64343-32LQXC 32-pin QFN (5 × 5 mm) 8 1 25 Full-Speed USB mouse, Various CY7C64343-32LQXCT 32-pin QFN (Tape and Reel), (5 × 5 mm) 8 1 25 Full-Speed USB mouse, Various CY7C64345-32LQXC 32-pin QFN (5 × 5 mm) 16 1 25 Full-Speed USB mouse, Various CY7C64345-32LQXCT 32-pin QFN (Tape and Reel), (5 × 5 mm) 16 1 25 Full-Speed USB mouse, Various CY7C64355-48LTXC 48-pin QFN (7 × 7 mm) 16 1 36 Full-Speed USB keyboard, Various CY7C64355-48LTXCT 48-pin QFN (Tape and Reel), (7 × 7 mm) 16 1 36 Full-Speed USB keyboard, Various CY7C64356-48LTXC 48-pin QFN (7 × 7 mm) 32 2 36 Feature-rich Full-Speed USB keyboard, Various CY7C64356-48LTXCT 48-pin QFN (Tape and Reel), (7 × 7 mm) 32 2 36 Feature-rich Full-Speed USB keyboard, Various Table 29.Ordering Code - Industrial Parts Ordering Code Package Information Flash SRAM No. of GPIOs (KB) (KB) Target Applications CY7C64315-16LKXI 16-pin QFN, Industrial (3 × 3 mm) 16 1 11 Mid-tier Full-Speed USB dongle, Remote Control Host Module, Various CY7C64315-16LKXIT 16-pin QFN, Industrial (Tape and Reel), (3 × 3 mm) 16 1 11 Mid-tier Full-Speed USB dongle, Remote Control Host Module, Various CY7C64343-32LQXI 32-pin QFN, Industrial (5 × 5 × 0.55 mm) 8 1 25 Full-Speed USB mouse, Various CY7C64343-32LQXIT 32-pin QFN, Industrial (Tape and Reel), (5 × 5 mm) 8 1 25 Full-Speed USB mouse, Various CY7C64345-32LQXI 32-pin QFN, Industrial (5 × 5 mm) 16 1 25 Full-Speed USB mouse, Various CY7C64345-32LQXIT 32-pin QFN, Industrial (Tape and Reel), (5 × 5 mm) 16 1 25 Full-Speed USB mouse, Various CY7C64356-48LTXI 48-pin QFN, Industrial (7 × 7 mm) 32 2 36 Feature-rich Full-Speed USB keyboard, Various CY7C64356-48LTXIT 48-pin QFN, Industrial (Tape and Reel), (7 × 7 mm) 32 2 36 Feature-rich Full-Speed USB keyboard, Various Document Number: 001-12394 Rev. *P Page 32 of 40 CY7C6431x CY7C6434x CY7C6435x Ordering Code Definitions CY 7C64 XXX- XX XXX C/I (T) Tape and reel Temperature range: Commercial/Industrial Package type: LK/LQ/LT: QFN Pb-free Pin count: 16 = 16 pins, 32 = 32 pins, 48 = 48 pins Base part number Marketing Code: 7C64 = enCoRe Full-Speed USB Controller Company ID: CY = Cypress Document Number: 001-12394 Rev. *P Page 33 of 40 CY7C6431x CY7C6434x CY7C6435x Acronyms Acronym Document Conventions Description API Application Programming Interface CPU Central Processing Unit GPIO General Purpose I/O ICE In-Circuit Emulator ILO Internal Low speed Oscillator IMO Internal Main Oscillator I/O Input/Output LSb Least Significant Bit LVD Low Voltage Detect MSb Most Significant Bit POR Power On Reset PPOR Precision Power On Reset PSoC Programmable System-on-Chip SLIMO Slow IMO SRAM Static Random Access Memory Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure degree Celsius decibel femtofarad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volt Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal. Document Number: 001-12394 Rev. *P Page 34 of 40 CY7C6431x CY7C6434x CY7C6435x Appendix: Errata Document for enCoRe™ V – CY7C643xx This section describes the errata for the enCoRe V – CY7C643xx. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. CY7C643xx Errata Summary The following Errata item applies to the CY7C643xx data sheets. 1. Latch up susceptibility when maximum I/O sink current exceeded ■ PROBLEM DEFINITION P1[3], P1[6], and P1[7] pins are susceptible to latch up when the I/O sink current exceeds 25 mA per pin on these pins. ■ PARAMETERS AFFECTED LU – Latch up current. Per JESD78A, the maximum allowable latch up current per pin is 100 mA. Cypress internal specification is 200 mA latch up current limit. ■ TRIGGER CONDITIONS Latch up occurs when both the following conditions are met: A. The offending I/O is externally connected to a voltage higher than the I/O high state, causing a current to flow into the pin that exceeds 25 mA. B. A Port1 I/O (P1[1], P1[4], and P1[5] respectively) adjacent to the offending I/O is connected to a voltage lower than the I/O low state. This causes a signal that drops below Vss (signal undershoot) and a current greater than 200 mA to flow out of the pin. ■ SCOPE OF IMPACT The trigger conditions outlined in this item exceed the maximum ratings specified in the CY7C643xx data sheets. ■ WORKAROUND Add a series resistor > 300 to P1[3], P1[6], and P1[7] pins to restrict current to within latch up limits. ■ FIX STATUS This issue will be corrected in the next new silicon revision. 2. Does not meet USB 2.0 specification for D+ and D- rise/fall matching when supply voltage is under 3.3 V ■ PROBLEM DEFINITION Rising to falling rate matching of the USB D+ and D- lines has a corner case at lower supply voltages, such as those under 3.3 V. ■ PARAMETERS AFFECTED Rising to falling rate matching of the USB data lines. ■ TRIGGER CONDITION(S) Operating the VCC supply voltage at the low end of the chip’s specification (under 3.3 V) may cause a mismatch in the rising to falling rate. ■ SCOPE OF IMPACT This condition does not affect USB communications but could cause corner case issues with USB lines’ rise/fall matching specification. Signal integrity tests were run using the Cypress development kit and excellent eye was observed with supply voltage of 3.15 V. Document Number: 001-12394 Rev. *P Page 35 of 40 CY7C6431x CY7C6434x CY7C6435x Figure 21. Eye Diagram ■ ■ WORKAROUND Avoid the trigger condition by using lower tolerance voltage regulators. FIX STATUS This issue will not be corrected in the next new silicon revision. Document Number: 001-12394 Rev. *P Page 36 of 40 CY7C6431x CY7C6434x CY7C6435x Document History Page Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig. of Change Submission Date ** 626256 TYJ See ECN New data sheet. *A 735718 TYJ / ARI See ECN Filled in TBDs, added new block diagram, and corrected some values. Part numbers updated as per new specifications. *B 1120404 ARI See ECN Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device. Corrected the description to pin 29 on Table 2, the Typ/Max values for ISB0 on the DC chip-level specifications, the current value for the latch-up current in the Electrical Characteristics section, and corrected the 16 QFN package information in the Thermal Impedance table. Corrected some of the bulleted items on the first page. Added DC Characteristics–USB Interface table. Added AC Characteristics–USB Data Timings table. Added AC Characteristics–USB Driver table. Corrected Flash Write Endurance minimum value in the DC Programming Specifications table. Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table. Implemented new latest template. Include parameters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2, Tfeopt, Tfst. Added register map tables. Corrected a value in the DC Chip-Level Specifications table. *C 1241024 TYJ / ARI See ECN Corrected Idd values in Table 6 - DC Chip-Level Specifications. *D 1639963 AESA See ECN Post to www.cypress.com *E 2138889 TYJ / PYRS See ECN Updated Ordering Code table: - Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC - Added a new package type – “LTXC” for 48-QFN - Included Tape and Reel ordering code for 32-QFN and 48-QFN packages Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level Specifications” - IDD24: 2.15 to 3.1mA - IDD12: 1.45 to 2.0mA - IDD6: 1.1 to 1.5mA Added information on using P1[0] and P1[1] as the I2C interface during POR or reset events Document Number: 001-12394 Rev. *P Description of Change Page 37 of 40 CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig. of Change Submission Date Description of Change *F 2583853 TYJ / PYRS / HMT 10/10/08 Converted from Preliminary to Final Added operating voltage ranges with USB ADC resolution changed from 10-bit to 8-bit Rephrased battery monitoring clause in page 1 to include “with external components” Included ADC specifications table Included Voh7, Voh8, Voh9, Voh10 specs Flash data retention – condition added to Note [11] Input leakage spec changed to 25 nA max Under AC Char, Frequency accuracy of ILO corrected GPIO rise time for ports 0,1 and ports 2,3 made common AC Programming specifications updated Included AC Programming cycle timing diagram AC SPI specification updated Spec change for 32-QFN package Input Leakage Current maximum value changed to 1 A Updated VOHV parameter in Table 13 Updated thermal impedances for the packages Update Development Tools, add Designing with PSoC Designer. Edit, fix links and table format. Update TMs. *G 2653717 DVJA / PYRS 02/04/09 Updated Features, Functional Overview, Development Tools, and Designing with PSoC Designer sections with edits. Removed ‘GUI - graphical user interface’ from Document Conventions acronym table. Removed ‘O - Only a read/write register or bits’ in Table 4 Edited Table 8: removed 10-bit resolution information and corrected units column. Added package handling section Added 8K part ‘CY7C64343-32LQXC’ to Ordering Information. *H 2714694 DVJA / AESA 06/04/2009 Updated Block Diagram. Added Full Speed USB, 10-bit ADC, SPI, and I2C Slave sections. ADC Resolution changed from 8-bit to 10-bit Updated Table 9 DC Chip Level Specs Updated Table10 DC Char - USB Interface Updated Table 12 DC POR and LDV Specs Changed operating temperature from Commercial to Industrial Changed Temperature Range to Industrial: –40 to 85°C Figure 9: Changed minimum CPU Frequency from 750 kHz to 5.7 MHz Table 14: Removed “Maximum” from the FCPU description Ordering Information: Replaced ‘C’ with ‘I’ in all part numbers to denote Industrial Temp Range *I 2764460 DVJA / AESA 09/16/2009 Changed Table 12: ADC Specs Added F32K2 (Untrimmed) spec to Table 16: AC Chip level Specs Changed TRAMP spec to SRPOWER_UP in Table 16: AC Chip Level Specs Added Table 27: Typical Package Capacitance on Crystal Pins *J 2811903 DVJA 11/20/2009 Added USB-IF TID number in Features on page 1. Added Note 5 on page 18. Changed VIHP in Table 15 on page 22. Document Number: 001-12394 Rev. *P Page 38 of 40 CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig. of Change Submission Date Description of Change *K 2874274 KKU / PYRS 02/05/10 On page 4, changed the input voltage range from ‘0 V to 1.3 V’ to ‘0 V to VREFADC’. Added note for Operating Voltage in Table 9. Updated Register Map. Added SPI slave and master mode diagrams; in Table 22, changed TOUT_HIGH parameter to TOUT_H and modified description; in Table 23, updated TSS_CLK and TCLK_SS min values to 2/FSCLK and changed description of TSS_MISO. Added VddUSB parameter in Table 9. Updated package diagrams. *L 3028310 XUT 09/13/2010 Removed HPOR bit reference from DC POR and LVD Specifications Updated Development Tools and Designing with PSoC Designer. Added Ordering Code Definitions Moved Acronyms and Document Conventions to end of document. *M 3048308 NXZ 10/06/2010 Updated Features section as furnished in the CDT 74890 Updated datasheet as per new template All footnotes updated sequentially *N 3557631 CSAI 03/21/2012 Updated Getting Started. Updated Package Diagram. Updated in new template. *O 3912957 NXZ 03/06/2013 Updated Functional Overview (Updated The enCoRe V Core (Updated contents in the section), updated Full-Speed USB (Updated contents in the section)). Updated Register Mapping Tables (Updated Table 6 (Replaced “EC0_ENBUS” with “ECO_ENBUS” and replaced “EC0_TRIM” with “ECO_TRIM”)). Updated Package Diagram: spec 001-09116 – Changed revision from *F to *H. spec 001-42168 – Changed revision from *D to *E. spec 001-13191 – Changed revision from *F to *G. *P 3979449 ANKC Document Number: 001-12394 Rev. *P 04/23/2013 Added Appendix: Errata Document for enCoRe™ V – CY7C643xx. Page 39 of 40 CY7C6431x CY7C6434x CY7C6435x Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2013. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12394 Rev. *P Revised April 23, 2013 Page 40 of 40 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.