CYPRESS CY8C20234

CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
Low power CapSense® block
❐ Configurable capacitive sensing elements
❐ Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
■
Powerful Harvard-architecture processor
❐ M8C processor speeds running up to 12 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Industrial temperature range: –40 °C to +85 °C
■
Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 512-Bytes SRAM data storage
❐ Partial flash updates
❐ Flexible protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
■
■
Additional system resources
❐ Configurable communication speeds
• I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
2
❐ I C slave
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
Logic Block Diagram
Port 3
Precision, programmable clocking
❐ Internal ±5.0% 6- / 12-MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and sleep
■
Programmable pin configurations
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐ Up to 28 analog inputs on all GPIOs
❐ Configurable inputs on all GPIOs
❐ 20-mA sink current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
• 3.0 V, 20 mA total port 1 source current
• 5 mA strong drive mode on port 1 versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Comparator noise immunity
❐ Low-dropout voltage regulator for the analog array
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *N
•
198 Champion Court
Port 1
Port 0
Config LDO
System Bus
Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator, and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■
Port 2
PSoC
CORE
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
I2C Slave/SPI
Master-Slave
CapSense
Block
Analog
Ref.
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2011
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Contents
PSoC® Programmable System-on-Chip™ ..................... 1
Features ............................................................................. 1
Logic Block Diagram ........................................................ 1
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
CapSense Analog System .......................................... 3
Additional System Resources ..................................... 3
PSoC Device Characteristics ...................................... 4
Getting Started .................................................................. 4
Application Notes ........................................................ 4
Development Kits ........................................................ 4
Training ....................................................................... 4
Cypros Consultants ..................................................... 4
Solutions Library .......................................................... 4
Technical Support ....................................................... 4
Development Tools .......................................................... 5
PSoC Designer Software Subsystems ........................ 5
In-Circuit Emulator ....................................................... 5
Designing with PSoC Designer ....................................... 6
Select Components ..................................................... 6
Configure Components ............................................... 6
Organize and Connect ................................................ 6
Generate, Verify, and Debug ....................................... 6
Pin Information ................................................................. 7
8-Pin SOIC Pinout ....................................................... 7
16-Pin SOIC Pinout ..................................................... 8
48-Pin OCD Part Pinout .............................................. 9
16-Pin Part Pinout ..................................................... 11
24-Pin Part Pinout ..................................................... 12
32-Pin Part Pinout ..................................................... 13
28-Pin Part Pinout ..................................................... 15
30-Ball Part Pinout .................................................... 16
Document Number: 001-05356 Rev. *N
Electrical Specifications ................................................ 17
Absolute Maximum Ratings ....................................... 17
Operating Temperature ............................................. 18
DC Electrical Characteristics ..................................... 18
AC Electrical Characteristics ........................................ 23
Packaging Dimensions .................................................. 30
Thermal Impedances ................................................. 35
Solder Reflow Peak Temperature ............................. 35
Development Tool Selection ......................................... 36
Software .................................................................... 36
Development Kits ...................................................... 36
Evaluation Tools ............................................................. 36
Device Programmers ................................................. 37
Accessories (Emulation and Programming) .............. 37
Ordering Information ...................................................... 38
Ordering Code Definitions ............................................. 38
Acronyms ........................................................................ 39
Acronyms Used ......................................................... 39
Reference Documents .................................................... 39
Document Conventions ................................................. 40
Units of Measure ....................................................... 40
Numeric Conventions ................................................ 40
Glossary .......................................................................... 40
Document History Page ................................................. 45
Sales, Solutions, and Legal Information ...................... 47
Worldwide Sales and Design Support ....................... 47
Products .................................................................... 47
PSoC Solutions ......................................................... 47
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PSoC Functional Overview
The PSoC architecture for this device family, as shown in
Figure 1, consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose I/O (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.
Figure 1. Analog System Block Diagram
ID AC
Analog Global Bus
The PSoC family consists of many Programmable
System-on-Chips with On-Chip Controller devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
Vr
R eferenc e
Buffer
C om parator
Mux
PSoC Core
Mux
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO , and ILO.
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a two MIPS, 8-bit
Harvard-architecture microprocessor.
C SC LK
IMO
The Analog System consists of the CapSense PSoC block and
an internal 1.8 V analog reference. Together they support capacitive sensing of up to 28 inputs.
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Document Number: 001-05356 Rev. *N
R efs
C ap Sens e C ounters
System Resources provide additional capability such as a
configurable I2C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
CapSense Analog System
C internal
C apSens e
C lock Selec t
R elaxation
O s c illator
(RO)
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces such as sliders and
touch pads
■
Chip-wide mux that enables analog input from any I/O pin
■
Crosspoint connection between any I/O pin combinations
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Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource follow:
■
The I2C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
Low voltage detection (LVD) interrupts signal the application of
falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.8 V reference provides an absolute reference for
capacitive sensing.
■
The 5 V maximum input, 3 V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
CY8C29x66
up to 64
CY8C28xxx
up to 44
CY8C27x43
up to 44
CY8C24x94
CY8C24x23A
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
4
16
up to 12
4
up to 3
up to 12
up to 44
up to 4
2
8
up to 12
4
up to 56
1
4
up to 48
up to 24
1
4
up to 12
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
4
12
2K
32 K
up to 6
up to
12 + 4[1]
1K
16 K
4
12
256
16 K
2
2
6
1K
16 K
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[1]
1K
16 K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[1]
512
8K
[1]
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4
512
CY8C21x23
up to 16
1
4
up to 8
0
2
4[1]
256
4K
CY8C20x34
up to 28
0
0
up to 28
0
0
3[1,2]
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[1,2]
up to
2K
up to
32 K
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the
PSoC integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming information, see the Technical Reference Manual for this PSoC
device.
Development Kits
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at http://www.cypress.com.
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
Application Notes
Cypros Consultants
Application notes are an excellent introduction to the wide variety
of possible PSoC designs and are available at
http://www.cypress.com.
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to http://www.cypress.com and refer to
CYPros Consultants.
Notes
1. Limited analog functionality
2. Two analog blocks and one CapSense®.
Document Number: 001-05356 Rev. *N
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Solutions Library
Technical Support
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE). Choose a base device to work with and then
select different onboard analog and digital components called
user modules that use the PSoC blocks. Examples of user
modules are ADCs, DACs, Amplifiers, and Filters. Configure the
user modules for your chosen application and connect them to
each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration enables changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-05356 Rev. *N
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers enable assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products enable
you to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands enable the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
enables the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Generate, Verify, and Debug
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that enable you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in datasheets that are viewed directly in PSoC
Designer. These datasheets explain the internal operation of the
component and provide performance specifications. Each
datasheet describes the use of each user module parameter or
driver property, and other information you may need to successfully implement your design.
Document Number: 001-05356 Rev. *N
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
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Pin Information
This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and CY8C20634 PSoC device
pins and pinout configurations.
The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin
(labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable
of Digital I/O.
8-Pin SOIC Pinout
Figure 2. CY8C20134-12SXI 8-Pin SOIC Pinout
VSS
A, I, P0[5]
AI,
P0[1]
A, I, P0[3]
AI,
SCL,P1[1]
P1[7]
I2CI2C
SCL,
AI, I2C SDA, P1[5]
Vss
1
8
2
7
SOIC
6
3
5
4
V
DD
Vdd
P2[2],AI
P0[4], A,
I
P1[0],
P0[2],I2C
A,SDA,
I DATA *, AI
P1[1],
SCL,
CLK*, AI
P1[0],I2CI2C
SDA
Table 2. Pin Definitions – CY8C20134 8-Pin (SOIC)
Pin No.
Digital
1
Power
2
I/O
3
I/O
Analog
Name
Description
VSS
Ground connection
I
P0[1]
Analog column mux input, integrating input
I
P1[7]
I2C serial clock(SCL)
4
I/O
I
P1[5]
I2C serial data (SDA)
5
I/O
I
P1[1]
I2C serial clock(SCL), ISSP-SCLK
6
I/O
I
P1[0]
I2C serial data (SDA), ISSP-SDATA
7
I/O
I
P2[2]
Analog column mux input
8
Power
VDD
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *N
Supply voltage
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16-Pin SOIC Pinout
Figure 3. CY8C20234-12SXI 16-Pin SOIC Pinout
AI,
A, I,P0[7]
P0[7]
AI,P0[3]
A,
I, P0[5]
AI,P0[1]
A,
I, P0[3]
A,
I, P0[1]
AI,P2[5]
AI,P2[1]
SMP
AI, I2C SCL, SPI SS, P1[7]
Vss
AI, I2C SDA, SPI I2C
MISO,
SCL,P1[5]
P1[1]
AI, SPI CLK, P1[3]
Vss
1
2
3
4
5
6
7
8
SOIC
16
15
14
13
12
11
10
9
VDD
Vdd
P0[4],AI
P0[6],
A, I
P0[4],
XRESA, I
P0[2],
A, I
P1[4],EXTCLK,AI
P1[2],AI
P0[0],
A, I
P1[0],I2C
SDA, DATA*, AI
P1[4],
EXTCLK
P1[2]
Vss
P1[0],
I2CSDA
P1[1],I2C
SCL, SPI MOSI, CLK*,AL
Table 3. Pin Definitions – CY8C20234 16-Pin (SOIC)
Pin No.
Digital
Analog
Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I
P0[3]
Analog column mux input and column input, integrating input
3
I/O
I
P0[1]
Analog column mux input, integrating input
4
I/O
I
P2[5]
Analog column mux input
5
I/O
I
P2[1]
Analog column mux input
6
I/O
I
P1[7]
I2C serial clock(SCL),SPI SS
7
I/O
I
P1[5]
I2C serial data (SDA),SPI MISO
8
I/O
I
P1[3]
Analog column mux input,SPI CLK
9
I/O
I
P1[1]
I2C serial clock(SCL), ISSP-SCLK,SPI MOSI
10
Power
11
I/O
12
13
14
VSS
Ground connection
I
P1[0]
I2C serial data (SDA), ISSP-SDATA
I/O
I
P1[2]
Analog column mux input
I/O
I
P1[4]
Analog column mux input ,optional external clock input(EXTCLK)
I/O
I
XRES
XRES
15
I/O
I
P0[4]
Analog column mux input
16
Power
VDD
Supply voltage
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *N
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48-Pin OCD Part Pinout
The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
NC
NC
38
37
OCDO
Vdd
P0[6], AI
NC
OCDE
42
41
40
39
P0[7], AI
43
P0[5], AI
45
44
46
P0[4],
P0[2],
P0[0],
P2[6],
P2[4],
P2[2],
AI
AI
AI
AI
AI
AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P1[4], EXTCLK, AI
NC
NC
22
23
24
NC
AI, P1[2]
20
21
36
35
34
33
32
31
30
29
28
27
26
25
AI, DATA*, I2C SDA, P1[0]
HCLK
18
19
CCLK
17
15
16
OCD QFN
AI, SPI CLK, P1[3]
13
14
3
4
5
6
7
8
9
10
11
12
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
1
2
NC
NC
NC
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
NC
NC
48
47
NC
Vss
P0[3], AI
Figure 4. CY8C20000 48-Pin OCD PSoC Device
Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) [4]
Pin No.
Digital
Analog
1
Name
NC
Description
No connection
2
I/O
I
P0[1]
3
I/O
I
P2[7]
4
I/O
I
P2[5]
5
I/O
I
P2[3]
6
I/O
I
P2[1]
7
I/O
I
P3[3]
8
I/O
I
P3[1]
9
IOH
I
P1[7]
I2C SCL, SPI SS
10
IOH
I
P1[5]
I2C SDA, SPI MISO
11
I/O
I
P0[1]
12
NC
No connection
13
NC
No Connection
14
NC
No Connection
15
NC
SPI CLK
16
IOH
I
P1[3]
CLK[3], I2C SCL, SPI MOSI
17
IOH
I
P1[1]
Ground connection
18
Power
VSS
OCD CPU clock output
19
CCLK
OCD high speed clock output
20
HCLK
DATA[3], I2C SDA
Document Number: 001-05356 Rev. *N
Page 9 of 47
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CY8C20434, CY8C20534, CY8C20634
Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) [4]
Pin No.
Digital
Analog
Name
21
IOH
I
P1[0]
22
IOH
I
Description
P1[2]
No connection
23
NC
No connection
24
NC
No connection
25
NC
Optional external clock input (EXTCLK)
26
IOH
I
P1[4]
27
IOH
I
P1[6]
28
Input
29
I/O
I
P3[0]
30
I/O
I
P3[2]
31
I/O
I
P2[0]
32
I/O
I
P2[2]
33
I/O
I
P2[4]
34
I/O
I
P2[6]
35
I/O
I
P0[0]
36
I/O
I
P0[2]
Active high external reset with internal pull-down
XRES
37
NC
No connection
38
NC
No connection
39
NC
No connection
40
I/O
41
Power
I
P0[6]
Analog bypass
VDD
Supply voltage
42
OCDO
OCD odd data output
43
OCDE
OCD even data I/O
44
I/O
I
P0[7]
45
I/O
I
P0[5]
46
I/O
I
P0[3]
Integrating Input
47
Power
VSS
Ground connection
NC
No connection
VSS
Center pad is connected to ground
48
CP
Power
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *N
Page 10 of 47
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CY8C20434, CY8C20534, CY8C20634
16-Pin Part Pinout
14
13
P0[1], AI
16
15
12
9
8
5
6
7
QFN
11
(Top View)10
AI, SPI CLK, P1[3]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
1
2
3
4
P0[4], AI
XRES
P1[4], AI, EXTCLK
P1[2], AI
CLK, I2C SCL, SPI MOSI P1[1]
VSS
AI, DATA, I2C SDA, P1[0]
AI, P2[5]
AI, P2[1]
P0[3], AI
P0[7], AI
VDD
Figure 5. CY8C20234 16-Pin PSoC Device
Table 5. Pin Definitions – CY8C20234 16-Pin (QFN no e-pad)
Pin No.
Type
Digital
Analog
Name
Description
1
I/O
I
P2[5]
2
I/O
I
P2[1]
3
IOH
I
P1[7]
I2C SCL, SPI SS
4
IOH
I
P1[5]
I2C SDA, SPI MISO
5
IOH
I
P1[3]
SPI CLK
6
IOH
I
P1[1]
CLK[3], I2C SCL, SPI MOSI
7
Power
VSS
Ground connection
8
IOH
I
P1[0]
DATA[3], I2C SDA
9
IOH
I
P1[2]
10
IOH
I
P1[4]
Optional external clock input (EXTCLK)
11
Input
XRES
Active high external reset with internal pull-down
12
I/O
13
Power
14
I/O
I
P0[7]
15
I/O
I
P0[3]
16
I/O
I
P0[1]
I
P0[4]
VDD
Supply voltage
Integrating Input
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
3. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the PSoC Technical Reference Manual for details.
Document Number: 001-05356 Rev. *N
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24-Pin Part Pinout
P0[1], AI
24
23
22
21
20
19
18
17
16
15
14
13
7
8
9
10
11
12
1
2
QFN
3
4 (Top View)
5
6
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
P1[6], AI
AI, CLK*, I2C SCL
SPI MOSI, P1[1]
NC
VSS
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
P0[3], AI
P0[5], AI
P0[7], AI
VDD
P0[6], AI
Figure 6. CY8C20334 24-Pin PSoC Device
Table 6. Pin Definitions – CY8C20334 24-Pin (QFN) [4]
1
2
3
4
Type
Digital
Analog
I/O
I
I/O
I
I/O
I
IOH
I
P2[5]
P2[3]
P2[1]
P1[7]
5
IOH
I
P1[5]
6
7
IOH
IOH
I
I
P1[3]
P1[1]
8
9
10
Power
IOH
I
NC
VSS
P1[0]
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CP
IOH
IOH
IOH
Input
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Power
Pin No.
I
I
I
I
I
I
I
I
I
I
I
I
Name
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
P0[7]
P0[5]
P0[3]
P0[1]
VSS
Description
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK[3], I2C SCL, SPI MOSI
No Connection
Ground Connection
DATA[3], I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Analog bypass
Supply voltage
Integrating input
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Document Number: 001-05356 Rev. *N
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32-Pin Part Pinout
AI, P3[1]
SPI SS, P1[7]
1
2
3
4
5
6
7
8
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
AI, I2C SCL
QFN
(Top View)
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
32
31
30
29
28
27
26
25
Vss
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
Figure 7. CY8C20434 32-Pin PSoC Device
Table 7. Pin Definitions – CY8C20434 32-Pin (QFN) [4]
Pin No.
Type
Analog
I
I
I
I
I
I
I
I
Name
1
2
3
4
5
6
7
8
Digital
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
9
IOH
I
P1[5]
10
11
IOH
IOH
I
I
P1[3]
P1[1]
12
13
Power
IOH
I
VSS
P1[0]
14
15
16
17
18
19
IOH
IOH
IOH
Input
I/O
I/O
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
Description
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK[3], I2C SCL, SPI MOSI
Ground Connection
DATA[3], I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Note
4. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
floated and not connected to any other signal.
Document Number: 001-05356 Rev. *N
Page 13 of 47
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CY8C20434, CY8C20534, CY8C20634
Table 7. Pin Definitions – CY8C20434 32-Pin (QFN) [4]
Type
Name
Description
Digital
Analog
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
I/O
I
P0[0]
25
I/O
I
P0[2]
26
I/O
I
P0[4]
27
I/O
I
P0[6]
Analog bypass
28
Power
VDD
Supply voltage
29
I/O
I
P0[7]
30
I/O
I
P0[5]
31
I/O
I
P0[3]
Integrating input
32
Power
VSS
Ground connection
CP
Power
VSS
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA high output drive.
Pin No.
Document Number: 001-05356 Rev. *N
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28-Pin Part Pinout
Figure 8. CY8C20534 28-Pin PSoC Device
AI P0[7]
AI P0[5]
AI P0[3]
AI P0[1]
AI P2[7]
AI P2[5]
AI P2[3]
AI P2[1]
Vss
AI, I2C SCL P1[7]
AI, I2C SDA P1[5]
AI P1[3]
AI, I2C SCL P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6] AI
P0[4] AI
P0[2] AI
P0[0] AI
P2[6] AI
P2[4] AI
P2[2] AI
P2[0] AI
XRES
P1[6] AI
P1[4] EXTCLK, AI
P1[2] AI
P1[0] I2C SDA, AI
Table 8. Pin Definitions – CY8C20534 28-Pin (SSOP)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Type
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
VSS
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output, integrating input
Analog column mux input, integrating input
Direct switched capacitor block input
Direct switched capacitor block input
Ground connection
I2C serial clock (SCL)
I2C serial data (SDA)
I2C serial clock (SCL), ISSP-SCLK[3]
Ground connection
I2C serial data (SDA), ISSP-SDATA[3]
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Direct switched capacitor block input
Direct switched capacitor block input
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *N
Page 15 of 47
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30-Ball Part Pinout
Figure 9. CY8C20634 30-Ball PSoC Device
5
4
3
2
1
A
B
C
D
E
F
Table 9. 30-Ball Part Pinout (WLCSP)
Pin No.
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
Digital
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
I/O
Input
IOH
IOH
IOH
I/O
Power
IOH
IOH
IOH
IOH
Type
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
VDD
P0[6]
P0[4]
P0[3]
P2[7]
P0[2]
P0[0]
P2[6]
P0[5]
P0[1]
P2[4]
P2[2]
P3[1]
P0[7]
P2[1]
P2[0]
P3[0]
P3[2]
P1[1]
P2[3]
XRES
P1[6]
P1[4]
P1[5]
P2[5]
VSS
P1[2]
P1[0]
P1[3]
P1[7]
Description
Supply voltage
Analog bypass
Integrating input
CLK[3], I2C SCL, SPI MOSI
Active high external reset with internal pull-down
Optional external clock input (EXTCLK)
I2C SDA, SPI MISO
Ground connection
DATA[3], I2C SDA
SPI CLK
I2C SCL, SPI SS
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *N
Page 16 of 47
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CY8C20434, CY8C20534, CY8C20634
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and
CY8C20634 PSoC devices. For the latest electrical specifications, check the most recent datasheet by visiting the web at
http://www.cypress.com.
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C as specified, except where mentioned.
Refer to Table 19 on page 23 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 10. Voltage versus CPU Frequency and IMO Frequency Trim Options
5.25
5.25
SLIMO SLIMO SLIMO
Mode=1 Mode=1 Mode=0
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
pe gio
Re
O
4.75
3.60
3.00
3.00
2.70
2.70
2.40
2.40
750 kHz
3 MHz
6 MHz
SLIMO SLIMO
Mode=1 Mode=0
750 kHz
12 MHz
3 MHz
SLIMO
Mode=1
SLIMO
Mode=0
6 MHz
12 MHz
IMO Frequency
CPU Frequency
Absolute Maximum Ratings
Table 10. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
TBAKETEMP
Bake temperature
tBAKETIME
Bake time
TA
VDD
VIO
VIOZ
IMIO
ESD
LU
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
DC voltage applied to tri-state
Maximum current into any port pin
Electro static discharge voltage
Latch-up current
Document Number: 001-05356 Rev. *N
Min
–55
Typ
25
Max
+100
Units
°C
–
125
°C
See package
label
–40
–0.5
VSS – 0.5
VSS – 0.5
–25
2000
–
–
See package
label
72
Hours
–
–
–
–
–
–
–
+85
+6.0
VDD + 0.5
VDD + 0.5
+50
–
200
°C
V
V
V
mA
V
mA
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25 °C ±
25 °C. Extended duration
storage temperatures above
65 °C degrades reliability.
Human body model ESD.
Page 17 of 47
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Operating Temperature
Table 11. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Min
–40
–40
Typ
–
–
Max
+85
+100
Units
°C
°C
Notes
The temperature rise from
ambient to junction is package
specific. See Table 16 on
page 21. The user must limit
the power consumption to
comply with this requirement.
DC Electrical Characteristics
DC Chip Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0V to 3.6V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 12. DC Chip Level Specifications
Symbol
VDD
IDD12
Description
Supply voltage
Supply current, IMO = 12 MHz
Min
2.40
–
Typ
–
1.5
Max
5.25
2.5
Units
V
mA
IDD6
Supply current, IMO = 6 MHz
–
1
1.5
mA
ISB27
Sleep (mode) current with POR, LVD, Sleep
timer, WDT, and internal slow oscillator active.
Mid temperature range.
Sleep (mode) current with POR, LVD, Sleep
timer, WDT, and internal slow oscillator active.
–
2.6
4
µA
Notes
See Table 16 on page 21.
Conditions are VDD = 3.0 V,
TA = 25 °C, CPU = 12 MHz.
Conditions are VDD = 3.0 V,
TA = 25 °C, CPU = 6 MHz
VDD = 2.55 V, 0 °C TA  40 °C
–
2.8
5
µA
VDD = 3.3 V, –40 °C TA  85 °C
ISB
DC GPIO Specifications
Unless otherwise noted, Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, and 2.7 V at 25 °C. These are for design guidance only.
Table 13. 5-V and 3.3-V DC GPIO Specifications
Symbol
RPU
VOH1
VOH2
VOH3
VOH4
VOH5
VOH6
VOH7
VOH8
Description
Pull-up resistor
High output voltage
Port 0, 2, or 3 pins
High output voltage
Port 0, 2, or 3 pins
High output voltage
Port 1 pins with LDO regulator disabled
High output voltage
Port 1 pins with LDO regulator disabled
High output voltage
Port 1 pins with 3.0 V LDO regulator enabled
High output voltage
Port 1 pins with 3.0 V LDO regulator enabled
High output voltage
Port 1 pins with 2.4 V LDO regulator enabled
High output voltage
Port 1 pins with 2.4 V LDO regulator enabled
Document Number: 001-05356 Rev. *N
Min
4
VDD – 0.2
Typ
5.6
–
Max
8
–
Units
k
V
VDD – 0.9
–
–
V
VDD – 0.2
–
–
V
VDD – 0.9
–
–
V
2.7
3.0
3.3
V
2.2
–
–
V
2.1
2.4
2.7
V
2.0
–
–
V
Notes
IOH  10 µA, VDD  3.0 V, maximum
of 20 mA source current in all I/Os.
IOH = 1 mA, VDD  3.0 V, maximum of
20 mA source current in all I/Os.
IOH < 10 µA, VDD  3.0 V, maximum
of 10 mA source current in all I/Os.
IOH = 5 mA, VDD  3.0 V, maximum of
20 mA source current in all I/Os.
IOH < 10 µA, VDD  3.1 V, maximum
of 4 I/Os all sourcing 5 mA.
IOH = 5 mA, VDD  3.1 V, maximum of
20 mA source current in all I/Os.
IOH < 10 µA, VDD  3.0 V , maximum
of 20 mA source current in all I/Os.
IOH < 200 µA, VDD  3.0 V, maximum
of 20 mA source current in all I/Os.
Page 18 of 47
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Table 13. 5-V and 3.3-V DC GPIO Specifications
Symbol
VOH9
Description
High output voltage
Port 1 pins with 1.8 V LDO regulator enabled
Min
1.6
Typ
1.8
Max
2.0
Units
V
VOH10
High output voltage
Port 1 pins with 1.8 V LDO regulator enabled
1.5
–
–
V
VOL
Low output voltage
–
–
0.75
V
IOH
High level source current
–
–
20
mA
IOH2
High level source current port 0, 2, or 3 pins
1
–
–
mA
IOH4
High level source current port 1 Pins with LDO
regulator disabled
5
–
–
mA
IOL
Low level sink current
20
–
–
mA
VIL
VIH
VH
IIL
CIN
Input low voltage
Input high voltage
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins as input
–
2.0
–
–
0.5
–
–
140
1
1.7
0.8
–
–
–
5
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Document Number: 001-05356 Rev. *N
Notes
IOH < 10 µA
3.0V  VDD  3.6 V
0 °C TA 85 °C
Maximum of 20 mA source current in
all I/Os.
IOH < 100 µA.
3.0V  VDD  3.6 V.
0 °C TA 85 °C.
Maximum of 20 mA source current in
all I/Os.
IOL = 20 mA, VDD > 3.0 V, maximum
of 60 mA sink current on even port
pins (for example, P0[2] and P1[4])
and 60 mA sink current on odd port
pins (for example, P0[3] and P1[5]).
VOH = VDD – 0.9. See the limitations
of the total current in the Notes for
VOH.
VOH = VDD – 0.9, for the limitations of
the total current and IOH at other VOH
levels, see the Notes for VOH.
VOH = VDD – 0.9, for the limitations of
the total current and IOH at other VOH
levels, see the Notes for VOH.
VOL = 0.75 V, see the limitations of the
total current in the Notes for VOL
3.6 V  VDD  5.25 V
3.6 V  VDD  5.25 V
Gross tested to 1 µA
Package and pin dependent
Temperature = 25 °C
Package and pin dependent
Temperature = 25 °C
Page 19 of 47
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Table 14. 2.7-V DC GPIO Specifications
Symbol
RPU
VOH1
VOH2
VOL
Description
Pull-up resistor
High output voltage
Port 1 pins with LDO regulator disabled
High output voltage
Port 1 pins with LDO regulator disabled
Low output voltage
Min
4
VDD – 0.2
Typ
5.6
–
Max
8
–
Units
k
V
VDD – 0.5
–
–
V
–
–
0.75
V
IOH2
High level source current port 1 Pins with LDO
regulator disabled
2
–
–
mA
IOL
Low level sink current
10
–
–
mA
VOLP1
Low output voltage port 1 pins
–
–
0.4
V
VIL
VIH1
VIH2
VH
IIL
CIN
Input low voltage
Input high voltage
Input high voltage
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins as input
–
1.4
1.6
–
–
0.5
–
–
–
60
1
1.7
0.75
–
–
–
–
5
V
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Notes
IOH < 10 µA, maximum of 10 mA
source current in all I/Os.
IOH = 2 mA, maximum of 10 mA source
current in all I/Os.
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5]).
VOH = VDD – 0.5, for the limitations of
the total current and IOH at other VOH
levels see the notes for VOH.
VOH = .75 V, see the limitations of the
total current in the note for VOL
IOL = 5 mA
Maximum of 50 mA sink current on
even port pins (for example, P0[2] and
P3[4]) and 50 mA sink current on odd
port pins (for example, P0[3] and
P2[5]).
2.4 V  VDD  3.6 V
2.4 V  VDD  3.6 V
2.4 V  VDD  2.7 V
2.7 V  VDD  3.6 V
Gross tested to 1 µA
Package and pin dependent
Temperature = 25 °C
Package and pin dependent
Temperature = 25 °C
DC Analog Mux Bus Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 15. DC Analog Mux Bus Specifications
Symbol
RSW
Description
Switch resistance to common analog bus
Document Number: 001-05356 Rev. *N
Min
–
Typ
–
Max
400
800
Units


Notes
VDD  2.7 V
2.4 V VDD 2.7 V
Page 20 of 47
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DC POR and LVD Specifications
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 16. DC POR and LVD Specifications
Symbol
VPPOR0
VPPOR1
VPPOR2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Description
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
–
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
2.39
2.54
2.75
2.85
2.96
–
–
4.52
2.45
2.71
2.92
3.02
3.13
–
–
4.73
2.51[3]
2.78[4]
2.99[5]
3.09
3.20
–
–
4.83
V
V
V
V
V
V
V
V
Notes
VDD is greater than or equal to 2.5 V
during startup, reset from the XRES pin,
or reset from watchdog.
Notes
3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.
6. A maximum of 36 × 50,000 block endurance cycles is allowed. This is balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks
of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever
sees more than 50,000 cycles).
7. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V and
4.75 V to 5.25 V.
Document Number: 001-05356 Rev. *N
Page 21 of 47
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DC Programming Specifications
Table 17 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash endurance and retention specifications with the
use of the EEPROM User Module are valid only within the range: 25 °C +/–20C during the Flash Write operation. Reference the
EEPROM User Module datasheet instructions for EEPROM flash write requirements outside of the 25 °C +/–20 °C temperature
window.
Table 17. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
VDDLV
Low VDD for verify
2.4
2.5
2.6
VDDHV
High VDD for verify
5.1
5.2
5.3
VDDIWRITE
Supply voltage for flash write operation
2.7
–
5.25
IDDP
VILP
VIHP
Supply current during programming or verify
Input low voltage during programming or verify
Input high voltage during programming or
verify
Input current when applying VILP to P1[0] or
P1[1] during programming or verify
Input current when applying VIHP to P1[0] or
P1[1] during programming or verify
Output low voltage during programming or
verify
Output high voltage during programming or
verify
Flash endurance (per block)
Flash endurance (total)[6]
Flash data retention
–
–
2.2
5
–
–
25
0.8
–
–
–
0.2
mA
Driving internal pull-down resistor.
–
–
1.5
mA
Driving internal pull-down resistor.
–
–
VSS + 0.75
V
VDD – 1.0
–
VDD
V
50,000[7]
1,800,000
10
–
–
–
–
–
–
IILP
IIHP
VOLV
VOHV
FlashENPB
FlashENT
FlashDR
Units
Notes
V
This specification applies to the
functional requirements of external
programmer tools
V
This specification applies to the
functional requirements of external
programmer tools
V
This specification applies to the
functional requirements of external
programmer tools
V
This specification applies to this
device when it is executing internal
flash writes
mA
V
V
–
Erase/write cycles per block.
–
Erase/write cycles.
Years
DC I2C Specifications
Table 18 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash endurance and retention specifications with the
use of the EEPROM user module are valid only within the range: 25 °C +/–20C during the Flash Write operation. Reference the
EEPROM User Module datasheet instructions for EEPROM flash Write requirements outside of the 25 °C +/–20 °C temperature
window.
Table 18. DC I2C Specifications[8]
Symbol
VILI2C
Input low level
Description
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
2.4 V VDD  3.6 V
4.75 V  VDD  5.25 V
2.4 V  VDD  5.25 V
Notes
8. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
9. 0 to 70 °C ambient, VDD = 3.3 V.
Document Number: 001-05356 Rev. *N
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AC Electrical Characteristics
AC Chip Level Specifications
Table 19, Table 20, and Table 21 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 19. 5-V and 3.3-V AC Chip-Level Specifications
Symbol
FCPU1
F32K1
F32K_U
Description
CPU frequency (3.3 V nominal)
Internal low speed oscillator frequency
Internal low speed oscillator (ILO) untrimmed
frequency
Min
0.75
15
5
Typ
–
32
–
Max
12.6
64
100
Units
MHz
kHz
kHz
FIMO12
Internal main oscillator stability for 12 MHz
(commercial temperature)[9]
11.4
12
12.6
MHz
FIMO6
Internal main oscillator stability for 6 MHz
(commercial temperature)
5.5
6.0
6.5
MHz
DCIMO
DCILO
tXRST
tPOWERUP
Duty cycle of IMO
Internal low speed oscillator duty cycle
External reset pulse width
Time from end of POR to CPU executing code
40
20
10
–
50
50
–
16
60
80
–
100
%
%
s
ms
–
–
–
–
200
600
250
1600
1400
V/ms
ps
ps
–
100
900
ps
SRPOWER_UP Power supply slew rate
tjit_IMO [11]
12 MHz IMO cycle-to-cycle jitter (RMS)
12 MHz IMO long term N cycle-to-cycle jitter
(RMS)
12 MHz IMO period jitter (RMS)
Document Number: 001-05356 Rev. *N
Notes
12 MHz only for SLIMO Mode = 0.
After a reset and before the M8C starts
to run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technical Reference Manual for details
on this timing.
Trimmed for 3.3 V operation using
factory trim values.
See Figure 10 on page 17,
SLIMO mode = 0.
Trimmed for 3.3 V operation using
factory trim values.
See Figure 10 on page 17,
SLIMO mode = 1.
Power-up from 0 V. See the System
Resets section of the PSoC Technical
Reference Manual.
N = 32
Page 23 of 47
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Table 20. 2.7-V AC Chip Level Specifications
Symbol
FCPU1
F32K1
F32K_U
Description
CPU Frequency (2.7 V nominal)
Internal low speed oscillator frequency
Internal low speed oscillator (ILO)
untrimmed frequency
Min
0.75
8
5
Typ
–
32
–
Max
3.25
96
100
Units
MHz
kHz
kHz
FIMO12
IMO stability for 12 MHz
(commercial temperature)[10]
11.0
12
12.9
MHz
FIMO6
IMO stability for 6 MHz
(commercial temperature)
5.5
6.0
6.5
MHz
DCIMO
DCILO
tXRST
tPOWERUP
Duty cycle of IMO
Internal low speed oscillator duty cycle
External reset pulse width
Time from end of POR to CPU executing
code
40
20
10
–
50
50
–
16
60
80
–
100
%
%
µs
ms
SRPOWER_UP
tjit_IMO [11]
Power supply slew rate
12 MHz IMO cycle-to-cycle jitter (RMS)
12 MHz IMO long term N cycle-to-cycle jitter
(RMS)
12 MHz IMO period jitter (RMS)
–
–
–
–
500
800
250
900
1400
V/ms
ps
ps
–
300
500
ps
Notes
SLIMO mode = 0
After a reset and before the M8C starts to
run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technical Reference Manual for details on
this timing.
Trimmed for 2.7 V operation using factory
trim values.
See Figure 10 on page 17,
SLIMO mode = 0.
Trimmed for 2.7 V operation using factory
trim values.
See Figure 10 on page 17,
SLIMO mode = 1.
Power-up from 0 V. See the System
Resets section of the PSoC Technical
Reference Manual
N = 32
Notes
10. 0 °C to 70 °C ambient, VDD = 3.3 V.
11. Refer to Cypress Jitter Specifications Application Note – AN5054 at http://www.cypress.com for more information.
Document Number: 001-05356 Rev. *N
Page 24 of 47
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AC GPIO Specifications
Table 21 and Table 22 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 21. 5-V and 3.3-V AC GPIO Specifications
Min
Typ
Max
Units
FGPIO
Symbol
GPIO operating frequency
Description
0
–
6
MHz
Notes
tRise023
Rise time, strong mode, Cload = 50 pF
ports 0, 2, 3
15
–
80
ns
VDD = 3.0 to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
tRise1
Rise time, strong mode, Cload = 50 pF
port 1
10
–
50
ns
VDD = 3.0 V to 3.6 V, 10% to 90%
tFall
Fall time, strong mode, Cload = 50 pF
all ports
10
–
50
ns
VDD = 3.0 V to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
Normal strong mode, port 1.
Table 22. 2.7-V AC GPIO Specifications
Min
Typ
Max
Units
FGPIO
Symbol
GPIO operating frequency
Description
0
–
1.5
MHz
Notes
tRise023
Rise time, strong mode, Cload = 50 pF
ports 0, 2, 3
15
–
100
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
tRise1
Rise time, strong mode, Cload = 50 pF
port 1
10
–
70
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
tFall
Fall time, strong mode, Cload = 50 pF
all Ports
10
–
70
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
Normal strong mode, port 1.
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise023
TRise1
AC Comparator Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 23. AC Comparator Specifications
Symbol
tCOMP
Description
Min
Typ
Max
Units
Comparator response time, 50 mV overdrive
–
–
100
200
ns
ns
Document Number: 001-05356 Rev. *N
Notes
VDD  3.0 V.
2.4 V < VCC <3.0 V.
Page 25 of 47
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AC External Clock Specifications
Table 24, Table 25, Table 26, and Table 27 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA 
85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 24. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.750
–
12.6
MHz
–
High period
38
–
5300
ns
–
Low period
38
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
Notes
Table 25. 3.3-V AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU clock divide by 1
Min
0.750
Typ
–
Max
12.6
Units
MHz
–
–
–
High period with CPU clock divide by 1
Low period with CPU clock divide by 1
Power-up IMO to switch
41.7
41.7
150
–
–
–
5300
–
–
ns
ns
µs
Notes
Maximum CPU frequency is 12 MHz at
3.3 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
Table 26. 2.7-V (Nominal) AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU clock divide by 1
Min
0.750
Typ
–
Max
3.080
Units
MHz
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.15
–
6.35
MHz
–
–
–
High period with CPU clock divide by 1
Low period with CPU clock divide by 1
Power-up IMO to switch
160
160
150
–
–
–
5300
–
–
ns
ns
µs
Notes
Maximum CPU frequency is 3 MHz at
2.7 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
If the frequency of the external clock is
greater than 3 MHz, the CPU clock
divider is set to 2 or greater. In this case,
the CPU clock divider ensures that the
fifty percent duty cycle requirement is
met.
Table 27. 2.7-V (Minimum) AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU clock divide by 1
Min
0.750
Typ
–
Max
6.30
Units
MHz
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.15
–
12.6
MHz
–
–
–
High period with CPU clock divide by 1
Low period with CPU clock divide by 1
Power-up IMO to switch
160
160
150
–
–
–
5300
–
–
ns
ns
µs
Document Number: 001-05356 Rev. *N
Notes
Maximum CPU frequency is 6 MHz at
2.7 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
If the frequency of the external clock is
greater than 6 MHz, the CPU clock
divider is set to 2 or greater. In this case,
the CPU clock divider ensures that the
fifty percent duty cycle requirement is
met.
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AC Programming Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 28. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK
tDSCLK3
tDSCLK2
tERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (Block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (Bulk)
Min
1
1
40
40
0
–
–
–
–
–
–
Typ
–
–
–
–
–
10
40
–
–
–
20
Max
20
20
–
–
8
–
–
45
50
70
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
ms
tPROGRAM_HOT
tPROGRAM_COLD
Flash block erase + flash block write time
Flash block erase + flash block write time
–
–
–
–
100
200
ms
ms
Notes
3.6  VDD
3.0  VDD  3.6
2.4  VDD  3.0
Erase all blocks and protection
fields at once
0 °C  Tj  100 °C
–40 °C  Tj  0 °C
AC I2C Specifications
Table 29 and Table 30 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 29. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V
Symbol
Description
Standard Mode
Fast Mode
Units
Min
Max
Min
Max
0
100
0
400
kHz
FSCLI2C
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START condition. After this period,
the first clock pulse is generated
4.0
–
0.6
–
µs
tLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
tSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
µs
tHDDATI2C
Data hold time
0
–
0
–
µs
–
ns
–
µs
100
[12]
tSUDATI2C
Data setup time
250
–
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
tBUFI2C
Bus free time between a STOP and START condition
4.7
–
1.3
–
µs
tSPI2C
Pulse width of spikes are suppressed by the input filter
–
–
0
50
ns
Note
12. A Fast Mode I2C bus device is used in a Standard Mode I2C bus system but the requirement tSU; DAT  250 ns is met. This automatically is the case if the device
does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.
Document Number: 001-05356 Rev. *N
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Table 30. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Symbol
Standard Mode
Description
Fast Mode
Min
Max
Min
Max
Units
FSCLI2C
SCL clock frequency
0
100
–
–
kHz
tHDSTAI2C
Hold time (repeated) START condition. After this period,
the first clock pulse is generated
4.0
–
–
–
µs
tLOWI2C
LOW period of the SCL clock
4.7
–
–
–
µs
tHIGHI2C
HIGH period of the SCL clock
4.0
–
–
–
µs
tSUSTAI2C
Setup time for a repeated start condition
4.7
–
–
–
µs
tHDDATI2C
Data hold time
0
–
–
–
µs
tSUDATI2C
Data setup time
250
–
–
–
ns
tSUSTOI2C
Setup time for STOP condition
4.0
–
–
–
µs
tBUFI2C
Bus free time between a STOP and START condition
4.7
–
–
–
µs
tSPI2C
Pulse width of spikes are suppressed by the input filter
–
–
–
–
ns
Figure 12. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
Document Number: 001-05356 Rev. *N
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
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AC SPI Specifications
Table 31 and Table 32 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 31. SPI Master AC Specifications
Conditions
Min
Typ
Max
Units
FSCLK
Symbol
SCLK clock frequency
Parameter
–
–
–
12
MHz
DCSCLK
SCLK duty cycle
–
–
50
–
%
tSETUP
MISO to SCLK setup time
–
40
–
–
ns
tHOLD
SCLK to MISO hold time
–
40
–
–
ns
tOUT_VAL
SCLK to MOSI valid time
–
–
–
40
ns
tOUT_HIGH
MOSI high time
–
40
–
–
ns
Conditions
Min
Typ
Max
Units
Table 32. SPI Slave AC Specifications
Symbol
Parameter
FSCLK
SCLK clock frequency
–
–
–
12
MHz
tLOW
SCLK low time
–
41.67
–
–
ns
tHIGH
SCLK high time
–
41.67
–
–
ns
tSETUP
MOSI to SCLK setup time
–
30
–
–
ns
tHOLD
SCLK to MOSI hold time
–
50
–
–
ns
tSS_MISO
SS low to MISO valid
–
–
–
153
ns
tSCLK_MISO
SCLK to MISO valid
–
–
–
125
ns
tSS_HIGH
SS high time
–
50
–
–
ns
tSS_SCLK
Time from SS low to first
SCLK
–
2/FSCLK
–
–
ns
tSCLK_SS
Time from last SCLK to SS
high
–
2/FSCLK
–
–
ns
Document Number: 001-05356 Rev. *N
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Packaging Dimensions
This section illustrates the packaging specifications for the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and CY8C20634
PSoC devices along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 13. 8-Pin (150-Mil) SOIC
51-85066 *D
Document Number: 001-05356 Rev. *N
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Figure 14. 16-Pin (150-Mil) SOIC
51-85068 *C
Figure 15. 48-Pin (7 × 7 × 1.0 mm) QFN
001-12919*C
Document Number: 001-05356 Rev. *N
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Figure 16. 16-Pin QFN No E-Pad 3 × 3 × 0.6 mm Package Outline (Sawn)
2.9
3.1
0.20 min
1
1
2
2.9
3.1
0.20 DIA TYP.
2
1.5 (NOM)
0.45
0.55
PIN #1 ID
0.152 REF.
0.30
0.18
0.05 MAX
0.50
0.60 MAX
1.5
SEATING PLANE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
PART NO.
DESCRIPTION
LG16A
LEAD-FREE
LD16A
STANDARD
1. JEDEC # MO-220
2. Package Weight: 0.014g
3. DIMENSIONS IN MM, MIN
MAX
001-09116 *E
Figure 17. 24-Pin (4 × 4 × 0.55 mm) Sawn QFN
001-13937 *C
Document Number: 001-05356 Rev. *N
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Figure 18. 32-Pin QFN 5 × 5 × 0.55 mm (Sawn)
001-48913 *B
Figure 19. 28-Pin (210-Mil) SSOP
51-85079 *D
Document Number: 001-05356 Rev. *N
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Figure 20. 30-Ball (1.85 × 2.31 × 0.40 mm) WLCSP
001-44613 *A
Important Note For information on the preferred dimensions for mounting the QFN packages, see the application note “Application
Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages” available at http://www.amkor.com.
It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 001-05356 Rev. *N
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Thermal Impedances
Table 33 illustrates the minimum solder reflow peak temperature to achieve good solderability.
Table 33. Thermal Impedances Per Package
Package
Typical JA [13]
8 SOIC
127 °C/W
16 SOIC
80 °C/W
16 QFN
46 °C/W
24
QFN[14]
25 °C/W
28 SSOP
96 °C/W
30 WLCSP
54 °C/W
32 QFN[14]
27 °C/W
48 QFN[14]
28 °C/W
Solder Reflow Peak Temperature
Table 34 illustrates the minimum solder reflow peak temperature to achieve good solderability.
Table 34. Solder Reflow Peak Temperature
Maximum Peak
Temperature
Time at Maximum
Temperature
8-Pin SOIC
260 °C
20 s
16-Pin SOIC
260 °C
20 s
16-Pin QFN
260 °C
20 s
24-Pin QFN
260 °C
20 s
28-Pin SSOP
260 °C
20 s
30-Pin WLCSP
260 °C
20 s
32-Pin QFN
260 °C
20 s
48-Pin QFN
260 °C
20 s
Package
Notes
13. TJ = TA + Power × JA.
14. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages" available at http://www.cypress.com.
15. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ±5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-05356 Rev. *N
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Development Tool Selection
Evaluation Tools
Software
All evaluation tools are sold at the Cypress Online Store.
PSoC Designer™
CY3210-MiniProg1
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
PSoC Programmer
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
PSoC Programmer is flexible enough and is used on the bench
in development and also suitable for factory programming. PSoC
Programmer works either as a standalone programming
application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■
PSoC Designer Software CD
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
Mini-Eval Programming Board
■
■
■
110 ~ 240V Power Supply, Euro-Plug Adapter
iMAGEcraft C Compiler (Registration Required)
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
■
■
Document Number: 001-05356 Rev. *N
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Page 36 of 47
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Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers are purchased from the Cypress Online
Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
Modular Programmer Base
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
3 Programming Module Cards
■
USB 2.0 Cable
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 35. Emulation and Programming Accessories
Part Number
Pin
Package
Flex-Pod Kit [16]
Foot Kit [17]
CY8C20234-12LKXI
16 QFN
Not Available
CY3250-16QFN-FK
CY8C20334-12LQXI
24 QFN
CY3250-20334QFN
CY3250-24QFN-FK
CY8C20634-12FDXI
30 WLCSP
Not Available
Prototyping
Module
Adapter [18]
CY3210-20X34 Not Available
CY3210-20X34 AS-24-28-01ML-6
CY3210-20X34 Not Available
Notes
16. Dual function Digital I/O Pins also connect to the common analog mux.
17. This part may be used for in-circuit debugging. It is NOT available for production.
18. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is available at
http://www.emulation.com.
Document Number: 001-05356 Rev. *N
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Ordering Information
Table 36 lists the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and CY8C20634 PSoC device’s key package features and
ordering codes.
Table 36. PSoC Device Key Features and Ordering Information
Ordering Code
Package
Flash
(Bytes)
SRAM
(Bytes)
Digital CapSense- Digital
Blocks
Blocks
I/O Pins
Analog
Inputs
Analog XRES
Outputs
Pin
CY8C20134-12SXI
8-Pin SOIC
8K
512
0
1
6
6
0
No
CY8C20234-12SXI
16-Pin SOIC
8K
512
0
1
13
13
0
Yes
CY8C20534-12PVXI
28-Pin SSOP
8K
512
0
1
24
24[16]
0
Yes
CY8C20534-12PVXIT
28-Pin SSOP
8K
512
0
1
24
24[16]
0
Yes
CY8C20000-12LFXI
48-Pin OCD
8K
512
0
1
28
28[16]
0
Yes
CY8C20234-12LKXI
16-Pin (3 × 3 mm
0.60 Max) Sawn QFN
8K
512
0
1
13
13
[16]
0
Yes
CY8C20234-12LKXIT
16-Pin (3 × 3 mm
0.60 Max) Sawn QFN
(Tape and Reel)
8K
512
0
1
13
13[16]
0
Yes
CY8C20334-12LQXI
24-Pin (4 × 4 mm 0.60
Max) Sawn QFN
8K
512
0
1
20
20[16]
0
Yes
CY8C20334-12LQXIT
24-Pin (4 × 4 mm
0.60 Max) Sawn QFN
(Tape and Reel)
8K
512
0
1
20
20[16]
0
Yes
CY8C20434-12LQXI
32-Pin (5 × 5 mm
0.60 Max) Thin Sawn
QFN
8K
512
0
1
28
28
0
Yes
CY8C20434-12LQXIT
32-Pin (5 × 5 mm
0.60 Max) Thin Sawn
QFN
(Tape and Reel)
8K
512
0
1
28
28
0
Yes
CY8C20634-12FDXI
30-Ball WLCSP
8K
512
0
1
27
27
0
Yes
CY8C20634-12FDXIT
30-Ball WLCSP
(Tape and Reel)
8K
512
0
1
27
27
0
Yes
QFN[16]
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 20 xxx- 12 xx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX/LQX = QFN Pb-Free
AX = TQFP Pb-Free
FDX = WLCSP Pb-free
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-05356 Rev. *N
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Acronyms
Acronyms Used
Table 37 lists the acronyms that are used in this document.
Table 37. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
Description
alternating current
MIPS
million instructions per second
ADC
analog-to-digital converter
OCD
on-chip debug
API
application programming interface
PCB
printed circuit board
complementary metal oxide semiconductor
PGA
programmable gain amplifier
central processing unit
POR
power on reset
CMOS
CPU
EEPROM
GPIO
ICE
IDAC
electrically erasable programmable read-only
memory
PPOR
precision power on reset
general purpose I/O
PSoC®
Programmable System-on-Chip
in-circuit emulator
PWM
current DAC
QFN
pulse width modulator
quad flat no leads
IDE
integrated development environment
SLIMO
slow IMO
ILO
internal low speed oscillator
SPITM
serial peripheral interface
IMO
internal main oscillator
SRAM
static random access memory
I/O
supervisory read only memory
input/output
SROM
ISSP
in-system serial programming
SSOP
LCD
liquid crystal display
USB
LED
light-emitting diode
WLCSP
LVD
low voltage detect
XRES
MCU
microcontroller unit
LDO
WDT
shrink small-outline package
universal serial bus
watchdog timer
wafer level chip scale package
external reset
Reference Documents
PSoC® CY8C20x34 and PSoC® CY8C20x24 Technical Reference Manual (TRM) – 001-13033
Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 001-05356 Rev. *N
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Document Conventions
Units of Measure
Table 38 lists the unit sof measures.
Table 38. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
°C
degree Celsius
ms
millisecond
pF
picofarad
ns
nanosecond
kHz
kilohertz
ps
picosecond
MHz
megahertz
µV
microvolts
kilohm
mV
millivolts
k

ohm
V
volts
µA
microampere
W
watt
mA
milliampere
mm
nA
nanoampere
%
µs
microsecond
millimeter
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
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Glossary
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
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Glossary
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
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Glossary
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
Document Number: 001-05356 Rev. *N
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Glossary
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 001-05356 Rev. *N
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Document History Page
Document Title:
CY8C20134, CY8C20234, CY8C20334, CY8C20434, CY8C20534, CY8C20634 PSoC® Programmable System-on-Chip™
Document Number: 001-05356
Revision
ECN
Orig. of
Change
Submission
Date
**
404571
HMT
See ECN
New silicon and document (Revision **).
*A
418513
HMT
See ECN
Updated Electrical Specifications, including Storage Temperature and
Maximum Input Clock Frequency. Updated Features and Analog System
Overview. Modified 32-pin QFN E-PAD dimensions. Added new 32-pin QFN.
Add High Output Drive indicator to all P1[x] pinouts. Updated trademarks.
*B
490071
HMT
See ECN
Made datasheet “Final”. Added new Development Tool section. Added OCD
pinout and package diagram. Added 16-pin QFN. Updated 24-pin and 32-pin
QFN package diagrams to 0.60 max thickness. Changed from commercial to
industrial temperature range. Updated Storage Temperature specification and
notes. Updated thermal resistance data. Added development tool kit part
numbers. Finetuned features and electrical specifications.
*C
788177
HMT
See ECN
Added CapSense SNR requirement reference. Added Low Power Comparator
(LPC) AC/DC electrical specifications tables. Added 2.7V minimum specifications. Updated figure standards. Updated Technical Training paragraph. Added
QFN package clarifications and dimensions. Updated ECN-ed Amkor dimensioned QFN package diagram revisions.
*D
1356805 HMT/SFVTM
P3/HCL/SFV
See ECN
Updated 24-pin QFN Theta JA. Added External Reset Pulse Width, TXRST,
specification. Fixed 48-pin QFN.vsd. Updated the table introduction and high
output voltage description in section two. The sentence: "Exceeding maximum
ratings may shorten the battery life of the device.” does not apply to all
datasheets. Therefore, the word "battery" is changed to "useful.” Took out tabs
after table and figure numbers in titles and added two hard spaces. Updated
the section, DC GPIO Specifications on page 18 with new text. Updated VOH5
and VOH6 to say, ”High Output Voltage, Port 1 Pins with 3.0V LDO Regulator
Enabled.” Updated VOH7 and VOH8 with the text, “maximum of 20 mA source
current in all I/Os.”Added 28-pin SSOP part, pinout, package. Updated specs.
Modified dev. tool part numbers.
*E
2197347
See ECN
Added 32-pin Sawn QFN Pin diagram
Removed package diagram: 32-Pin (5 × 5 mm) SAWN QFN(001-42168 *A)
Updated Ordering Information table with CY8C20434-12LQXI and
CY8C20434-12LQXIT ordering details.
Corrected Table 16. DC Programming Specifications - Included above the table
"Flash Endurance and Retention specifications with the use of the EEPROM
User Module are valid only within the range: 25 °C +/-20C during the Flash
Write operation. Refer the EEPROM User Module datasheet instructions for
EEPROM Flash Write requirements outside of the 25 °C +/-20 °C temperature
window."
*F
2542938 RLRM/AESA
07/30/2008
Corrected Ordering Information format. Updated package diagrams 001-13937
and 001-30999. Updated datasheet template. Corrected Figure 6 (28-pin
diagram).
*G
2610469
SNV/PYRS
11/20/08
*H
2693024
DPT/PYRS
04/16/2009
Changed title from PSoC® Mixed Signal Array to PSoC® Programmable
System-on-Chip™
Replaced package outline drawing for 32-Pin Sawn QFN
Updated “Development Tool Selection” on page 36
Updated “Development Tools” on page 5 and “Designing with PSoC Designer”
on page 6
Updated “Getting Started” on page 4
*I
2717566 DRSW/AESA
06/11/2009
Updated AC Chip-Level, and AC Programming Specifications as follows:
Modified FIMO6 (page 20), TWRITE specifications (page 23) Added IOH, IOL
(page 17), Flash endurance note (page 19), DCILO (page 20), F32K_U (page
20), TPOWERUP (page 20), TERASEALL (page 23), TPROGRAM_HOT (page 24),
and TPROGRAM_COLD (page 24) specifications
Added AC SPI Master and Slave Specifications
Added 30-Ball WLCSP Package
UVS/AESA
Document Number: 001-05356 Rev. *N
Description of Change
Updated VOH5, VOH7, and VOH9 specifications
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Document History Page
Document Title:
CY8C20134, CY8C20234, CY8C20334, CY8C20434, CY8C20534, CY8C20634 PSoC® Programmable System-on-Chip™
Document Number: 001-05356
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*J
2825336
ISW
12/10/2009
Updated pin description table for 48-pin OCD. Updated Ordering information
table to include CY8C20534-12PVXA parts. Updated package diagrams for
48-pin QFN, 16-pin QFN (sawn), 24-pin QFN (sawn), and 30-ball WLCSP
specs.
*K
2892629
NJF
03/15/2010
Updated Programmable pin configuration details in Features.
Updated Analog Multiplexer System.
Updated Cypress website links.
Updated PSoC Designer Software Subsystems.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings.
Removed the following sections:
DC Low Power Comparator Specifications, AC Analog Mux Bus Specifications,
AC Low Power Comparator Specifications, Third Party Tools, and Build a PSoC
Emulator into your Board.
Modified Notes in Packaging Dimensions.
Updated Ordering Code Definitions.
Removed inactive parts from Ordering Information.
Updated links in Sales, Solutions, and Legal Information.
*L
2872902
VMAD
04/06/10
Added part number CY8C20134 to the title.
Added 8-pin and 16-pin SOIC pin and package details.
Updated content to match current style guide and datasheet template.
Moved acronyms and units of measure tables to page 35.
*M
3043170
NJF
09/30/10
Added PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changed were made to I2C Timing Diagram. Updated for clearer
understanding.
Template and styles update.
*N
3173718
NJF
02/16/2011
CY8C20134-12SX1I and CY8C20234-12SX2I typo error fixed in the ordering
information table and changed in to CY8C20134-12SXI and
CY8C20234-12SXI. Updated document version and date.
Updated package diagram to 001-12919 *C.
Document Number: 001-05356 Rev. *N
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
PSoC Solutions
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
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cypress.com/go/psoc
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Wireless/RF
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cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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