CYRF89435 ® PRoC™ - CapSense PRoC™ - CapSense® PRoC-CS Features ■ Single Device, Two functions ❐ 8-bit flash based capacitive touch controller MCU function and 2.4-GHz WirelessUSB™ NL radio transceiver function in a single device ■ Wide operating range: 1.9 V to 3.6 V ❐ Configurable capacitive sensing elements ❐ 7 μA per sensor at 500 ms scan rate ❐ Supports SmartSense™ Auto-tuning ® buttons, sliders, ❐ Supports a combination of CapSense touchpads, touchscreens, and proximity sensors ❐ SmartSense_EMC offers superior noise immunity for applications with challenging conducted and radiated noise conditions ❐ 2.4-GHz WirelessUSB NL Transceiver function ❐ Operates in the 2.4-GHz ISM Band (2.402 GHz - 2.479 GHz) ❐ 1-Mbps over-the-air data rate ❐ Receive sensitivity typical: –87 dBm ❐ Below 1 μA typical current consumption in sleep state ❐ Closed-loop frequency synthesis ❐ Supports frequency-hopping spread spectrum ❐ On-chip packet framer with 64-byte first in first out (FIFO) data buffer ❐ Built-in auto-retry-acknowledge protocol simplifies usage ❐ Built-in cyclic redundancy check (CRC), forward error correction (FEC), data whitening ❐ Additional outputs for interrupt request (IRQ) generation ❐ Digital readout of received signal strength indication (RSSI) ■ Powerful Harvard-architecture processor ❐ M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external crystal resonator or clock signal ❐ Low power at high speed ■ Temperature range: 0 °C to +70 °C ■ Flexible on-chip memory • 32 KB Flash/2 KB SRAM ❐ 50,000 flash erase/write cycles ❐ Partial flash updates ❐ Flexible protection modes ❐ In-system serial programming (ISSP) Cypress Semiconductor Corporation Document Number: 001-76581 Rev. *D • ■ Precision, programmable clocking ❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5% ❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers ❐ Precision 32 kHz oscillator for optional external crystal ■ Programmable pin configurations ❐ Up to 13 general-purpose I/Os (GPIOs) ❐ Dual mode GPIO: All GPIOs support digital I/O and analog inputs ❐ 25-mA sink current on each GPIO • 120 mA total sink current on all GPIOs ❐ Pull-up, high Z, open-drain modes on all GPIOs ❐ CMOS drive mode –5 mA source current on ports 0 and 1 and 1 mA on port 2 ❐ 20 mA total source current on all GPIOs ■ Versatile analog system ❐ Low-dropout voltage regulator for all analog resources ❐ Common internal analog bus enabling capacitive sensing on all pins ❐ High power supply rejection ratio (PSRR) comparator ❐ 8 to 10-bit incremental analog-to-digital converter (ADC) ■ Additional system resources 2 ❐ I C slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz ❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz ❐ Three 16-bit timers ❐ Watchdog and sleep timers ❐ Integrated supervisory circuit ❐ Emulated E2PROM using flash memory ■ Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory ■ Package option ❐ 40-pin 6 mm × 6 mm QFN 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 18, 2012 CYRF89435 Logical Block Diagram Document Number: 001-76581 Rev. *D Page 2 of 40 CYRF89435 Contents PSoC® Functional Overview ............................................ 4 PSoC Core .................................................................. 4 CapSense System ....................................................... 4 WirelessUSB NL System ............................................. 5 Transmit Power Control ............................................... 5 Power-on and Register Initialization Sequence ........... 5 Getting Started .................................................................. 6 CapSense Design Guides ........................................... 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 7 PSoC Designer Software Subsystems ........................ 7 Designing with PSoC Designer ....................................... 8 Select User Modules ................................................... 8 Configure User Modules .............................................. 8 Organize and Connect ................................................ 8 Generate, Verify, and Debug ....................................... 8 Pinouts .............................................................................. 9 Pin Definitions ................................................................ 10 Absolute Maximum Ratings .......................................... 11 Operating Temperature .................................................. 11 Electrical Specifications – PSoC Core ......................... 12 DC Chip-Level Specifications .................................... 13 DC GPIO Specifications ............................................ 14 Analog DC Mux Bus Specifications ........................... 15 DC Low Power Comparator Specifications ............... 15 Comparator User Module Electrical Specifications ... 16 ADC Electrical Specifications .................................... 17 DC POR and LVD Specifications .............................. 18 DC Programming Specifications ............................... 18 DC I2C Specifications ............................................... 19 DC Reference Buffer Specifications .......................... 19 Document Number: 001-76581 Rev. *D DC IDAC Specifications ............................................ 19 AC Chip-Level Specifications .................................... 20 AC GPIO Specifications ............................................ 21 AC Comparator Specifications .................................. 22 AC External Clock Specifications .............................. 22 AC Programming Specifications ................................ 23 AC I2C Specifications ................................................ 24 SPI Master AC Specifications ................................... 25 SPI Slave AC Specifications ..................................... 26 Electrical Specifications – RF Section ......................... 28 Packaging Information ................................................... 33 Thermal Impedances ................................................. 34 Capacitance on Crystal Pins ..................................... 34 Solder Reflow Specifications ..................................... 34 Development Tool Selection ......................................... 35 Software .................................................................... 35 Development Kits ...................................................... 35 Evaluation Tools ........................................................ 35 Device Programmers ................................................. 35 Accessories (Emulation and Programming) .............. 36 Third Party Tools ....................................................... 36 Ordering Information ...................................................... 36 Ordering Code Definitions ......................................... 36 Acronyms ........................................................................ 37 Reference Documents .................................................... 37 Document Conventions ................................................. 37 Units of Measure ....................................................... 37 Numeric Naming ........................................................ 38 Glossary .......................................................................... 38 Document History Page ................................................. 39 Sales, Solutions, and Legal Information ...................... 40 Worldwide Sales and Design Support ....................... 40 Products .................................................................... 40 PSoC Solutions ......................................................... 40 Page 3 of 40 CYRF89435 PSoC® Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logical Block Diagram on page 2, consists of three main areas: ■ The Core ■ CapSense Analog System ■ WirelessUSB NL System ■ System Resources. A common, versatile bus allows connection between I/O and the analog system. from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. SmartSense_EMC In addition to the SmartSense auto-tuning algorithm to remove manual tuning of CapSense applications, SmartSense_EMC user module incorporates a unique algorithm to improve robustness of capacitive sensing algorithm/circuit against high frequency conducted and radiated noise. Every electronic device must comply with specific limits for radiated and conducted external noise and these limits are specified by regulatory bodies (for example, FCC, CE, U/L and so on). A very good PCB layout design, power supply design and system design is a mandatory for a product to pass the conducted and radiated noise tests. An ideal PCB layout, power supply design or system design is not often possible because of cost and form factor limitations of the product. SmartSense_EMC with superior noise immunity is well suited and handy for such applications to pass radiated and conducted noise test. Figure 1. CapSense System Block Diagram CS1 Each CYRF89435 device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. The 13 GPIOs provide access to the MCU and analog mux. IDAC Analog Global Bus PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. Reference Buffer Document Number: 001-76581 Rev. *D Cinternal Comparator The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1 V or 1.2 V analog reference, which together support capacitive sensing of up to 13 inputs. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easy to use and provides a robust noise immunity. It is the only auto-tuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go CSN Vr CapSense System SmartSense CS2 Cexternal (P0[1] or P0[3]) Mux Mux Refs Cap Sense Counters CSCLK IMO CapSense Clock Select Oscillator Page 4 of 40 CYRF89435 Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Complex capacitive sensing interfaces, such as sliders and touchpads. ■ Chip-wide mux that allows analog input from any I/O pin. ■ Crosspoint connection between any I/O pin combinations. On-chip transmit and receive FIFO registers are available to buffer the data transfer with MCU. Over-the-air data rate is always 1 Mbps even when connected to a slow, low-cost MCU. Built-in CRC, FEC, data whitening, and automatic retry/acknowledge are all available to simplify and optimize performance for individual applications. For more details on the radio’s implementation details and timing requriements, please go through the WirelessUSB NL datasheet in www.cypress.com. Figure 2. WirelessUSB NL logic Block Diagram WirelessUSB NL System WirelessUSB NL, optimized to operate in the 2.4-GHz ISM band, is Cypress's third generation of 2.4-GHz low-power RF technology. WirelessUSB NL implements a Gaussian frequency-shift keying (GFSK) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity. Closed-loop modulation effectively eliminates the problem of frequency drift, enabling WirelessUSB NL to transmit up to 255-byte payloads without repeatedly having to pay power penalties for re-locking the phase-locked loop (PLL) as in open-loop designs Among the advantages of WirelessUSB NL are its fast lock times and channel switching, along with the ability to transmit larger payloads. Use of longer payload packets, compared to multiple short payload packets, can reduce overhead, improve overall power efficiency, and help alleviate spectrum crowding. Combined with Cypress's Capacitive touch sense controllers, WirelessUSB NL also provides the lowest bill of materials (BOM) cost solution for sophisticated PC peripheral applications such as wireless keyboards and mice, as well as best-in-class wireless performance in other demanding applications. such as toys, remote controls, fitness, automation, presenter tools, and gaming. With PRoC-CS, the WirelessUSB NL transceiver can add wireless capability to a wide variety of CapSense applications. The WirelessUSB NL is a fully-integrated CMOS RF transceiver, GFSK data modem, and packet framer, optimized for use in the 2.4-GHz ISM band. It contains transmit, receive, RF synthesizer, and digital modem functions, with few external components. The transmitter supports digital power control. The receiver uses extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. The product transmits GFSK data at approximately 0-dBm output power. Sigma-Delta PLL delivers high-quality DC-coupled transmit data path. The low-IF receiver architecture produces good selectivity and image rejection, with typical sensitivity of –87 dBm or better on most channels. Sensitivity on channels that are integer multiples of the crystal reference oscillator frequency (12 MHz) may show approximately 5 dB degradation. Digital RSSI values are available to monitor channel quality. Document Number: 001-76581 Rev. *D Transmit Power Control The following table lists recommended settings for register 9 for short-range applications, where reduced transmit RF power is a desirable trade off for lower current. Table 1. Transmit Power Control Power Setting Description Typical Transmit Power (dBm) Register 9 PA0 - Highest power +1 0x1820 PA2 - High power 0 0x1920 PA4 - High power –3 0x1A20 PA8 - Low power –7.5 0x1C20 PA12 - Lower power –11.2 0x1E20 Power-on and Register Initialization Sequence For proper initialization at power up, VIN must ramp up at the minimum overall ramp rate no slower than shown by TVIN specification in the following figure. During this time, the RST_n line must track the VIN voltage ramp-up profile to within approximately 0.2 V. Since most MCU GPIO pins automatically default to a high-Z condition at power up, it only requires a pull-up resistor. When power is stable and the MCU POR releases, and MCU begins to execute instructions, RST_n must then be pulsed Page 5 of 40 CYRF89435 low as shown in Figure 13 on page 32, followed by writing Reg[27 = 0x4200. During or after this SPI transaction, the State Machine status can be read to confirm FRAMER_ST= 1, indicating a proper initialization. Additional System Resources System resources provide additional capability, such as configurable I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power-on reset. The merits of each system resource are listed here: I2C ■ The slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). ■ Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power-on reset (POR) circuit eliminates the need for a system supervisor. ■ An internal reference provides an absolute reference for capacitive sensing. ■ A register-controlled bypass mode allows the user to disable the LDO regulator. Getting Started The quickest way to understand the PRoC-CS silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for the CapSense devices. Document Number: 001-76581 Rev. *D For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at www.cypress.com/psoc. CapSense Design Guides Design Guides are an excellent introduction to the wide variety of possible CapSense designs. They are located at www.cypress.com/go/CapSenseDesignGuides. Refer Getting Started with CapSense design guide for information on CapSense design and CY8C20XX6A/H/AS CapSense® Design Guide for specific information on PRoC-CS controllers. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Page 6 of 40 CYRF89435 Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. ■ Integrated source-code editor (C and assembly) Debugger ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC’s resources for an application. Document Number: 001-76581 Rev. *D Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 7 of 40 CYRF89435 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules”. User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the Document Number: 001-76581 Rev. *D internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. The interface lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 8 of 40 CYRF89435 Pinouts The CYRF89435 PRoC-CS device is available in a 40-pin QFN package, which is illustrated in the following table. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VDD, and XRES are not capable of Digital I/O. P1[3] 1 P1[1] GND P2[5] P2[3] VDD VDD ANTb ANT VDD P1[7] P1[5] VDD Figure 3. 40-pin QFN pinout 40 39 38 37 36 35 34 33 32 31 30 P0[1] 2 29 P0[3] 3 28 P0[7] VDD 4 27 XTALi DNU 5 QFN 26 XTALo DNU 6 (Top View) 25 VDD FIFO 7 24 VIN DNU 8 23 P0[4] P1[0] 9 22 VOUT VIN 10 21 VIN 11 12 13 14 15 16 17 18 19 20 VDD RST_n MISO MOSI CLK PKT SPI_SS XRES P1[4] P1[2] Document Number: 001-76581 Rev. *D Page 9 of 40 CYRF89435 Pin Definitions Pin No Pin name Pin Description [2] Digital I/O, Analog I/O, SPI CLK 1 P1[3]/SCLK 2 P1[1]/MOSI [1] 3 GND Ground connection 4, 20, 25, 33, 34, 37, 40 VDD Core power supply voltage. Connect all VDD pins to VOUT pin. 5 DNU Do not use 6 DNU Do not use 7 FIFO FIFO status indicator bit 8 DNU Do not use 9 P1[0] [1] Digital I/O, Analog I/O, TC CLK, I2C SCL, SPI MOSI Analog I/O, Digital I/O, TC DATA, I2C SDA 10, 21, 24 VIN 11 P1[2] Analog I/O, Digital I/O 12 P1[4] Analog I/O, Digital I/O, EXT CLK 13 XRES 14 SPI_SS Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator Active high external reset with internal pull-down Enable input for SPI, active low. Also used to bring device out of sleep state. 15 PKT 16 SPI_CLK Transmit/receive packet status indicator bit 17 SPI_MOSI Data input for the SPI bus 18 SPI_MISO Data output (tristate when not active) 19 RST_n 22 VOUT 1.8 V output from on-chip LDO. Connect to all VDD pins, do not connect to external loads. 23 P0[4] Analog I/O, Digital I/O, VREF 26 XTALO Output of the crystal oscillator gain block 27 XTALI Input to the crystal oscillator gain block 28 P0[7] Analog I/O, Digital I/O,SPI CLK 29 P0[3] Analog I/O, Digital I/O, Integrating input 30 P0[1] Analog I/O, Digital I/O, Integrating input 31 P2[5] Analog I/O, Digital I/O, XTAL Out Clock input for SPI interface RST_n Low: Chip shutdown to conserve power. Register values lost RST_n High: Turn on chip, registers restored to default value 32 P2[3] Analog I/O, Digital I/O, XTAL In 35 ANTb Differential RF input/output. Each of these pins must be DC grounded, 20 kΩ or less 36 ANT 38 P1[7]/SS_N Digital I/O, Analog I/O, I2C SCL, SPI SS Differential RF input/output. Each of these pins must be DC grounded, 20 kΩ or less 39 P1[5]/MISO Digital I/O, Analog I/O, I2C SDA, SPI MISO Notes 1. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 2. Alternate SPI clock. Document Number: 001-76581 Rev. *D Page 10 of 40 CYRF89435 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 2. Absolute Maximum Ratings Symbol TSTG VIN[3] VDD VIO VIOZ[4] IMIO ESD LU Description Storage temperature Conditions Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. – Supply voltage – DC input voltage – DC voltage applied to tristate – Maximum current into any port pin – Electrostatic discharge voltage Human body model ESD i) RF pins (ANT, ANTb) ii) Analog pins (XTALi, XTALo) iii) Remaining pins Latch-up current In accordance with JESD78 standard Min TBD Typ TBD 1.9 –0.5 –0.5 –0.5 TBD – 3.63 – 1.98 – VDD + 0.5 – VDD + 0.5 TBD TBD – – 500 500 2000 – Max TBD Units °C V V V V mA V – 140 mA Typ – TBD Max 70 TBD Units °C Operating Temperature Table 3. Operating Temperature Symbol TA TJ Description Ambient temperature Operational die temperature Conditions – The temperature rise from ambient to junction is package specific. Refer the Thermal Impedances on page 34. The user must limit the power consumption to comply with this requirement. Min 0 TBD °C Notes 3. Program the device at 3.3 V only. Hence use MiniProg3 only as MiniProg1 does not support programming at 3.3 V. 4. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VIN. Document Number: 001-76581 Rev. *D Page 11 of 40 CYRF89435 Electrical Specifications – PSoC Core This section presents the DC and AC electrical specifications of the CYRF89435 PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 4. Voltage versus CPU Frequency 3.6 V V I N Voltage li d ng Va rati n e io Op Reg 1.9 V 750 kHz 3 MHz CPU Document Number: 001-76581 Rev. *D 24 MHz Frequency Page 12 of 40 CYRF89435 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 4. DC Chip-Level Specifications Symbol Conditions Min Typ Max Units Supply voltage Refer the table DC POR and LVD Specifications on page 18 1.9 – 3.6 V IDD24 Supply current, IMO = 24 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current – 2.88 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current – 1.71 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VIN 3.0 V, TA = 25 °C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current – 1.16 1.80 mA IDDAVG10 Average supply current per sensor One sensor scanned at 10 ms rate – 250 – A IDDAVG100 Average supply current per sensor One sensor scanned at 100 ms rate – 25 – A IDDAVG500 Average supply current per sensor One sensor scanned at 500 ms rate – 7 – A ISB0 Deep sleep current VIN 3.0 V, TA = 25 °C, I/O regulator turned off – 0.10 1.05 A ISB1 Standby current with POR, LVD and sleep timer VIN 3.0 V, TA = 25 °C, I/O regulator turned off – 1.07 1.50 A ISBI2C Standby current with I2C enabled Conditions are VIN = 3.3 V, TA = 25 °C and CPU = 24 MHz – 1.64 – A VIN [5, 6, 7, 8] Description Notes 5. If powering down in standby sleep mode, to properly detect and recover from a VIN brown out condition any of the following actions must be taken: Bring the device out of sleep before powering down. Assure that VIN falls below 100 mV before powering back up. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. Increase the buzz rate to assure that the falling edge of VIN is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VIN brown out conditions to be detected for edge rates slower than 1V/ms. 6. Always greater than 50 mV above VPPOR1 voltage for falling supply. 7. Always greater than 50 mV above VPPOR2 voltage for falling supply. 8. Always greater than 50 mV above VPPOR3 voltage for falling supply. Document Number: 001-76581 Rev. *D Page 13 of 40 CYRF89435 DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 5. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Typ Max Units RPU Pull-up resistor 4 5.60 8 k VOH1 High output voltage Port 2 or 3 or IOH < 10 A, maximum of 10 mA 4 pins source current in all I/Os VIN – 0.20 – – V VOH2 High output voltage Port 2 or 3 or IOH = 0.2 mA, maximum of 10 mA 4 pins source current in all I/Os VIN – 0.40 – – V VOH3 High output voltage Port 0 or 1 IOH < 10 A, maximum of 10 mA pins with LDO regulator Disabled source current in all I/Os for port 1 VIN – 0.20 – – V VOH4 High output voltage Port 0 or 1 IOH = 2 mA, maximum of 10 mA pins with LDO regulator Disabled source current in all I/Os for Port 1 VIN – 0.50 – – V VOH5A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH < 10 A, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.50 1.80 2.10 V VOH6A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH = 1 mA, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.20 – – V VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – 0.75 V VIL Input low voltage – – – 0.72 VIH Input high voltage – 1.40 – VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low Bit3 of IO_CFG1 set to enable low threshold enable set, Enable for threshold voltage of Port1 input Port1 0.7 – – V VIHLVT2.5 Bit3 of IO_CFG1 set to enable low Input High Voltage with low threshold enable set, Enable for threshold voltage of Port1 input Port1 1.2 – – V Document Number: 001-76581 Rev. *D – Min V V Page 14 of 40 CYRF89435 Table 6. 1.9 V to 2.4 V DC GPIO Specifications Symbol Description Conditions – Min Typ Max Units 4 5.60 8 k RPU Pull-up resistor VOH1 High output voltage Port 2 or 3 or IOH = 10 A, maximum of 10 mA VIN – 0.20 4 pins source current in all I/Os – – V VOH2 High output voltage Port 2 or 3 or IOH = 0.5 mA, maximum of 10 mA VIN – 0.50 4 pins source current in all I/Os – – V VOH3 High output voltage Port 0 or 1 IOH = 100 A, maximum of 10 mA VIN – 0.20 pins with LDO regulator Disabled source current in all I/Os for Port 1 – – V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA VIN – 0.50 source current in all I/Os – – V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – 0.40 V VIL Input low voltage – – – 0.30 × VIN V VIH Input high voltage – 0.65 × VIN – – V VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent temp = 25 °C 0.50 1.70 7 pF Analog DC Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 7. DC Analog Mux Bus Specifications Symbol Description Conditions Min Typ Max Units RSW Switch resistance to common analog bus – – – 800 RGND Resistance of initialization switch – to GND – – 800 The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 8. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units 0.0 – 1.8 V VLPC Low power comparator (LPC) common mode Maximum voltage limited to VIN ILPC LPC supply current – – 10 40 A VOSLPC LPC voltage offset – – 3 30 mV Document Number: 001-76581 Rev. *D Page 15 of 40 CYRF89435 Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: 0 °C TA 70 °C, 1.9 V VIN 3.6 V. Table 9. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive – 70 100 ns Offset Valid from 0.2 V to VIN – 0.2 V – 2.5 30 mV Current Average DC current, 50 mV overdrive – 20 80 µA Supply voltage > 2 V Power supply rejection ratio – 80 – dB Supply voltage < 2 V Power supply rejection ratio – 40 – dB – 0 1.5 V tCOMP PSRR Description Comparator response time Input range Document Number: 001-76581 Rev. *D Conditions Page 16 of 40 CYRF89435 ADC Electrical Specifications Table 10. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units Input VIN Input voltage range – 0 – VREFADC V CIIN Input capacitance – – – 5 pF RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution ADC reference voltage – 1.14 – 1.26 V 2.25 – 6 MHz 1/(500fF × 1/(400fF × 1/(300fF × data clock) data clock) data clock) Reference VREFADC Conversion Rate FCLK Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data clock set to 6 MHz. Sample rate = 0.001 / (2^Resolution/Data Clock) – 23.43 – ksps S10 10-bit sample rate Data clock set to 6 MHz. Sample rate = 0.001 / (2^resolution/data clock) – 5.85 – ksps DC Accuracy RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits DNL Differential nonlinearity – –1 – +2 LSB INL Integral nonlinearity – –2 – +2 LSB EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB EGAIN Gain error For any resolution –5 – +5 %FSR IADC Operating current – – 2.10 2.60 mA PSRR Power supply rejection ratio PSRR (VIN > 3.0 V) – 24 – dB PSRR (VIN < 3.0 V) – 30 – dB Power Document Number: 001-76581 Rev. *D Page 17 of 40 CYRF89435 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. DC POR and LVD Specifications Symbol Description Conditions Min – – – 2.82 2.95 VPOR1 2.36 V selected in PSoC Designer VPOR2 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VIN must be greater than or equal to 1.9 V during startup, reset from the XRES pin, or reset from watchdog. VLVD0 2.45 V selected in PSoC Designer – 2.40 Typ Max Units 2.36 2.41 V 2.60 2.66 2.45 2.51 [9] VLVD1 2.71 V selected in PSoC Designer 2.64 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85[10] 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95[11] 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 V DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. DC Programming Specifications Symbol Description Conditions Min Typ Max Units VIN Supply voltage for flash write operations – 1.91 – 3.6 V IDDP Supply current during programming or verify – – 5 25 mA VILP Input low voltage during programming or verify See the appropriate DC GPIO Specifications on page 14 – – VIL V VIHP Input high voltage during programming or verify See the appropriate DC GPIO Specifications on page 14 VIH – – V IILP Input current when Applying VILP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify – – 0.2 mA IIHP Input current when applying VIHP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify – – 1.5 mA VOLP Output low voltage during programming or verify – – + 0.75 V VOHP Output high voltage during programming or verify See appropriate DC GPIO Specifications on page 14. For VIN > 3 V use VOH4 in Table 3 on page 11. VOH – VIN V FlashENPB Flash write endurance Erase/write cycles per block 50,000 – – – FlashDR Flash data retention Following maximum Flash write cycles; ambient temperature of 55 °C 20 – – Years Notes 9. Always greater than 50 mV above VPPOR1 voltage for falling supply. 10. Always greater than 50 mV above VPPOR2 voltage for falling supply. 11. Always greater than 50 mV above VPPOR3 voltage for falling supply. Document Number: 001-76581 Rev. *D Page 18 of 40 CYRF89435 DC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3, 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 13. DC I2C Specifications Symbol VILI2C VIHI2C Description Input low level Input high level Conditions Min Typ Max Units 3.1 V ≤ VIN ≤ 3.6 V – – 0.25 × VIN V 2.5 V ≤ VIN ≤ 3.0 V – – 0.3 × VIN V 1.9 V ≤ VIN ≤ 2.4 V – – 0.3 × VIN V 1.9 V ≤ VIN ≤ 3.6 V 0.65 × VIN – – V DC Reference Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA 70 °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 14. DC Reference Buffer Specifications Symbol Description Conditions Min Typ Max Units VRef Reference buffer output 1.9 V to 3.6 V 1 – 1.05 V VRefHi Reference buffer output 1.9 V to 3.6 V 1.2 – 1.25 V DC IDAC Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. DC IDAC Specifications Symbol Description Min Typ Max Units IDAC_DNL Differential nonlinearity –4.5 – +4.5 LSB IDAC_INL Integral nonlinearity –5 – +5 LSB IDAC_Gain (Source) Range = 0.5x 6.64 – 22.46 µA Range = 1x 14.5 – 47.8 µA Range = 2x 42.7 – 92.3 µA Notes DAC setting = 128 dec. Not recommended for CapSense applications. Range = 4x 91.1 – 170 µA DAC setting = 128 dec Range = 8x 184.5 – 426.9 µA DAC setting = 128 dec Document Number: 001-76581 Rev. *D Page 19 of 40 CYRF89435 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC Chip-Level Specifications Symbol Description Conditions Min Typ Max Units 24 25.2 MHz FIMO24 IMO frequency at 24 MHz Setting – 22.8 FIMO12 IMO frequency at 12 MHz setting – 11.4 12 12.6 MHz FIMO6 IMO frequency at 6 MHz setting – 5.7 6.0 6.3 MHz FCPU CPU frequency – 0.75 – 25.20 MHz F32K1 ILO frequency – 19 32 50 kHz F32K_U ILO untrimmed frequency – 13 32 82 kHz DCIMO Duty cycle of IMO – 40 50 60 % DCILO ILO duty cycle – 40 50 60 % SRPOWER_UP Power supply slew rate VIN slew rate during power-up – – 250 V/ms tXRST External reset pulse width at power-up After supply voltage is valid 1 – – ms tXRST2 External reset pulse width after power-up Applies after part has booted 10 – – s tOS Startup time of ECO – – 1 – s tJIT_IMO N = 32 6 MHz IMO cycle-to-cycle jitter (RMS) – 0.7 6.7 ns 6 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 4.3 29.3 ns 6 MHz IMO period jitter (RMS) – 0.7 3.3 ns 12 MHz IMO cycle-to-cycle jitter (RMS) – 0.5 5.2 ns 12 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 2.3 5.6 ns 12 MHz IMO period jitter (RMS) – 0.4 2.6 ns 24 MHz IMO cycle-to-cycle jitter (RMS) – 1.0 8.7 ns 24 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) – 1.4 6.0 ns 24 MHz IMO period jitter (RMS) – 0.6 4.0 ns Document Number: 001-76581 Rev. *D Page 20 of 40 CYRF89435 AC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency Conditions Min Typ Normal strong mode Port 0, 1 0 – 0 – Max Units 6 MHz for 1.9 V <VIN < 2.40 V 12 MHz for 2.40 V < VIN< 3.6 V MHz MHz tRISE23 Rise time, strong mode, Cload = 50 pF Port 2 or 3 or 4 pins VIN = 3.0 to 3.6 V, 10% to 90% 15 – 80 ns tRISE23L Rise time, strong mode low supply, Cload = 50 pF, Port 2 or 3 or 4 pins VIN = 1.9 to 3.0 V, 10% to 90% 15 – 80 ns tRISE01 Rise time, strong mode, Cload = 50 pF, Ports 0 or 1 VIN = 3.0 to 3.6 V, 10% to 90%, LDO enabled or disabled 10 – 50 ns tRISE01L Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 VIN = 1.9 to 3.0 V, 10% to 90%, LDO enabled or disabled 10 – 80 ns tFALL Fall time, strong mode, Cload = 50 pF, all ports VIN = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns tFALLL Fall time, strong mode low supply, Cload = 50 pF, all ports VIN = 1.9 to 3.0 V, 10% to 90% 10 – 70 ns Figure 5. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISE23 tRISE01 tRISE23L tRISE01L Document Number: 001-76581 Rev. *D tFALL tFALLL Page 21 of 40 CYRF89435 AC Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions Min Typ Max Units 50 mV overdrive does not include offset voltage. – – 100 ns AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC External Clock Specifications Symbol FOSCEXT Min Typ Max Units Frequency (external oscillator frequency) Description – 0.75 – 25.20 MHz High period – 20.60 – 5300 ns Low period – 20.60 – – ns Power-up IMO to switch – 150 – – s Document Number: 001-76581 Rev. *D Conditions Page 22 of 40 CYRF89435 AC Programming Specifications Figure 6. AC Waveform SCLK (P1[1]) TFSCLK TRSCLK SDATA (P1[0]) THSCLK TSSCLK TDSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. AC Programming Specifications Symbol Description Conditions Min Typ Max Units 1 – 20 ns – 1 – 20 ns – 40 – – ns Data hold time from falling edge of SCLK – 40 – – ns FSCLK Frequency of SCLK – 0 – 8 MHz tERASEB Flash erase time (block) – – – 18 ms tWRITE Flash block write time – – – 25 ms tDSCLK3 Data out delay from falling edge of SCLK 3.0 VDD 3.6 – – 85 ns tDSCLK2 Data out delay from falling edge of SCLK 1.9 VDD 3.0 – – 130 ns tXRST3 External reset pulse width after power-up Required to enter programming mode when coming out of sleep 300 – – s tXRES XRES pulse length – 300 – – s tVDDWAIT VDD stable to wait-and-poll hold off – 0.1 – 1 ms tVDDXRES VDD stable to XRES assertion delay – 14.27 – – ms tPOLL SDATA high pulse time – 0.01 – 200 ms tACQ “Key window” time after a VDD ramp acquire event, based on 256 ILO clocks. – 3.20 – 19.60 ms tXRESINI “Key window” time after an XRES event, based on 8 ILO clocks – 98 – 615 s tRSCLK Rise time of SCLK – tFSCLK Fall time of SCLK tSSCLK Data setup time to falling edge of SCLK tHSCLK Document Number: 001-76581 Rev. *D Page 23 of 40 CYRF89435 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 21. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard Mode Fast Mode Units Min Max Min Max 0 100 0 400 kHz fSCL SCL clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – µs tLOW LOW period of the SCL clock 4.7 – 1.3 – µs tHIGH HIGH Period of the SCL clock 4.0 – 0.6 – µs tSU;STA Setup time for a repeated START condition 4.7 – 0.6 – µs tHD;DAT Data hold time 0 3.45 0 0.90 µs – ns – µs tSU;DAT Data setup time 250 – 100[12] tSU;STO Setup time for STOP condition 4.0 – 0.6 tBUF Bus free time between a STOP and START condition 4.7 – 1.3 – µs tSP Pulse width of spikes are suppressed by the input filter – – 0 50 ns Figure 7. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 12. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-76581 Rev. *D Page 24 of 40 CYRF89435 SPI Master AC Specifications Table 22. SPI Master AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description VIN 2.4 V VIN < 2.4 V Conditions – – – – 6 3 MHz MHz DC SCLK duty cycle – – 50 – % tSETUP MISO to SCLK setup time VIN 2.4 V VIN < 2.4 V 60 100 – – – – ns ns tHOLD SCLK to MISO hold time – 40 – – ns tOUT_VAL SCLK to MOSI valid time – – – 40 ns tOUT_HIGH MOSI high time – 40 – – ns Figure 8. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 9. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-76581 Rev. *D LSB MSB TOUT_H MSB LSB Page 25 of 40 CYRF89435 SPI Slave AC Specifications Table 23. SPI Slave AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description – Conditions – – 4 MHz tLOW SCLK low time – 42 – – ns tHIGH SCLK high time – 42 – – ns tSETUP MOSI to SCLK setup time – 30 – – ns tHOLD SCLK to MOSI hold time – 50 – – ns tSS_MISO SS high to MISO valid – – – 153 ns tSCLK_MISO SCLK to MISO valid – – – 125 ns tSS_HIGH SS high time – 50 – – ns tSS_CLK Time from SS low to first SCLK – 2/SCLK – – ns tCLK_SS Time from last SCLK to SS high – 2/SCLK – – ns Figure 10. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TCLK_SS TSS_CLK TSS_HIGH /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) Document Number: 001-76581 Rev. *D THOLD MSB LSB Page 26 of 40 CYRF89435 Figure 11. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-76581 Rev. *D LSB THOLD MSB LSB Page 27 of 40 CYRF89435 Electrical Specifications – RF Section Symbol Description Min Typ Max Units Test Condition and Notes 1.9 – 3.6 VDC – 18.5 – mA Transmit power PA2. BRCLK off. – 13.7 – mA Transmit power PA12. BRCLK off Supply voltage VIN DC power supply voltage range Input to VIN pins Current consumption IDD_TX2 Current consumption – Tx IDD_TX12 IDD_RX Current consumption – Rx – 18 – mA BRCLK off IDD_IDLE1 Current consumption – idle – 1.1 – mA Configured for BRCLK output off IDD_SLPx Current consumption – sleep – 1 – µA Temperature = +25 °C. Using firmware sleep patch. Register 27 = 0x1200, for VIN ≥ 3.00 VDC only IDD_SLPr – 8 – µA Temperature = +25 °C; using firmware sleep patch Register 27 = 0x4200. IDD_SLPh – 38 – µA Temperature = +70 °C ‘C’ grade part; using firmware sleep patch Register 27 = 0x4200 0.8 VIN – 1.2 VIN V VIH Logic input high VIL Logic input low 0 – 0.8 V I_LEAK_IN Input leakage current – – 10 µA VOH Logic output high 0.8 VIN – – V IOH = 100 µA source VOL Logic output low – – 0.4 V IOL = 100 µA sink I_LEAK_OUT Output leakage current – – 10 µA MISO in tristate T_RISE_OUT Rise/fall time (SPI MISO) – 8 25 ns 7 pF cap. load T_RISE_IN Rise/fall time (SPI MOSI) – – 25 ns Tr_spi CLK rise, fall time (SPI) – – 25 ns F_OP Operating frequency range 2400 – 2482 MHz VSWR_I Antenna port mismatch (Z0 = 50 ) – <2:1 – VSWR Receive mode. Measured using LC matching circuit – <2:1 – VSWR Transmit mode. Measured using LC matching circuit VSWR_O Receive section Document Number: 001-76581 Rev. *D Requirement for error-free register reading, writing. Usage on-the-air is subject to local regulatory agency restrictions regarding operating frequency. Measured using LC matching circuit for BER 0.1% Page 28 of 40 CYRF89435 Electrical Specifications – RF Section (continued) Symbol Min Typ Max Units Test Condition and Notes – –87 – dBm Room temperature only 0-ppm crystal frequency error. RxStemp – –84 – dBm Over temperature; 0-ppm crystal frequency error. RxSppm – –84 – dBm Room temperature only 80-ppm total frequency error (± 40-ppm crystal frequency error, each end of RF link) RxStemp+ppm – –80 – dBm Over temperature; 80-ppm total frequency error (± 40-ppm crystal frequency error, each end of RF link) –20 0 – dBm Room temperature only – 1 – µs RxSbase Description Receiver sensitivity (FEC off) Rxmax-sig Maximum usable signal Ts Data (Symbol) rate For BER 0.1%. Room temperature only. Minimum Carrier/Interference ratio CI_cochannel Co-channel interference – +9 – dB –60-dBm desired signal CI_1 Adjacent channel interference, 1-MHz offset – +6 – dB –60-dBm desired signal CI_2 Adjacent channel interference, 2-MHz offset – –12 – dB –60-dBm desired signal CI_3 Adjacent channel interference, 3-MHz offset – –24 – dB –67-dBm desired signal OBB Out-of-band blocking – –27 – dBm Transmit section PAVH RF output power PAVL 30 MHz to 12.75 GHz Measured with ACX BF2520 ceramic filter on ant. pin. –67-dBm desired signal, BER 0.1%. Room temperature only. Measured using a LC matching circuit – +1 – dBm PA0 (PA_GN = 0, Reg9 = 0x1820). Room temperature only – –11.2 – dBm PA12 (PA_GN = 12, Reg9 = 0x1E20). Room temperature only. TxPfx2 Second harmonic – –45 – dBm Measured using a LC matching circuit. Room temperature only. TxPfx3 Third and higher harmonics – –45 – dBm Measured using a LC matching circuit. Room temperature only. Df1avg – 263 – kHz Modulation pattern: 11110000... Df2avg – 255 – kHz Modulation pattern: 10101010... Modulation characteristics In-band spurious emission IBS_2 2-MHz offset – – –20 dBm IBS_3 3-MHz offset – – –30 dBm IBS_4 4-MHz offset – –30 – dBm Document Number: 001-76581 Rev. *D Page 29 of 40 CYRF89435 Electrical Specifications – RF Section (continued) Symbol Description Min Typ Max Units Test Condition and Notes 1 – MHz –75 – dBc/Hz 100-kHz offset –105 – dBc/Hz 1-MHz offset –40 – +40 ppm – 100 150 µs Settle to within 30 kHz of final value. AutoCAL off. – 250 350 µs Settle to within 30 kHz of final value. AutoCAL on. – 0.17 0.3 V Measured during receive state RF VCO and PLL section Fstep Channel (Step) size L100k SSB phase noise L1M dFX0 Crystal oscillator frequency error THOP RF PLL settling time THOP_AC Relative to 12-MHz crystal reference frequency LDO voltage regulator section VDO Dropout voltage Document Number: 001-76581 Rev. *D Page 30 of 40 CYRF89435 Table 24. Initialization Timing Requirements Timing Parameter Min Max Unit Notes TRSU – 30 / 150 ms 30 ms Reset setup time necessary to ensure complete Reset for VIN = 6.5mV/s, 150 ms Reset setup time necessary to ensure complete Reset for VIN = 2mV/s TRPW 1 10 µs Reset pulse width necessary to ensure complete reset TCMIN 3 – ms Minimum recommended crystal oscillator and APLL settling time TVIN – 6.5 / 2 mV/s Maximum ramp time for VIN, measured from 0 to 100% of final voltage. For example, if VIN = 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms. If VIN = 1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms. Reset setup time necessary to ensure complete Reset for VIN = 6.5 mV/s Reset setup time necessary to ensure complete Reset for VIN = 6.5 mV/s Reset setup time necessary to ensure complete Reset for VIN=6.5 mV/s Figure 12. Initialization Flowchart Initialize CYRF89435 at power-up MCU generates negative- going RST_n pulse Wait Crystal Enable Time Initialize Registers, beginning with Reg[27] Initialization Done RST_n pulls up along with Vin Document Number: 001-76581 Rev. *D Page 31 of 40 CYRF89435 Table 25. SPI Timing Requirements Timing Parameter Min Max Unit TSSS 20 – ns Setup time from assertion of SPI_SS to CLK edge TSSH 200 – ns Hold time required deassertion of SPI_SS TSCKH 20 – ns CLK minimum high time TSCKL 20 – ns CLK minimum low time TSCK 83 – ns Maximum CLK clock is 12 MHz TSSU 10 – ns MOSI setup time TSHD 10 – ns MOSI hold time TSS_SU 10 – ns Before SPI_SS enable, CLK hold low time requirement TSS_HD 200 – ns Minimum SPI inactive time TSDO – 35 ns MISO setup time, ready to read TSDO1 – 5 ns If MISO is configured as tristate, MISO assertion time TSDO2 Notes – 250 ns If MISO is configured as tristate, MISO deassertion time T1 Min_R50 350 – ns When reading register 50 (FIFO) T1 Min 83 – ns When writing Register 50 (FIFO), or reading/writing any registers other than register 50. Figure 13. Power-on and Register Programming Sequence TVIN VIN RST_n Clock stable BRCLK Clock unstable SPI_SS SPI Activity TRPW TRSU TCMIN Write Reg[27]= 0x4200 ■ After RST_n transitions from 0 to 1, BRCLK begins running at 12-MHz clock. ■ After register initialization, CYRF89435 is ready to transmit or receive. Document Number: 001-76581 Rev. *D (not drawn to scale) Page 32 of 40 CYRF89435 Packaging Information This section illustrates the packaging specifications for the CY7C89435 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 14. 40-pin QFN (6 × 6 × 1.0 mm) LT40B 3.5 × 3.5 mm E-Pad (Sawn) Package Outline, 001-13190 001-13190 *H Important Notes ■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. ■ Pinned vias for thermal conduction are not required for the low power PSoC device. Document Number: 001-76581 Rev. *D Page 33 of 40 CYRF89435 Thermal Impedances Table 26. Thermal Impedances per Package Package 40-pin QFN [14] Typical JA [13] Typical JC 27°C/W 34°C/W Capacitance on Crystal Pins Table 27. Typical Package Capacitance on Crystal Pins Package Package Capacitance 40-pin QFN TBD Solder Reflow Specifications Table 28 shows the solder reflow temperature limits that must not be exceeded. Table 28. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C TBD TBD 40-pin QFN Notes 13. TJ = TA + Power × JA. 14. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. Document Number: 001-76581 Rev. *D Page 34 of 40 CYRF89435 Development Tool Selection Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for over half a decade. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC Programmer is available free of charge at http://www.cypress.com. Development Kits All development kits are sold at the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes: ■ PSoC Designer Software CD ■ ICE-Cube In-Circuit Emulator ■ ICE Flex-Pod for CY8C29X66A Family ■ Cat-5 Adapter ■ Mini-Eval Programming Board ■ 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ iMAGEcraft C Compiler (Registration Required) ■ ISSP Cable ■ 2 CY8C29466A-24PXI 28-pin PDIP Chip Samples Document Number: 001-76581 Rev. *D Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY8CKIT-006 PSoC® 3 LCD Segment Drive Evaluation Kit Cypress’s PSoC programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new products, but the capability to also get those products to market faster than anyone else.The ability to drive a 5 V display on 0.5 V of input and the ability to drive multiple displays on one PSoC device can translate to the ultimate in design freedom, lower BOM costs and new product differentiators with this easy to use evaluation kit.The kit contains: ■ PSoC 3 LCD Segment Drive Evaluation Board ■ 9 V Battery ■ 12 V Wall Power Supply ■ MiniProg3 Programmer / Debugger ■ USB Cable (to connect MiniProg3 to the PC) ■ Kit Stand ■ Quick Start Guide ■ Kit CD, which includes: PSoC Creator, PSoC Programmer, Projects and Documentation Device Programmers Firmware needs to be downloaded to PRoC CS device only at 3.3 V using Miniprog3 Programmer. This Programmer kit can be purchased from Cypress Store using part# ‘CY8CKIT-002 MiniProg3’. It is a small, compact programmer which connects PC via a USB 2.0 cable (provided along with CY8cKIT-002). Note: MiniProg1 Programmer should not be used as it does not support programming at 3.3 V. Page 35 of 40 CYRF89435 Accessories (Emulation and Programming) Table 29. Emulation and Programming Accessories Part Number TBD Pin Package TBD Flex-Pod Kit Foot Kit TBD Adapter TBD TBD Third Party Tools Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards. Ordering Information The following table lists the CY7C89435 PSoC devices' key package features and ordering codes. Table 30. PSoC Device Key Features and Ordering Information Package 40-pin (6 × 6 × 1.0 mm) QFN Ordering Code CYRF89435-40LTXC Flash SRAM CapSense Digital Analog XRES ADC (Bytes) (Bytes) Blocks I/O Pins Inputs Pin 32 K 2K 1 13 13 Yes Yes Ordering Code Definitions ........................................................................................ TBD Document Number: 001-76581 Rev. *D Page 36 of 40 CYRF89435 Acronyms Reference Documents Table 31. Acronyms Used in this Document Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CMOS complementary metal oxide semiconductor CPU central processing unit DAC digital-to-analog converter DC direct current EOP end of packet FSR full scale range GPIO general purpose input/output GUI graphical user interface I2C inter-integrated circuit ICE in-circuit emulator IDAC digital analog converter current ILO internal low speed oscillator IMO internal main oscillator I/O input/output ISSP in-system serial programming LCD liquid crystal display LDO low dropout (regulator) LSB least-significant bit LVD low voltage detect MCU micro-controller unit MIPS mega instructions per second MISO master in slave out MOSI master out slave in MSB most-significant bit OCD on-chip debugger POR power on reset PPOR precision power on reset PSRR power supply rejection ratio PWRSYS power system PSoC® Programmable System-on-Chip SLIMO slow internal main oscillator SRAM static random access memory SNR signal to noise ratio QFN quad flat no-lead SCL serial I2C clock SDA serial I2C data SDATA serial ISSP data SPI serial peripheral interface SS slave select SSOP shrink small outline package TC test controller USB universal serial bus USB D+ USB Data+ USB D– USB Data– WLCSP wafer level chip scale package XTAL crystal ■ Technical reference manual for CY8C20xx6 devices ■ In-system Serial Programming (ISSP) protocol for 20xx6 (AN2026C) ■ Host Sourced Serial Programming for 20xx6 devices (AN59389) Document Number: 001-76581 Rev. *D Document Conventions Units of Measure Table 32. Units of Measure Symbol °C dB fF g Hz KB Kbit KHz Ksps k MHz M A F H s W mA ms mV nA nF ns nV W pA pF pp ppm ps sps s V W Unit of Measure degree Celsius decibels femtofarad gram hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatt milliampere millisecond millivolt nanoampere nanofarad nanosecond nanovolt ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volt watt Page 37 of 40 CYRF89435 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Glossary Crosspoint connection Connection between any GPIO combination via analog multiplexer bus. Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time Hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. I2C It is a serial multi-master bus used to connect low speed peripherals to MCU. Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Latch-up current Current at which the latch-up test is conducted according to JESD78 standard (at 125 degree Celsius) Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Scan The conversion of all sensor capacitances to digital values. Setup time Period required to prepare a device, machine, process, or system for it to be ready to function. Signal-to-noise ratio The ratio between a capacitive finger signal and system noise. SPI Serial peripheral interface is a synchronous serial data link standard. Document Number: 001-76581 Rev. *D Page 38 of 40 CYRF89435 Document History Page Document Title: CYRF89435, PRoC™ - CapSense® Document Number: 001-76581 Revision ECN Orig. of Change Submission Date ** 3545779 ANTG 03/13/2012 New silicon document *A 3591949 ANTG 05/14/2012 Modified title. Updated status “Company Confidential” of the datasheet. Changed “PRoC NL - CapSense” to “PRoC-CS” everywhere in the datasheet. Updated the Electrical Specifications. Updated the RF specifications. *B 3714928 AKHL 08/16/2012 Major text update. Updated the pinout (Figure 3). *C 3747532 AKHL 09/25/2012 Removed “Company Confidential” tag in the header. Replaced package diagram spec with 001-13190. *D 3784571 AKHL 10/18/2012 Updated PSoC® Functional Overview (Added Transmit Power Control). Updated Electrical Specifications – RF Section (Replaced CYRF8935 with CYRF89435 in Figure 12 and also in the last bullet point below Figure 13). Updated Development Tool Selection (Updated Evaluation Tools (Removed “CY8CKIT-002 - MiniProg 3”), updated Device Programmers (Removed “CY3207ISSP In-System Serial Programmer (ISSP)”, added the content from the removed section “CY8CKIT-002 - MiniProg 3” with slight modification). Updated in new template. Document Number: 001-76581 Rev. *D Description of Change Page 39 of 40 CYRF89435 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-76581 Rev. *D Revised October 18, 2012 Page 40 of 40 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.