CYPRESS CY8C27466

PSoC™ Mixed Signal Array
Preliminary Data Sheet
CY8C27466, CY8C27566, and CY8C27666
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25 V Operating Voltage
❐ Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ 24/48 MHz with Optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 1K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 40 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
SYSTEM BUS
SRAM
1K
Global Analog Interconnect
SROM
Flash 32K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Clocks
Analog
Block
Array
(2 Rows,
8 Blocks)
(4 Columns,
12 Blocks)
Two
Multiply
Accum.
POR and LVD
Decimator
I 2C
System Resets
SYSTEM RESOURCES
June 2004
Analog
Ref
Analog
Input
Muxing
Internal
Voltage
Ref.
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x66 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
ANALOG SYSTEM
Digital
Block Array
❐ I2C Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Analog
Drivers
PSoC
CORE
Global Digital Interconnect
■ Additional System Resources
The PSoC Core
Switch
Mode
Pump
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 18 vec-
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12019 Rev. *B
1
CY8C27x66 Preliminary Data Sheet
PSoC™ Overview
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Port 5
Port 4
Port 3
Digital Clocks
From Core
Memory encompasses 32K of Flash for program storage, 1 KB
of SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Port 1
Port 0
To Analog
System
To System Bus
DIGITAL SYSTEM
The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
8
8
Row 1
DBB10
DBB11
DCB13
4
GIE[7:0]
The Digital System
DCB12
4
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
Row Input
Configuration
8
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configurations include those listed below.
Port 2
GOE[7:0]
GOO[7:0]
Digital System Block Diagram
The Analog System
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 2)
■
SPI master and slave (up to 2 each)
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application
requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.
■
I2C slave and master (1 available as a System Resource)
■
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
Analog to digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
■
IrDA (up to 2)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
Pseudo Random Sequence Generators (8 to 32 bit)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to
93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Characteristics” on page 3.
June 1, 2004
Document No. 38-12019 Rev. *B
2
CY8C27x66 Preliminary Data Sheet
■
Peak detectors
■
Many other topologies possible
PSoC™ Overview
Additional System Resources
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The number of blocks is dependant on the device family
which is detailed in the table titled “PSoC Device Characteristics” on page 3.
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
P0[7]
P2[3]
P2[1]
System Resources, some of which have been previously listed,
provide additSNRional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch
mode pump, low voltage detection, and power on reset. Brief
statements describing the merits of each system resource are
presented below.
■
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate to assist in both general math as well
as digital filters.
■
The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
PSOC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups.
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
PSoC Part
Number
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
PSoC Device Characteristics
CY8C29x66
up to
64
4
16
12
4
4
12
CY8C27x66
up to
44
2
8
12
4
4
12
CY8C27x43
up to
44
2
8
12
4
4
12
M8C Interface (Address Bus, Data Bus, Etc.)
CY8C24x23
up to
24
1
4
12
2
2
6
Analog System Block Diagram
CY8C22x13
up to
16
1
4
8
1
1
3
Analog Reference
Interface to
Digital System
June 1, 2004
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
Document No. 38-12019 Rev. *B
3
CY8C27x66 Preliminary Data Sheet
PSoC™ Overview
Getting Started
Development Tools
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows 98, Windows
NT 4.0, Windows 2000, Windows Millennium (Me), or Windows
XP. (Reference the PSoC Designer Functional Flow diagram
below.)
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Results
Free PSoC "Tele-training" is available for beginners and taught
by a live marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Commands
Tele-Training
Context
Sensitive
Help
Graphical Designer
Interface
PSoCTM
Designer
Importable
Design
Database
PSoC
Configuration
Sheet
Device
Database
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
PSoCTM
Designer
Core
Engine
Application
Database
Manufacturing
Information
File
Project
Database
User
Modules
Library
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
June 1, 2004
Emulation
Pod
Document No. 38-12019 Rev. *B
In-Circuit
Emulator
Device
Programmer
PSoC Designer Subsystems
4
CY8C27x66 Preliminary Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
June 1, 2004
Document No. 38-12019 Rev. *B
PSoC Development Tool Kit
5
CY8C27x66 Preliminary Data Sheet
PSoC™ Overview
User Modules and the PSoC
Development Process
the device to your specification and provides the high-level user
module API functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
User
Module
Selection
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a pictorial environment (GUI) for
configuring the hardware. You pick the user modules you need
for your project and map them onto the PSoC blocks with pointand-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
June 1, 2004
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides highlevel functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service routines that you can adapt as needed.
Placement
and
Parameter
-ization
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a ROM file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger downloads the ROM image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document No. 38-12019 Rev. *B
6
CY8C27x66 Preliminary Data Sheet
PSoC™ Overview
Document Conventions
Table of Contents
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
POR
power on reset
PPOR
precision power on reset
PSoC™
Programmable System-on-Chip
PWM
pulse width modulator
RAM
random access memory
ROM
read only memory
SC
switched capacitor
SMP
switch mode pump
TBD
to be determined
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized
into the following chapters and sections.
1.
Pin Information ............................................................. 8
1.1 Pinouts ................................................................... 8
1.1.1 28-Pin Part Pinout ..................................... 8
1.1.2 44-Pin Part Pinout ..................................... 9
1.1.3 48-Pin Part Pinouts .................................. 10
2.
Register Reference ..................................................... 12
2.1 Register Conventions ........................................... 12
2.1.1 Abbreviations Used .................................. 12
2.2 Register Mapping Tables ..................................... 12
3.
Electrical Specifications ............................................ 15
3.1 Absolute Maximum Ratings ................................ 16
3.2 Operating Temperature ....................................... 16
3.3 DC Electrical Characteristics ................................ 17
3.3.1 DC Chip-Level Specifications ................... 17
3.3.2 DC General Purpose IO Specifications .... 17
3.3.3 DC Operational Amplifier Specifications ... 18
3.3.4 DC Analog Output Buffer Specifications ... 19
3.3.5 DC Switch Mode Pump Specifications ..... 20
3.3.6 DC Analog Reference Specifications ....... 21
3.3.7 DC Analog PSoC Block Specifications ..... 22
3.3.8 DC POR, SMP, and LVD Specifications ... 23
3.3.9 DC Programming Specifications ............... 24
3.4 AC Electrical Characteristics ................................ 25
3.4.1 AC Chip-Level Specifications ................... 25
3.4.2 AC General Purpose IO Specifications .... 27
3.4.3 AC Operational Amplifier Specifications ... 28
3.4.4 AC Digital Block Specifications ................. 30
3.4.5 AC Analog Output Buffer Specifications ... 31
3.4.6 AC External Clock Specifications ............. 32
3.4.7 AC Programming Specifications ............... 32
3.4.8 AC I2C Specifications ............................... 33
4.
Packaging Information ............................................... 34
4.1 Packaging Dimensions ......................................... 34
4.2 Thermal Impedances .......................................... 37
4.3 Capacitance on Crystal Pins ............................... 37
5.
Ordering Information .................................................. 38
5.1 Ordering Code Definitions ................................... 38
6.
Sales and Service Information .................................. 39
6.1 Revision History .................................................. 39
6.2 Copyrights ............................................................ 39
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
June 1, 2004
Document No. 38-12019 Rev. *B
7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C27x66 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C27x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
28-Pin Part Pinout
Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
Type
Digital
Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
IO
IO
I
IO
IO
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
I
I
Power
Power
IO
IO
IO
IO
Input
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
IO
IO
I
Power
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
CY8C27466 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
Active high pin reset with internal pull down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
May 2004
Document No. 38-12019 Rev. *B
8
CY8C27x66 Preliminary Data Sheet
1.1.2
1. Pin Information
44-Pin Part Pinout
Table 1-2. 44-Pin Part Pinout (TQFP)
IO
IO
IO
IO
IO
IO
IO
IO
IO
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
38
39
40
41
42
43
44
IO
I
I
I
IO
IO
I
Power
IO
IO
IO
IO
IO
I
IO
IO
I
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P0[7], AI
Vdd
P0[6],
P0[4],
P0[2],
P0[0],
P2[6], External VREF
38
37
36
35
34
AI
AIO
AIO
AI
P0[3], AIO
P0[5], AIO
P2[7]
P0[1], AI
44
Active high pin reset with internal pull down.
22
29
30
31
32
33
34
35
36
37
Input
Optional External Clock Input (EXTCLK)
33
32
31
30
29
28
27
26
25
24
23
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P1[6]
P3[0]
IO
IO
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
P4[0]
P4[2]
11
TQFP
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
IO
IO
IO
IO
IO
IO
IO
IO
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
1
2
3
4
5
6
7
8
9
10
16
17
18
19
20
21
20
21
22
23
24
25
26
27
28
Power
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
I2C SCL, XTALin, P1[1]
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
14
15
IO
IO
IO
IO
IO
IO
IO
IO
Switch Mode Pump (SMP) connection to
external components required.
I2C SDA, P1[5]
P1[3]
9
10
11
12
13
14
15
16
17
18
19
Direct switched capacitor block input.
Direct switched capacitor block input.
12
13
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
CY8C27566 44-Pin PSoC Device
Description
43
42
41
40
39
Pin
Name
P3[1]
1
2
3
4
5
6
7
8
Type
Digital Analog
IO
IO
I
IO
I
IO
IO
IO
IO
Power
I2C SCL, P1[7]
Pin
No.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
June 1, 2004
Document No. 38-12019 Rev. *B
9
CY8C27x66 Preliminary Data Sheet
1.1.3
1. Pin Information
48-Pin Part Pinouts
Table 1-3. 48-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
Digital Analog
IO
I
IO
IO
IO
IO
IO
I
IO
IO
IO
I
IO
I
IO
IO
IO
IO
Power
14
15
16
17
18
19
20
21
22
23
24
25
26
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
IO
IO
IO
IO
IO
IO
IO
IO
47
48
IO
IO
IO
Input
I
I
I
IO
IO
I
Power
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Pin
Name
CY8C27666 48-Pin PSoC Device
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL)
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VREF)
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
P0[6]
Vdd
Analog column mux input.
Supply voltage.
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK)
Active high pin reset with internal pull down.
LEGEND: A = Analog, I = Input, and O = Output.
June 1, 2004
Document No. 38-12019 Rev. *B
10
CY8C27x66 Preliminary Data Sheet
1. Pin Information
Table 1-4. 48-Pin Part Pinout (MLF*)
Direct switched capacitor block input.
P2[1]
Direct switched capacitor block input.
3
IO
P4[7]
4
IO
P4[5]
5
IO
P4[3]
6
IO
P3[7]
9
IO
P3[5]
10
IO
P3[3]
11
IO
P3[1]
12
IO
P5[3]
13
IO
P5[1]
14
IO
P1[7]
I2C Serial Clock (SCL)
15
IO
P1[5]
I2C Serial Data (SDA)
16
IO
P1[3]
17
IO
18
Power
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL)
Vss
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA)
19
IO
P1[0]
20
IO
P1[2]
21
IO
P1[4]
22
IO
P1[6]
23
IO
P5[0]
24
IO
P5[2]
25
IO
P3[0]
26
IO
P3[2]
27
IO
P3[4]
28
IO
29
Optional External Clock Input (EXTCLK)
(Top View)
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high pin reset with internal pull down.
30
IO
P4[0]
31
IO
P4[2]
32
IO
P4[4]
33
IO
34
IO
I
P2[0]
35
IO
I
P2[2]
Direct switched capacitor block input.
36
IO
P2[4]
External Analog Ground (AGND)
37
IO
P2[6]
External Voltage Reference (VREF)
38
IO
I
P0[0]
Analog column mux input.
39
IO
IO
P0[2]
Analog column mux input and column output.
40
IO
IO
P0[4]
Analog column mux input and column output.
41
IO
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
42
MLF
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
IO
1
2
3
4
5
6
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
8
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
15
16
Switch Mode Pump (SMP) connection to
external components required.
I2C SDA, P1[5]
P1[3]
SMP
48
47
46
45
44
43
P4[1]
Power
38
37
P2[3]
I
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
I
IO
42
41
40
39
IO
2
P2[5]
P2[7]
P0[1], AI
1
7
CY8C27666 48-Pin PSoC Device
Description
P0[3], AIO
P0[5], AIO
P0[7], AI
Pin
Name
Analog
13
14
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
Direct switched capacitor block input.
43
IO
I
P0[7]
Analog column mux input.
44
IO
IO
P0[5]
Analog column mux input and column output.
45
IO
IO
P0[3]
Analog column mux input and column output.
46
IO
I
P0[1]
Analog column mux input.
47
IO
P2[7]
48
IO
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to the ground (Vss).
June 1, 2004
Document No. 38-12019 Rev. *B
11
2. Register Reference
This chapter lists the registers of the CY8C27x66 PSoC device by way of mapping tables, in offset order. For detailed register information, reference the PSoC™ Mixed Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
2.2
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Convention
Description
RW
Read and write register or bit(s)
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
June 2004
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is
set, the user is said to be in the “extended” address space or
the “configuration” registers.
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Document No. 38-12019 Rev. *B
12
CY8C27x66 Preliminary Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Document No. 38-12019 Rev. *B
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Addr
(0,Hex)
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDIOLT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(0,Hex)
June 1, 2004
Name
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
RW
4C
0D
RW
4D
0E
RW
4E
0F
RW
4F
10
RW
50
11
RW
51
12
RW
52
13
RW
53
14
RW
54
15
RW
55
16
RW
56
17
RW
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
RW
5F
DBB00DR0
20
#
AMX_IN
60
DBB00DR1
21
W
61
DBB00DR2
22
RW
62
DBB00CR0
23
#
ARF_CR
63
DBB01DR0
24
#
CMP_CR0
64
DBB01DR1
25
W
ASY_CR
65
DBB01DR2
26
RW
CMP_CR1
66
DBB01CR0
27
#
67
DCB02DR0
28
#
68
DCB02DR1
29
W
69
DCB02DR2
2A
RW
6A
DCB02CR0
2B
#
6B
DCB03DR0
2C
#
TMP0_DR
6C
DCB03DR1
2D
W
TMP1_DR
6D
DCB03DR2
2E
RW
TMP2_DR
6E
DCB03CR0
2F
#
TMP3_DR
6F
DBB10DR0
30
#
ACB00CR3
70
DBB10DR1
31
W
ACB00CR0
71
DBB10DR2
32
RW
ACB00CR1
72
DBB10CR0
33
#
ACB00CR2
73
DBB11DR0
34
#
ACB01CR3
74
DBB11DR1
35
W
ACB01CR0
75
DBB11DR2
36
RW
ACB01CR1
76
DBB11CR0
37
#
ACB01CR2
77
DCB12DR0
38
#
ACB02CR3
78
DCB12DR1
39
W
ACB02CR0
79
DCB12DR2
3A
RW
ACB02CR1
7A
DCB12CR0
3B
#
ACB02CR2
7B
DCB13DR0
3C
#
ACB03CR3
7C
DCB13DR1
3D
W
ACB03CR0
7D
DCB13DR2
3E
RW
ACB03CR1
7E
DCB13CR0
3F
#
ACB03CR2
7F
Blank fields are Reserved and should not be accessed.
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
13
CY8C27x66 Preliminary Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
RDI3RI
C8
RDI3SYN
C9
RDI3IS
CA
RDI3LT0
CB
RDI3LT1
CC
RDI3RO0
CD
RDI3RO1
CE
CF
GDI_O_IN
D0
GDI_E_IN
D1
GDI_O_OU
D2
GDI_E_OU
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
OSC_GO_EN DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
E5
E6
E7
IMO_TR
E8
ILO_TR
E9
BDG_TR
EA
ECO_TR
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
CPU_F
F7
F8
F9
FLS_PR1
FA
FB
FC
FD
CPU_SCR1
FE
CPU_SCR0
FF
Document No. 38-12019 Rev. *B
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
RW
RW
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDIOLT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(1,Hex)
June 1, 2004
Name
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
RW
4C
0D
RW
4D
0E
RW
4E
0F
RW
4F
10
RW
50
11
RW
51
12
RW
52
13
RW
53
14
RW
54
15
RW
55
16
RW
56
17
RW
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00FN
20
RW
CLK_CR0
60
DBB00IN
21
RW
CLK_CR1
61
DBB00OU
22
RW
ABF_CR0
62
23
AMD_CR0
63
DBB01FN
24
RW
64
DBB01IN
25
RW
65
DBB01OU
26
RW
AMD_CR1
66
27
ALT_CR0
67
DCB02FN
28
RW
ALT_CR1
68
DCB02IN
29
RW
CLK_CR2
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
TMP0_DR
6C
DCB03IN
2D
RW
TMP1_DR
6D
DCB03OU
2E
RW
TMP2_DR
6E
2F
TMP3_DR
6F
DBB10FN
30
RW
ACB00CR3
70
DBB10IN
31
RW
ACB00CR0
71
DBB10OU
32
RW
ACB00CR1
72
33
ACB00CR2
73
DBB11FN
34
RW
ACB01CR3
74
DBB11IN
35
RW
ACB01CR0
75
DBB11OU
36
RW
ACB01CR1
76
37
ACB01CR2
77
DCB12FN
38
RW
ACB02CR3
78
DCB12IN
39
RW
ACB02CR0
79
DCB12OU
3A
RW
ACB02CR1
7A
3B
ACB02CR2
7B
DCB13FN
3C
RW
ACB03CR3
7C
DCB13IN
3D
RW
ACB03CR0
7D
DCB13OU
3E
RW
ACB03CR1
7E
3F
ACB03CR2
7F
Blank fields are Reserved and should not be accessed.
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
RW
#
#
14
3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C27x66 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
5.25
4.75
4.75
Vdd Voltage
Vdd Voltage
lid ng
V a r a ti n
pe gio
Re
O
5.25
SLIMO Mode = 0
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
3.60
SLIMO
Mode=0
SLIMO
Mode=1
3.00
3.00
93 kHz
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
Figure 3-1a. Voltage versus Operating Frequency
Figure 3-1b. Voltage versus IMO Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
degree Celsius
µW
micro watts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nano ampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
pico ampere
MΩ
megaohm
pF
pico farad
µA
micro ampere
pp
peak-to-peak
µF
micro farad
ppm
µH
micro henry
ps
picosecond
µs
microsecond
sps
samples per second
µV
micro volts
σ
sigma: one standard deviation
micro volts root-mean-square
V
volts
µVrms
June 2004
parts per million
Document No. 38-12019 Rev. *B
15
CY8C27x66 Preliminary Data Sheet
3.1
3. Electrical Specifications
Absolute Maximum Ratings
Table 3-2: Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
–
+100
oC
TA
Ambient Temperature with Power Applied
-40
–
+85
o
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss-0.5
–
Vdd+0.5
V
–
DC Voltage Applied to Tri-state
Vss-0.5
–
Vdd+0.5
V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog
Driver
-50
–
+50
mA
–
Static Discharge Voltage
2000
–
–
V
–
Latch-up Current
–
–
200
mA
3.2
Notes
Higher storage temperatures will reduce data
retention time.
C
Operating Temperature
Table 3-3: Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
June 1, 2004
Document No. 38-12019 Rev. *B
Notes
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 37. The user must limit the power consumption to comply with this requirement.
16
CY8C27x66 Preliminary Data Sheet
3.3
3.3.1
3. Electrical Specifications
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-4: DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.00
–
5.25
V
IDD
Supply Current
–
8
14
mA
Conditions are 5.0V, 25 oC, 3 MHz, 48 MHz disabled. VC1=1.5 MHz, VC2=93.75 kHz,
VC3=0.366 kHz.
IDD3
Supply Current
–
5
9
mA
Conditions are Vdd=3.3V, TA=25 oC, CPU=3
MHz, 48 MHz=Disabled, VC1=1.5 MHz,
VC2=93.75 kHz, VC3=0.366 Khz.
IDDP
Supply current when IMO = 6 MHz
–
2
3
mA
Conditions are Vdd=3.3V, TA=25 oC, CPU=3
MHz, 48 MHz=Disabled, VC1=1.5 MHz,
VC2=93.75 kHz, VC3=0.366 Khz.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active. Lower 3/4 temperature
range.
–
3
10
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC <=TA <= 55 oC.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active. Higher 1/4 temperature
range (hot).
–
4
25
µA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA <= 85 oC.
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
internal slow oscillator, and 32 kHz crystal oscillator active.
Lower 3/4 temperature range.
–
4
12
µA
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC <= TA <=
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and 32 kHz crystal oscillator active. Higher 1/4 temperature
range (hot).
–
Reference Voltage (Bandgap)
1.28
ISBXTLH
VREF
3.3.2
55 oC.
5
µA
27
Conditions are with properly loaded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA <=
85 oC.
1.3
1.32
V
Trimmed for appropriate Vdd.
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-5: DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
4
5.6
8
kΩ
Pull down Resistor
4
5.6
8
kΩ
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 IO switching, 4 per side)
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 IO switching, 4 per side)
0.8
V
Vdd = 3.0 to 5.25
V
Vdd = 3.0 to 5.25
RPU
Pull up Resistor
RPD
VOH
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
June 1, 2004
Document No. 38-12019 Rev. *B
17
CY8C27x66 Preliminary Data Sheet
3.3.3
3. Electrical Specifications
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor
PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to
5V at 25°C and are for design guidance only.
Table 3-6: 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value) Low Power
–
1.6
10
mV
Input Offset Voltage (absolute value) Mid Power
–
1.3
8
mV
Input Offset Voltage (absolute value) High Power
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range. All Cases, except highest.
0.0
–
Vdd
V
V
Power = High, Opamp Bias = High
0.5
–
Vdd-0.5
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (worst case internal load)
Vdd-.01
–
–
V
VOLOWOA
Low Output Voltage Swing (worst case internal load)
–
–
0.1
V
ISOA
Supply Current (including associated AGND buffer)
Power=Low
–
150
200
µA
Power=Low, Opamp Bias=High
–
300
400
µA
Power=Medium
–
600
800
µA
Power=Medium, Opamp Bias=High
–
1200
1600
µA
Power=High
–
2400
3200
µA
Power=High, Opamp Bias=High
–
4600
6400
µA
Supply Voltage Rejection Ratio
60
–
–
dB
PSRROA
Opamp bias = high.
Important Note Do not use the combination of Power = High and Opamp Bias = High for 3.3V operations.
Table 3-7: 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Input Offset Voltage (absolute value) Low Power
–
1.65
10
mV
Input Offset Voltage (absolute value) Mid Power
–
1.32
8
mV
Notes
Opamp bias = high.
High Power is 5 Volt Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
µV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 µA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0
–
Vdd
V
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (worst case internal load)
Vdd-.01
–
–
V
VOLOWOA
Low Output Voltage Swing (worst case internal load)
–
–
0.1
V
ISOA
Supply Current (including associated AGND buffer)
Power=Low
–
150
200
µA
Power=Low, Opamp Bias=High
–
300
400
µA
Power=Medium
–
600
800
µA
Power=Medium, Opamp Bias=High
–
1200
1600
µA
Power=High
–
2400
3200
µA
Supply Voltage Rejection Ratio
50
–
–
dB
PSRROA
June 1, 2004
Document No. 38-12019 Rev. *B
18
CY8C27x66 Preliminary Data Sheet
3.3.4
3. Electrical Specifications
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-8: 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
1
Ω
Power = High
–
–
1
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.3 –
–
V
0.5 x Vdd + 1.3 –
–
V
VOHIGHOB
Power = High
VOLOWOB
ISOB
PSRROB
Notes
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd - 1.3
V
Power = High
–
–
0.5 x Vdd - 1.3
V
Power = Low
–
1.1
2
mA
Power = High
–
2.6
5
mA
Supply Voltage Rejection Ratio
40
–
–
dB
Supply Current Including Bias Cell (No Load)
Table 3-9: 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
µV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
10
Ω
Power = High
–
–
10
Ω
VOHIGHOB
VOLOWOB
ISOB
High Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.0 –
–
V
Power = High
0.5 x Vdd + 1.0 –
–
V
Power = Low
–
–
0.5 x Vdd - 1.0
V
Power = High
–
–
0.5 x Vdd - 1.0
V
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)
Supply Current Including Bias Cell (No Load)
0.8
1
mA
Power = High
–
2.0
8
mA
Supply Voltage Rejection Ratio
60
–
–
dB
Power = Low
PSRROB
Notes
June 1, 2004
Document No. 38-12019 Rev. *B
19
CY8C27x66 Preliminary Data Sheet
3.3.5
3. Electrical Specifications
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-10: DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5V Output voltage at Vdd from Pump
4.75
5.0
5.25
V
Average, neglecting ripple. Configuration with a 2 µH inductor, 10 µF capacitor, and Schottky diode (see Figure 3-2).
SMP trip voltage is set to 5.00V.
VPUMP 3V
3V Output voltage at Vdd from Pump
3.00
3.25
3.60
V
Average, neglecting ripple. Configuration with a 2 µH inductor, 10 µF capacitor, and Schottky diode (see Figure 3-2).
SMP trip voltage is set to 3.25V.
IPUMP
Available Output Current
VBAT= 1.5V, Vo= 3.25V
8
–
–
mA
VBAT= 1.8V, Vo= 5.0V
5
–
–
mA
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2). SMP trip voltage is set to
5.00V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2). SMP trip voltage is set to
3.25V.
VBATSTART
Minimum Input Voltage from Battery to
Start Pump
1.1
–
–
V
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
∆VPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
∆VPUMP_Load
Load Regulation
–
5
–
%VO
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
∆VPUMP_Ripple Output Voltage Ripple (depends on cap/
load)
–
25
–
mVpp
Configuration with a 2 µH inductor, 10 µF capacitor, load is
5mA, and Schottky diode (see Figure 3-2).
–
Efficiency
35
50
–
%
Configuration with a 2 µH inductor, 10 µF capacitor, load is
5mA, and Schottky diode (see Figure 3-2). SMP trip voltage
is set to 3.25V.
FPUMP
Switching Frequency
–
1.4
–
MHz
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
DCPUMP
Switching Duty Cycle
–
50
–
%
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
Configuration with a 2 µH inductor, 10 µF capacitor, and
Schottky diode (see Figure 3-2).
D1
Vdd
C1
VBAT
+
SMP
Battery
PSoCTM
Vss
Figure 3-2. Basic Switch Mode Pump Circuit
June 1, 2004
Document No. 38-12019 Rev. *B
20
CY8C27x66 Preliminary Data Sheet
3.3.6
3. Electrical Specifications
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Table 3-11: 5V DC Analog Reference Specifications
Symbol
Description
VBG5
Bandgap Voltage Reference 5V
–
AGND = Vdd/2a
–
AGND = 2*BandGapa
Min
CT Block Power = High
CT Block Power = High
–
AGND = P2[4] (P2[4] =
AGND =
AGND =
V
Vdd/2 - 0.017
Vdd/2
Vdd/2 + 0.017
V
2.52
2.60
2.72
V
P2[4] - 0.013
P2[4]
P2[4] + 0.013
V
1.27
1.3
1.33
V
2.03
2.08
2.13
V
-0.034
0.000
0.034
V
Vdd/2 + 1.218
Vdd/2 + 1.3
Vdd/2 + 1.382
V
3.75
3.9
4.05
V
P2[6] + 2.478
P2[6] + 2.6
P2[6] + 2.722
V
P2[4] + 1.218
P2[4] + 1.30
P2[4] + 1.382
V
P2[4] + P2[6] - 0.058
P2[4] + P2[6]
P2[4] + P2[6] + 0.058
V
2.50
2.60
2.70
V
4.02
4.16
4.29
V
Vdd/2 - 1.369
Vdd/2 - 1.30
Vdd/2 - 1.231
V
1.20
1.30
1.40
V
2.489 - P2[6]
2.6 - P2[6]
2.711 - P2[6]
V
P2[4] - 1.368
P2[4] - 1.30
P2[4] - 1.232
V
P2[4] - P2[6] - 0.042
P2[4] - P2[6]
P2[4] - P2[6] + 0.042
V
1.6*BandGapa
CT Block Power = High
–
Units
1.32
BandGapa
CT Block Power = High
–
Max
1.30
Vdd/2)a
CT Block Power = High
–
Typ
1.28
AGND Column to Column Variation
(AGND=Vdd/2)a
CT Block Power = High
–
RefHi = Vdd/2 + BandGap
–
RefHi = 3*BandGap
–
RefHi = 2*BandGap + P2[6] (P2[6] = 1.3V)
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
–
RefHi = 2*BandGap
–
RefHi = 3.2*BandGap
–
RefLo = Vdd/2 – BandGap
–
RefLo = BandGap
–
RefLo = 2*BandGap - P2[6] (P2[6] = 1.3V)
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
Ref Control Power = High
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
June 1, 2004
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21
CY8C27x66 Preliminary Data Sheet
3. Electrical Specifications
Table 3-12: 3.3V DC Analog Reference Specifications
Symbol
Description
VBG33
Bandgap Voltage Reference 3.3V
–
AGND = Vdd/2a
Min
CT Block Power = High
–
AGND =
2*BandGapa
–
AGND = P2[4] (P2[4] = Vdd/2)
–
AGND = BandGapa
CT Block Power = High
CT Block Power = High
AGND =
AGND Column to Column Variation
RefHi = Vdd/2 + BandGap
RefHi = 3*BandGap
RefHi = 2*BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
–
RefHi = 2*BandGap
–
RefHi = 3.2*BandGap
Ref Control Power = High
Ref Control Power = High
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2*BandGap - P2[6] (P2[6] = 0.5V)
V
1.27
1.30
1.33
V
2.03
2.08
2.13
V
-0.034
0.000
0.034
mV
P2[4] + P2[6] - 0.042
P2[4] + P2[6] - 0.0
P2[4] + P2[6] + 0.042
V
2.50
2.60
2.70
V
P2[4] - P2[6] + 0.0
P2[4] - P2[6] + 0.036
V
Not Allowed
Ref Control Power = High
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
Ref Control Power = High
–
P2[4] + 0.009
Not Allowed
Ref Control Power = High
–
P2[4] + 0.0
Not Allowed
Ref Control Power = High
–
P2[4] - 0.009
Not Allowed
Ref Control Power = High
–
V
Not Allowed
Ref Control Power = High
–
Vdd/2 + 0.017
Not Allowed
Ref Control Power = High
–
Vdd/2 - 0.0
Not Allowed
Ref Control Power = High
–
Vdd/2 - 0.017
Not Allowed
Ref Control Power = High
–
V
(AGND=Vdd/2)a
CT Block Power = High
–
Units
1.32
1.6*BandGapa
CT Block Power = High
–
Max
1.30
Not Allowed
CT Block Power = High
–
Typ
1.28
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Ref Control Power = High
P2[4] - P2[6] - 0.036
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
3.3.7
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-13: DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.24
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
June 1, 2004
Document No. 38-12019 Rev. *B
Notes
22
CY8C27x66 Preliminary Data Sheet
3.3.8
3. Electrical Specifications
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-14: DC POR, SMP, and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0]=00b
VPPOR1R
PORLEV[1:0]=01b
VPPOR2R
PORLEV[1:0]=10b
2.908
–
4.394
V
–
4.548
V
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0]=00b
VPPOR1
PORLEV[1:0]=01b
VPPOR2
PORLEV[1:0]=10b
2.816
–
4.394
V
–
4.548
V
V
PPOR Hysteresis
VPH0
PORLEV[1:0]=00b
–
92
–
mV
VPH1
PORLEV[1:0]=01b
–
0
–
mV
VPH2
PORLEV[1:0]=10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0]=000b
2.863
2.921
2.979a
V
VLVD1
VM[2:0]=001b
2.963
3.023
3.083
VLVD2
VM[2:0]=010b
3.070
3.133
3.196
VLVD3
VM[2:0]=011b
3.920
4.00
4.080
VLVD4
VM[2:0]=100b
4.393
4.483
4.573
VLVD5
VM[2:0]=101b
4.550
4.643
4.736b
VLVD6
VM[2:0]=110b
4.632
4.727
4.822
VLVD7
VM[2:0]=111b
4.718
4.814
4.910
V
V
V
V
V
V
V
V
Vdd Value for SMP Trip
VPUMP0
VM[2:0]=000b
2.963
3.023
3.083
VPUMP1
VM[2:0]=001b
3.033
3.095
3.157
VPUMP2
VM[2:0]=010b
3.185
3.250
3.315
VPUMP3
VM[2:0]=011b
4.110
4.194
4.278
VPUMP4
VM[2:0]=100b
4.550
4.643
4.736
VPUMP5
VM[2:0]=101b
4.632
4.727
4.822
VPUMP6
VM[2:0]=110b
4.719
4.815
4.911
VPUMP7
VM[2:0]=111b
4.900
5.000
5.100
V
V
V
V
V
V
V
V
V
a. Always greater than 50 mV above PPOR (PORLEV=00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV=10) for falling supply.
June 1, 2004
Document No. 38-12019 Rev. *B
23
CY8C27x66 Preliminary Data Sheet
3.3.9
3. Electrical Specifications
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-15: DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
ICCP
Supply Current During Programming or Verify
–
10
30
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss+0.75
V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
The PSoC devices use an adaptive algorithm to enhance endurance over the industrial temperature range (-40°C to +85°C ambient). Any temperature range within a 50°C
span between 0°C and 85°C is considered constant with respect to endurance enhancements. For instance, if room temperature (25°C) is the nominal operating temperature, then the range from 0°C to 50°C can be approximated by the constant value 25 and a temperature sensor is not needed.
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
June 1, 2004
Document No. 38-12019 Rev. *B
24
CY8C27x66 Preliminary Data Sheet
3.4
3. Electrical Specifications
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 3-16: AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO
Internal Main Oscillator Frequency
23.4
24
24.6a
MHz
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3b,c
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2a,b,d
MHz
F24M
Digital PSoC Block Frequency
0
24
24.6b,e,d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWLOW
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
300
600f
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
µs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2a,c
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
µs
a.
b.
c.
d.
e.
f.
Trimmed. Utilizing factory trim values.
Refer to the AC Digital Block Specifications below.
ns
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V.
See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for 3.3V operation.
3.0V < 5.25V.
The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level
32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC ≤ TA ≤ 85 oC.
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 3-3. PLL Lock Timing Diagram
June 1, 2004
Document No. 38-12019 Rev. *B
25
CY8C27x66 Preliminary Data Sheet
3. Electrical Specifications
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
June 1, 2004
Document No. 38-12019 Rev. *B
26
CY8C27x66 Preliminary Data Sheet
3.4.2
3. Electrical Specifications
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-17: AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO Operating Frequency
0
–
12
MHz
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
90%
GPIO
Pin
10%
TRiseF
TRiseS
TFallF
TFallS
Figure 3-8. GPIO Timing Diagram
June 1, 2004
Document No. 38-12019 Rev. *B
27
CY8C27x66 Preliminary Data Sheet
3.4.3
3. Electrical Specifications
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-18: 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
Description
Min
Typ
Max
Power = Low
–
Power = Low, Opamp Bias = High
–
Power = Medium
–
Power = Medium, Opamp Bias = High
–
Power = High
–
Power = High, Opamp Bias = High
–
–
3.9
µs
Power = Low
–
Power = Low, Opamp Bias = High
–
Power = Medium
–
Power = Medium, Opamp Bias = High
–
Power = High
–
Power = High, Opamp Bias = High
–
0.72
–
0.62
µs
–
5.9
µs
µs
µs
0.92
–
0.72
µs
µs
µs
V/µs
–
V/µs
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
V/µs
Power = Medium, Opamp Bias = High
1.7
–
6.5
–
V/µs
V/µs
Power = High
Power = High, Opamp Bias = High
V/µs
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
0.01
Power = Low
V/µs
–
V/µs
Power = Low, Opamp Bias = High
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
V/µs
Power = Medium
Power = Medium, Opamp Bias = High
V/µs
0.5
–
4.0
–
V/µs
0.75
–
MHz
V/µs
Power = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low
Power = Low, Opamp Bias = High
MHz
Power = Medium
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
MHz
Power = Medium, Opamp Bias = High
3.1
–
Power = High, Opamp Bias = High
5.4
–
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
70
MHz
Power = High
June 1, 2004
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
µs
–
Power = Medium
ENOA
µs
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
0.15
Notes
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
µs
–
Power = Low, Opamp Bias = High
BWOA
µs
Falling Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
Power = Low
SRFOA
Units
Rising Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
MHz
MHz
–
Document No. 38-12019 Rev. *B
nV/rt-Hz
28
CY8C27x66 Preliminary Data Sheet
3. Electrical Specifications
Table 3-19: 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
Description
Min
Typ
Max
–
3.92
–
Power = Low, Opamp Bias = High
–
Power = Medium
–
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = High (3.3 Volt High Bias Operation not supported)
–
–
–
µs
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
µs
µs
Falling Settling Time to 0.1% of a 1V Step (10 pF load,
Unity Gain)
–
5.41
–
Power = Low, Opamp Bias = High
–
Power = Medium
–
Power = Medium, Opamp Bias = High
–
–
0.72
µs
Power = High (3.3 Volt High Bias Operation not supported)
–
–
–
µs
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
µs
µs
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
V/µs
–
V/µs
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
V/µs
V/µs
Power = Medium, Opamp Bias = High
2.7
–
Power = High (3.3 Volt High Bias Operation not supported)
–
–
–
V/µs
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
V/µs
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load,
Unity Gain)
Power = Low
0.24
V/µs
–
V/µs
Power = Low, Opamp Bias = High
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
V/µs
Power = Medium
V/µs
Power = Medium, Opamp Bias = High
1.8
–
Power = High (3.3 Volt High Bias Operation not supported)
–
–
–
V/µs
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
V/µs
0.67
–
Gain Bandwidth Product
Power = Low
MHz
MHz
Power = Low, Opamp Bias = High
Specification minimums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
MHz
Power = Medium
MHz
Power = Medium, Opamp Bias = High
2.8
–
Power = High (3.3 Volt High Bias Operation not supported)
–
–
–
MHz
Power = High, Opamp Bias = High (3.3 Volt High Power,
High Opamp Bias not supported)
–
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
70
–
nV/rt-Hz
June 1, 2004
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
µs
Power = Medium
ENOA
µs
Power = Low
0.31
Notes
Specification maximums for low power and
high opamp bias, medium power, and
medium power and high opamp bias levels
are between low and high power levels.
µs
Power = Low, Opamp Bias = High
BWOA
µs
Power = Low
Power = Low
SRFOA
Units
Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity
Gain)
Document No. 38-12019 Rev. *B
29
CY8C27x66 Preliminary Data Sheet
3.4.4
3. Electrical Specifications
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-20: AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
Timer
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
a
–
–
ns
Counter
Dead Band
49.2
Maximum Block Clocking Frequency (< 4.75V)
Notes
4.75V < Vdd < 5.25V.
24.6
3.0V < Vdd < 4.75V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Disable Mode
50
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
16.4
MHz
Receiver
Maximum Input Clock Frequency
–
16
49.2
MHz
4.75V < Vdd < 5.25V.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
June 1, 2004
Document No. 38-12019 Rev. *B
30
CY8C27x66 Preliminary Data Sheet
3.4.5
3. Electrical Specifications
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-21: 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4
µs
Power = High
–
–
4
µs
Power = Low
–
–
3.4
µs
Power = High
–
–
3.4
µs
Power = Low
0.5
–
–
V/µs
Power = High
0.5
–
–
V/µs
Power = Low
0.55
–
–
V/µs
Power = High
0.55
–
–
V/µs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 3-22: 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4.7
µs
Power = High
–
–
4.7
µs
Power = Low
–
–
4
µs
Power = High
–
–
4
µs
Power = Low
.36
–
–
V/µs
Power = High
.36
–
–
V/µs
Power = Low
.4
–
–
V/µs
Power = High
.4
–
–
V/µs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
June 1, 2004
Document No. 38-12019 Rev. *B
31
CY8C27x66 Preliminary Data Sheet
3.4.6
3. Electrical Specifications
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-23: 5V AC External Clock Specifications
Symbol
FOSCEXT
Description
Min
Frequency
Typ
Max
Units
0
–
24.24
MHz
ns
–
High Period
20.6
–
–
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
Notes
Table 3-24: 3.3V AC External Clock Specifications
Symbol
FOSCEXT
FOSCEXT
–
Description
Min
Typ
Max
Units
Frequency with CPU Clock divide by 1
0
–
12.12
MHz
Frequency with CPU Clock divide by 2 or greaterb
0
–
24.24
MHz
High Period with CPU Clock divide by 1
41.7
–
–
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
a
Notes
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-25: AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
15
–
ms
TWRITE
Flash Block Write Time
–
30
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
June 1, 2004
Document No. 38-12019 Rev. *B
Notes
32
CY8C27x66 Preliminary Data Sheet
3.4.8
3. Electrical Specifications
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-26: AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
µs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
µs
THDDATI2C
Data Hold Time
0
–
0
–
µs
TSUDATI2C
Data Set-up Time
250
–
100
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
µs
TBUFI2C
Bus Free Time Between a STOP and START Condition 4.7
–
1.3
–
µs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
0
50
ns
–
a
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus
June 1, 2004
Document No. 38-12019 Rev. *B
33
4. Packaging Information
4.1
Packaging Dimensions
This chapter illustrates the packaging specifications for the CY8C27x66 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
51-85014 - *C
Figure 4-1. 28-Lead (300-Mil) Molded DIP
51-85079 - *C
Figure 4-2. 28-Lead (210-Mil) SSOP
May 2004
Document No. 38-12019 Rev. *B
34
CY8C27x66 Preliminary Data Sheet
4. Packaging Information
51-85026 - *C
Figure 4-3. 28-Lead (300-Mil) SOIC
51-85064 - *B
Figure 4-4. 44-Lead TQFP
June 1, 2004
Document No. 38-12019 Rev. *B
35
CY8C27x66 Preliminary Data Sheet
4. Packaging Information
51-85061 - *C
51-85061-C
Figure 4-5. 48-Lead (300-Mil) SSOP
51-85152 - *A
Figure 4-6. 48-Lead (7x7 mm) MLF
June 1, 2004
Document No. 38-12019 Rev. *B
36
CY8C27x66 Preliminary Data Sheet
4.2
4. Packaging Information
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical θJA *
28 PDIP
69 oC/W
28 SSOP
96 oC/W
28SOIC
TBD
44 TQFP
60 oC/W
48 SSOP
69 oC/W
48 MLF
28 oC/W
* TJ = TA + POWER x θJA
4.3
Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 PDIP
3.5 pF
28 SSOP
2.8 pF
28 SOIC
TBD
44 TQFP
2.6 pF
48 SSOP
3.3 pF
48 MLF
1.8 pF
June 1, 2004
Document No. 38-12019 Rev. *B
37
5. Ordering Information
The following table lists the CY8C27x66 PSoC Device family’s key package features and ordering codes.
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
-40oC to +85oC
(Columns of 3)
Yes
Analog PSoC
Blocks
1K
(Rows of 4)
Temperature
Range
32
Digital PSoC
Blocks
Switch Mode
Pump
CY8C27466-24PXI
RAM
(Bytes)
28 Pin (300 Mil) DIP
Flash
(Kbytes)
Package
Ordering
Code
Table 5-1. CY8C27x66 PSoC Device Family Key Features and Ordering Information
8
12
24
12
4
Yes
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP
CY8C27466-24PVXI
32
1K
Yes
-40oC to +85oC
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27466-24PVXIT
32
1K
Yes
-40oC to +85oC
8
12
24
12
4
Yes
28 Pin (300 Mil) SOIC
CY8C27466-24SXI
32
1K
Yes
-40oC to +85oC
8
12
24
12
4
Yes
8
12
24
12
4
Yes
28 Pin (300 Mil) SOIC
(Tape and Reel)
CY8C27466-24SXIT
32
1K
Yes
-40oC to +85oC
44 Pin TQFP
CY8C27566-24AXI
32
1K
Yes
-40oC to +85oC
8
12
40
12
4
Yes
44 Pin TQFP
(Tape and Reel)
CY8C27566-24AXIT
32
1K
Yes
-40oC to +85oC
8
12
40
12
4
Yes
48 Pin (300 Mil) SSOP
CY8C27666-24PVXI
32
1K
Yes
-40oC to +85oC
8
12
44
12
4
Yes
48 Pin (300 Mil) SSOP
(Tape and Reel)
CY8C27666-24PVXIT
32
1K
Yes
-40oC to +85oC
8
12
44
12
4
Yes
48 Pin MLF
CY8C27666-24LFXI
32
1K
Yes
-40oC to +85oC
8
12
44
12
4
Yes
5.1
Ordering Code Definitions
CY 8 C 27 xxx-SPxx
Package Type:
PX = PDIP Pb Free
SX = SOIC Pb Free
PVX = SSOP Pb Free
LFX = MLF Pb Free
AX = TQFP Pb Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
June 1, 2004
Document No. 38-12019 Rev. *B
38
6. Sales and Service Information
To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone:
Facsimile:
800.669.0557
425.787.4641
Web Sites:
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
6.1
Revision History
Table 6-1. CY8C27x66 Data Sheet Revision History
Document Title:
CY8C27466, CY8C27566, and CY8C27666 PSoC Mixed Signal Array Preliminary Data Sheet
Document Number:
Revision
38-12019
ECN #
Issue Date
Origin of Change
Description of Change
**
133204
02/09/2004
SFV
New silicon and document (Revision **).
*A
209441
03/15/2004
SFV
Changed block diagram on first page to match feature set description.
*B
227242
06/01/2004
SFV
Changes to Overview section, deleted 100-pin TQFP, added 28-pin SOIC, and significant changes to the Electrical Specifications section. Title changed to reflect removal of
CY8C27x866, along with removal or registers x,18h - x,1Fh (in bank 0 and bank 1) from
Register Reference chapter.
Distribution: External/Public
6.2
Posting: None
Copyrights
© Cypress MicroSystems, Inc. 2004. All rights reserved. PSoC™ (Programmable System-on-Chip™) are trademarks of Cypress MicroSystems, Inc. All other trademarks
or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress MicroSystems.
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12019 Rev. *B
39