CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip™ Features ■ Powerful Harvard-architecture processor ❐ M8C processor speeds to 24 MHz ❐ 8x8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ 3.0 V to 5.25 V operating voltage ❐ Industrial temperature range: –40 °C to +85 °C ■ Advanced peripherals (PSoC blocks) ❐ Four Rail-to-Rail analog PSoC blocks provide: • Up to 14-bit ADCs • Up to 8-bit DACs • Programmable gain amplifiers • Programmable filters and comparators ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers and counters, 8- and 16-bit pulse-width modulators (PWMs) • CRC and PRS modules • Full-duplex UART • Multiple SPI masters or slaves • Connectable to all GPIO Pins ❐ Complex peripherals by combining blocks ❐ High-Speed 8-Bit SAR ADC optimized for motor control ■ ■ ■ ■ ■ Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full-featured in-circuit emulator and programmer ❐ Full speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Logic Block Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes SROM Global Analog Interconnect Flash 8K CPUCore (M8C) Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Precision, programmable clocking ❐ Internal ±2.5% 24/48 MHz oscillator ❐ High accuracy 24 MHz with optional 32 KHz crystal and PLL ❐ Optional external oscillator, up to 24 MHz ❐ Internal oscillator for watchdog and sleep DIGITAL SYSTEM Digital Block Array Flexible on-chip memory ❐ 8K bytes flash program storage 50,000 erase/write cycles ❐ 256 bytes SRAM data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash Digital Clocks Multiply Accum. Analog Ref Analog Block Array 2 Columns 4 Blocks 1 Row 4 Blocks Programmable pin configurations ❐ 25 mA Sink, 10 mA source on all GPIO ❐ Pull-up, pull-down, high Z, strong, or open drain drive modes on all GPIO ❐ Up to eight analog inputs on GPIO plus two additional analog inputs with restricted routing ❐ Two 30 mA analog outputs on GPIO ❐ Configurable interrupt on all GPIO ANALOG SYSTEM Analog Input Muxing SAR8 ADC Decimator I2C POR and LVD System Resets Internal Voltage Ref. SYSTEM RESOURCES Additional system resources 2 ❐ I C slave, master, and multi-master to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low voltage detection ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference Cypress Semiconductor Corporation Document Number: 001-44369 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 8, 2013 CY8C23433, CY8C23533 Contents PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ................................................................... 3 Analog System .................................................................. 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 7 PSoC Designer Software Subsystems ........................ 7 Designing with PSoC Designer ....................................... 8 Select User Modules ................................................... 8 Configure User Modules .............................................. 8 Organize and Connect ................................................ 8 Generate, Verify, and Debug ....................................... 8 Pinouts .............................................................................. 9 32-Pin Part Pinout ....................................................... 9 28-Pin Part Pinout .................................................... 10 Register Reference ......................................................... 11 Register Conventions ................................................ 11 Register Mapping Tables .......................................... 11 Document Number: 001-44369 Rev. *G Electrical Specifications ................................................ 14 Absolute Maximum Ratings ....................................... 15 Operating Temperature ............................................ 15 DC Electrical Characteristics ..................................... 16 AC Electrical Characteristics ..................................... 31 Packaging Information ................................................... 41 Thermal Impedances ................................................ 42 Capacitance on Crystal Pins .................................... 42 Solder Reflow Peak Temperature ............................. 42 Ordering Information ...................................................... 43 Acronyms ........................................................................ 44 Acronyms Used ......................................................... 44 Reference Documents .................................................... 44 Document Conventions ................................................. 45 Units of Measure ....................................................... 45 Numeric Conventions .................................................... 45 Glossary .......................................................................... 46 Silicon Errata for the CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip ....................... 51 Part Numbers Affected .............................................. 51 CY8C23433 Qualification Status ............................... 51 CY8C23433 Errata Summary .................................... 51 Document History Page ................................................. 52 Sales, Solutions, and Legal Information ...................... 53 Worldwide Sales and Design Support ....................... 53 Products .................................................................... 53 PSoC Solutions ......................................................... 53 Page 2 of 53 CY8C23433, CY8C23533 PSoC Functional Overview Digital System The PSoC family consists of many programmable system-on-chips with on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture make it possible for you to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast central processing unit (CPU), flash memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The Digital system consists of 4 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 3 Port 2 To System Bus Digital Clocks FromCore The PSoC architecture, as shown in the Logic Block Diagram on page 1, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows combining all of the device resources into a complete custom system. The PSoC CY8C23x33 family can have up to three I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and four analog blocks. Port 1 Port 0 ToAnalog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 Row Input Configuration 8 DBB00 DBB01 DCB02 4 DCB03 4 8 Row Output Configuration 8 8 PSoC Core The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general Purpose I/O (GPIO) The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four million instructions per second MIPS 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (WDT). Memory encompasses 8 KB of flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the flash. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to ±2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Document Number: 001-44369 Rev. *G GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations are: ■ PWMs (8-and 16-bit) ■ PWMs with Dead band (8- and 16-bit) ■ Counters (8- to 32- bit) ■ Timers (8- to 32- bit) ■ UART 8 bit with selectable parity (up to 1) ■ Serial peripheral interface (SPI) master and slave (up to 1) ■ I2C slave and multi master (1 available as a system resource) ■ Cyclical redundancy checker (CRC)/Generator (8 to 32 bit) ■ IrDA (up to 1) ■ Pseudo Random Sequence Generators (8- to 32- bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Characteristics on page 5. Page 3 of 53 CY8C23433, CY8C23533 The analog system consists of an 8-bit SAR ADC and four configurable blocks. The programmable 8-bit SAR ADC is an optimized ADC that runs up to 300 Ksps, with monotonic guarantee. It also has the features to support a motor control application. Each analog block consists of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ Filters (2 band pass, low-pass) ■ Amplifiers (up to 2, with selectable gain to 48x) ■ Instrumentation amplifiers (1 with selectable gain to 93x) ■ Comparators (1, with 16 selectable thresholds) ■ DAC (6 or 9-bit DAC) ■ Multiplying DAC (6 or 9-bit DAC) ■ High current output drivers (two with 30 mA drive) ■ 1.3-V reference (as a system resource) ■ DTMF dialer Figure 2. Analog System Block Diagram P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn Analog System P2[3] P2[6] P2[4] P2[1] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ■ Modulators ■ Correlators ■ Peak detectors ■ Many other topologies possible ACB01 ASD11 ASC21 P0[7:0] Analog blocks are arranged in a column of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks. The Analog column 0 contains the SAR8 ADC block rather than the standard SC blocks. ACI2[3:0] 8-Bit SAR ADC Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Notes 1. One complete column, plus one Continuous Time Block. 2. Limited analog functionality. 3. Two analog blocks and one CapSense. Document Number: 001-44369 Rev. *G Page 4 of 53 CY8C23433, CY8C23533 Additional System Resources ■ The decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma ADCs. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. Low-Voltage detection interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power-on-reset. Brief statements describing the merits of each system resource follow: ■ ■ PSoC Device Characteristics Depending on the PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. Table 1 lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics PSoC Part Number Digital I/O CY8C29x66 up to 64 CY8C28xxx up to 44 Digital Rows Digital Blocks Analog Inputs Analog Outputs 4 16 up to 12 4 up to 3 up to 12 up to 44 up to 4 Analog Columns Analog Blocks SRAM Size Flash Size SAR ADC 4 12 2K 32 K No up to 6 up to 12 + 4[1] 1K 16 K Yes CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K No CY8C24x94 up to 56 1 4 up to 48 2 2 6 1K 16 K No CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4K No CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K Yes CY8C24x33 up to 26 1 4 up to 12 2 2 4 256 8K Yes [1] CY8C22x45 up to 38 2 8 up to 38 0 4 6 1K 16 K No CY8C21x45 up to 24 1 4 up to 24 0 4 6[1] 512 8K Yes CY8C21x34 up to 28 1 4 up to 28 0 2 4[1] 512 8K No CY8C21x23 up to 16 1 4 up to 8 0 2 4[1] 256 4K No CY8C20x34 up to 28 0 0 up to 28 0 0 3[1,2] 512 8K No 0 3[1,2] up to 2K up to 32 K No CY8C20xx6 up to 36 0 0 up to 36 0 Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense®. Document Number: 001-44369 Rev. *G Page 5 of 53 CY8C23433, CY8C23533 Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer integrated development environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online at http:// www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. For in-depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. CYPros Consultants For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at http://www.cypress.com. Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to http://www.cypress.com and look for CYPros. Application Notes Solutions Library Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs and can be found at http://www.cypress.com Visit our growing library of solution-focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from cypress at http://www.cypress.com and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Document Number: 001-44369 Rev. *G Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Page 6 of 53 CY8C23433, CY8C23533 Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation ■ Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-44369 Rev. *G Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, and read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality ICE is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Page 7 of 53 CY8C23433, CY8C23533 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-44369 Rev. *G Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 8 of 53 CY8C23433, CY8C23533 Pinouts The CY8C23X33 PSoC is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and Vdd in the following table and figure, is capable of Digital I/O. 32-Pin Part Pinout Table 2. Pin Definitions - 32-Pin (QFN) Pin Digital Analog Name 1 I/O 2 I/O 3 I/O I 4 I/O I 5 I/O AVref P2[7] GPIO P2[5] GPIO P2[3] Direct switched capacitor block input P2[1] Direct switched capacitor block input P3[0][4] GPIO/ADC Vref (optional) No connection GPIO, P2[7] GPIO, P2[5] A, I, P2[3] A, I, P2[1] AVref, P3[0] NC I2C SCL, P1[7] I2C SDA, P1[5] 1 2 3 4 5 6 7 8 QFN (Top View) 24 23 22 21 20 19 18 17 7 I/O P1[7] I2C serial clock (SCL) 8 I/O P1[5] I2C serial data (SDA) 9 10 11 12 13 14 15 16 NC Figure 3. CY8C23533 32-Pin PSoC Device No connection NC GPIO P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] GPIO P1[2] GPIO, EXTCLK, P1[4] NC 6 Description P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I Vdd P0[6], A, I P0[4], A, I NC Type 32 31 30 29 28 27 26 25 Pin No. 9 NC 10 I/O P1[3] GPIO 11 I/O P1[1] GPIO, crystal Input (XTAL in), I2C serial clock (SCL), ISSP-SCLK* 12 Power Vss Ground connection 13 I/O P1[0] GPIO, crystal output (XTAL out), I2C serial data (SDA), ISSP-SDATA* 14 I/O P1[2] GPIO 15 I/O P1[4] GPIO, external clock IP I/O P1[6] 16 17 NC 18 Input P2[6], Vref P2[4], AGnd P2[2], A, I P2[0], A, I XRES P1[6], GPIO No connection GPIO XRES Active high external reset with internal pull down 19 I/O I 20 I/O I 21 I/O 22 I/O 23 I/O I 24 I/O I 25 P2[0] Direct switched capacitor block input P2[2] Direct switched capacitor block input P2[4] External analog ground (AGnd) P2[6] External voltage reference (VRef) P0[0] Analog column mux input and ADC input P0[2] Analog column mux input and ADC input NC No connection 26 I/O I P0[4] Analog column mux input and ADC input 27 I/O I P0[6] Analog column mux input and ADC input 28 P0[2], A, I P0[0], A, I VDD Supply voltage 29 I/O Power I P0[7] Analog column mux input and ADC input 30 I/O I/O P0[5] Analog column mux input, column output and ADC input 31 I/O I/O P0[3] Analog column mux input, column output and ADC input 32 I/O I P0[1] Analog column mux input.and ADC input LEGEND: A = Analog, I = Input, and O = Output. Note 4. Even though P3[0] is an odd port, it resides on the left side of the pinout. Document Number: 001-44369 Rev. *G Page 9 of 53 CY8C23433, CY8C23533 28-Pin Part Pinout Table 3. Pin Definitions - 28-Pin (SSOP) Figure 4. Type Pin No. Digital 1 I/O I P0[7] Analog column mux IP and ADC IP 2 I/O I/O P0[5] Analog column mux IP and column O/P and ADC IP 3 4 I/O I/O Analog I/O I Pin Name P0[3] P0[1] Description Analog column mux IP and column O/P and ADC IP Analog column mux IP and ADC IP Figure 5. CY8C23433 28-Pin PSoC Device AIO, P0[7] 1 28 Vdd IO, P0[5] 2 27 P0[6], AIO, AnColMux and ADC IP IO, P0[3] 3 26 P0[4], AIO, AnColMux and ADC IP AIO, P0[1] 4 25 P0[2], AIO, AnColMux and ADC IP IO, P2[7] 5 24 P0[0], AIO, AnColMux and ADC IP IO, P2[5] 6 23 P2[6], VREF AIO, P2[3] 7 22 P2[4], AGND AIO, P2[1] 8 21 P2[2], AIO SSOP 5 I/O P2[7] GPIO AVref, IO, P3[0] 9 20 P2[0], AIO 6 I/O P2[5] GPIO I2C SCL, IO, P1[7] 10 19 P3[1], IO 7 I/O I P2[3] Direct switched capacitor input I2C SDA, IO, P1[5] 11 18 P1[6], IO IO, P1[3] 12 17 P1[4], IO, EXTCLK 8 I/O I P2[1] Direct switched capacitor input I2C SCL,ISSP SCL,XTALin,IO, P1[1] 13 16 P1[2], IO 9 I/O AVref P3[0][5] GPIO/ADC Vref (optional) Vss 14 15 P1[0],IO,XTALout,ISSP SDA,I2C SDA 10 I/O P1[7] I2C SCL 11 I/O P1[5] I2C SDA 12 I/O P1[3] 13 I/O P1[1] 14 Power Vss 15 I/O P1[0] 16 I/O P1[2] 17 I/O P1[4] GPIO, External clock IP 18 I/O P1[6] GPIO 19 I/O P3[1][7] GPIO 20 I/O I P2[0] Direct switched capacitor input 21 I/O I 22 I/O 23 I/O 24 I/O I 25 I/O 26 I/O 27 I/O 28 Power GPIO [6] GPIO, Xtal input, I2C SCL, ISSP SCL Ground Pin [6] GPIO, Xtal output, I2C SDA, ISSP SDA GPIO P2[2] Direct switched capacitor input P2[4] External analog ground (AGnd) P2[6] Analog voltage reference (VRef) P0[0] Analog column mux IP and ADC IP I P0[2] Analog column mux IP and ADC IP I P0[4] Analog column mux IP and ADC IP I P0[6] Analog column mux IP and ADC IP Vdd Supply Voltage LEGEND: A = Analog, I = Input, and O = Output. Notes 5. Even though P3[0] is an odd port, it resides on the left side of the pinout. 6. ISSP pin, which is not High Z at POR. 7. Even though P3[1] is an even port, it resides on the right side of the pinout. Document Number: 001-44369 Rev. *G Page 10 of 53 CY8C23433, CY8C23533 Register Reference Register Mapping Tables This section lists the registers of the CY8C23433 PSoC device by using mapping tables, in offset order. Register Conventions The register conventions specific to this section are listed in Table 4. The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks Bank 0 and Bank 1. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set to 1 the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed. Table 4. Register Conventions Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-44369 Rev. *G Page 11 of 53 CY8C23433, CY8C23533 Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Gray fields are reserved. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # W RW # # W RW # # W RW # # W RW # Name AMX_IN ARF_CR CMP_CR0 ASY_CR CMP_CR1 SARADC_DL SARADC_CR0 SARADC_CR1 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 * ACB01CR2 * Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RW RW # # RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access Name RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (0,Hex) Access C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 RW D7 # D8 RW D9 # DA RW DB RW DC DD RW DE RW DF E0 RW E1 RW E2 RC E3 W E4 RC E5 RC E6 RW E7 RW E8 W E9 W EA R EB R EC RW ED RW EE RW EF RW F0 F1 F2 F3 F4 F5 F6 F7 RL F8 F9 FA FB FC FD FE # FF # # Access is bit specific. Document Number: 001-44369 Rev. *G Page 12 of 53 CY8C23433, CY8C23533 Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Gray fields are reserved. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 AMD_CR1 ALT_CR0 RW RW RW RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 * Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SARADC_TRS SARADC_TRCL SARADC_TRCH SARADC_CR2 SARADC_LCR RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Addr (1,Hex) Access Name Addr (1,Hex) Access 80 C0 81 C1 82 C2 83 C3 84 RW C4 85 RW C5 86 RW C6 87 RW C7 88 C8 89 C9 8A CA 8B CB 8C CC 8D CD 8E CE 8F CF 90 GDI_O_IN D0 RW 91 GDI_E_IN D1 RW 92 GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 RW D4 95 RW D5 96 RW D6 97 RW D7 98 D8 99 D9 9A DA 9B DB 9C DC 9D OSC_GO_EN DD RW 9E OSC_CR4 DE RW 9F OSC_CR3 DF RW A0 OSC_CR0 E0 RW A1 OSC_CR1 E1 RW A2 OSC_CR2 E2 RW A3 VLT_CR E3 RW A4 VLT_CMP E4 R A5 E5 A6 E6 A7 E7 A8 RW IMO_TR E8 W A9 RW ILO_TR E9 W AA RW BDG_TR EA RW AB # ECO_TR EB W AC RW EC AD ED AE EE AF EF B0 RW F0 B1 RW F1 B2 RW F2 B3 RW F3 B4 RW F4 B5 RW F5 B6 RW F6 B7 CPU_F F7 RL B8 F8 B9 F9 BA FLS_PR1 FA RW BB FB BC FC BD FD BE CPU_SCR1 FE # BF CPU_SCR0 FF # # Access is bit specific. Document Number: 001-44369 Rev. *G Page 13 of 53 CY8C23433, CY8C23533 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C23433 PSoC device. For up-to-date latest electrical specifications, visit http://www.cypress.com. Specifications are valid for –40°C TA 85°C and TJ 100°C, except where noted. Refer to Table 23 on page 31 for the electrical specifications for the IMO using SLIMO mode. Figure 6. Voltage versus CPU Frequency 5.25 SLIMO Mode = 0 Figure 8. IMO Frequency Trim Options 5.25 4.75 Vdd Voltage Vdd Voltage lid g Va ratin n pe io O Reg 4.75 SLIMO Mode=1 SLIMO Mode=0 SLIMO Mode=1 SLIMO Mode=0 3.60 3.00 3.00 93 kHz 3 MHz CPU Frequency Document Number: 001-44369 Rev. *G 12 MHz 24 MHz 93 kHz 6 MHz 12 MHz 24 MHz IMO Frequency Page 14 of 53 CY8C23433, CY8C23533 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol TSTG Description Storage temperature TBAKETEMP Bake temperature TBAKETIME Bake time Min Typ Max Units Notes –55 25 +100 °C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrade reliability. – 125 See package label See package label – 72 Hour s –40 – +85 °C o C TA Ambient temperature with power applied Vdd Supply voltage on VDD relative to VSS –0.5 – +6.0 V VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any port pin –25 – +50 mA ESD Electrostatic discharge voltage 2000 – – V LU Latch up current – – 200 mA Human Body Model ESD. Operating Temperature Table 8. Operating Temperature Min Typ Max Units TA Symbol Ambient temperature Description –40 – +85 °C TJ Junction temperature –40 – +100 °C Document Number: 001-44369 Rev. *G Notes The temperature rise from ambient to junction is package specific. See Table 37 on page 42. You must limit the power consumption to comply with this requirement. Page 15 of 53 CY8C23433, CY8C23533 DC Electrical Characteristics DC Chip-Level Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 9. DC Chip-Level Specifications Symbol Description VDD Supply voltage IDD Supply current Min 3.0 – Typ – 5 Max 5.25 8 IDD3 Supply current – 3.3 6.0 ISB Sleep (mode) current with POR, LVD, Sleep Timer, and WDT.[8] – 3 6.5 ISBH Sleep (mode) current with POR, LVD, sleep timer, and WDT at high temperature.[8] – 4 25 ISBXTL Sleep (mode) current with POR, LVD, sleep timer, WDT, and external crystal.[8] – 4 7.5 ISBXTLH Sleep (mode) current with POR, LVD, sleep timer, WDT, and external crystal at high temperature.[8] – 5 26 VREF Reference voltage (Bandgap) 1.28 1.30 1.32 Units Notes V See Table 19 on page 28. mA Conditions are VDD = 5.0V, TA = 25°C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. mA Conditions are VDD = 3.3V, TA = 25°C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. A Conditions are with internal slow speed oscillator, VDD = 3.3V, –40°C TA 55°C, analog power = off. A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55°C < TA 85°C, analog power = off. A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3V, –40°C TA 55°C, analog power = off. A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. VDD = 3.3 V, 55°C < TA 85°C, analog power = off. V Trimmed for appropriate VDD. VDD > 3.0V Note 8. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 001-44369 Rev. *G Page 16 of 53 CY8C23433, CY8C23533 DC General-Purpose I/O Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3V at 25°C and are for design guidance only. Table 10. 5-V and 3.3-V DC GPIO Specifications Symbol Description Min Typ Max Units Notes RPU Pull-up resistor 4 5.6 8 k RPD Pull-down resistor 4 5.6 8 k VOH High output level VDD - 1.0 – – V IOH = 10 mA, VDD = 4.75 to 5.25 V (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. VOL Low output level – – 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 100 mA maximum combined IOH budget. IOH High level source current 10 – – mA VOH = VDD-1.0 V, see the limitations of the total current in the note for VOH IOL Low level sink current 25 – – mA VOL = 0.75 V, see the limitations of the total current in the note for VOL VIL Input low level – – 0.8 V VDD = 3.0 to 5.25 VIH Input high level 2.1 – V VDD = 3.0 to 5.25 VH Input hysterisis – 60 – mV IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 A CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent. Temp = 25°C COUT Capacitive load on pins as output – 3.5 10 pF Package and pin dependent. Temp = 25°C Document Number: 001-44369 Rev. *G Page 17 of 53 CY8C23433, CY8C23533 DC Operational Amplifier Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. The Operational amplifier is a component of both the analog continuous time PSoC blocks and the analog switched cap PSoC blocks. The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters apply to 5 V at 25°C and are for design guidance only. Table 11. 5-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high TCVOSOA Average input offset voltage drift Min Typ Max Units – – – 1.6 1.3 1.2 10 8 7.5 mV mV mV – 7.0 35.0 V/°C Notes IEBOA Input leakage current (Port 0 analog pins) – 20 – pA Gross tested to 1 A CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25°C VCMOA Common mode voltage range Common mode voltage range (high power or high opamp bias) 0.0 0.5 – – VDD VDD – 0.5 V V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. GOLOA Open loop gain Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high 60 60 80 – – – – – – dB – – VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high VDD – 0.2 VDD – 0.2 VDD – 0.5 – – – – – – V V V VOLOWOA Low output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high – – – – – – 0.2 0.2 0.5 V V V – – – – – 300 600 1200 2400 4600 400 800 1600 3200 6400 A A A A A 52 80 – dB ISOA Supply current (including associated AGND buffer) Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high PSRROA Supply voltage rejection ratio Document Number: 001-44369 Rev. *G Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Vss VIN (VDD - 2.25) or (VDD - 1.25V) VIN VDD Page 18 of 53 CY8C23433, CY8C23533 Table 12. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Min Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high TCVOSOA Average input offset voltage drift Typ Max Units – – – 1.65 1.32 – 10 8 – mV mV mV – 7.0 35.0 µV/°C Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. IEBOA Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 A CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25 °C VCMOA Common mode voltage range 0.2 – VDD – 0.2 V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. GOLOA Open loop gain Power = low, ppamp Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low 60 60 80 – – – – – – dB dB dB VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low VDD – 0.2 VDD – 0.2 VDD – 0.2 – – – – – – V V V VOLOWOA Low output voltage swing (internal signals) Power = low, ppamp Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low – – – – – – 0.2 0.2 0.2 V V V ISOA PSRROA Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high – – – – – – 150 300 600 1200 2400 – 200 400 800 1600 3200 – mA mA mA mA mA mA Supply voltage rejection ratio 64 80 – dB Specification is applicable at low Opamp bias. For high Opamp bias mode (except high power, high Opamp bias), minimum is 60 dB. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. VSS £ VIN £ (VDD – 2.25) or (VDD – 1.25 V) £ VIN £ VDD DC Low Power Comparator Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 13. DC Low Power Comparator Specifications Symbol Description Min Typ Max Units 0.2 – VDD – 1.0 V VREFLPC Low power comparator (LPC) reference voltage range ISLPC LPC supply current – 10 40 A VOSLPC LPC voltage offset – 2.5 30 mV Document Number: 001-44369 Rev. *G Page 19 of 53 CY8C23433, CY8C23533 DC Analog Output buffer specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 14. 5-V DC Analog Output Buffer Specifications Symbol CL Description Load capacitance Min Typ Max Units Notes – – 200 pF This specification applies to the external circuit that is being driven by the analog output buffer. 3 +6 – 12 – VDD – 1.0 mV V/°C V 1 1 – – W W – – – – V V – – 0.5 x VDD - 1.3 0.5 x VDD - 1.3 V V 1.1 2.6 64 5.1 8.8 – mA mA dB VOSOB TCVOSOB VCMOB ROUTOB Input offset voltage (absolute value) – Average input offset voltage drift – Common-mode input voltage range 0.5 Output resistance Power = low – Power = high – VOHIGHOB High output voltage swing (Load = 32 ohms to VDD/2) Power = low 0.5 x VDD + 1.1 Power = high 0.5 x VDD + 1.1 VOLOWOB Low output voltage swing (Load = 32 ohms to VDD/2) Power = low – Power = high – ISOB Supply current including bias cell (no load) Power = low – Power = high – PSRROB Supply voltage rejection ratio 52 VOUT >(VDD - 1.25) Table 15. 3.3-V DC Analog Output Buffer Specifications Min Typ Max Units Notes CL Symbol Load capacitance Description – – 200 pF This specification applies to the external circuit that is being driven by the analog output buffer. VOSOB Input offset voltage (absolute value) – 3 12 mV TCVOSOB Average input offset voltage drift VCMOB Common-mode input voltage range ROUTOB Output resistance Power = low Power = high – +6 – V/°C 0.5 – VDD – 1.0 V – – 1 1 – – W W – – – – V V – – 0.5 x VDD - 1.0 0.5 x VDD - 1.0 V V VOHIGHOB High output voltage swing (Load = 1k ohms to VDD/2) 0.5 x VDD + 1.0 Power = low 0.5 x VDD + 1.0 Power = high VOLOWOB Low output voltage swing (Load = 1k ohms to VDD/2) Power = low – Power = high – ISOB PSRROB Supply current including bias cell (no load) Power = low Power = high – 0.8 2.0 2.0 4.3 mA mA Supply voltage rejection ratio 52 64 – dB Document Number: 001-44369 Rev. *G VOUT > (VDD - 1.25) Page 20 of 53 CY8C23433, CY8C23533 DC Analog Reference Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the analog reference control register. The limits stated for AGND include the offset error of the AGND buffer local to the analog continuous time PSoC block. reference control power is high. Table 16. 5-V DC Analog Reference Specifications Reference ARF_CR [5:3] 0b000 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High VAGND AGND RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b001 RefPower = high Opamp bias = high RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Description Min Typ Max Units VDD/2 + Bandgap VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409 V VDD/2 VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132 VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154 V VREFLO Ref Low VDD/2 – Bandgap VREFHI Ref High VDD/2 + Bandgap VAGND AGND V V VDD/2 VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358 VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055 V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218 V VREFHI Ref High VDD/2 + Bandgap V VAGND AGND VDD/2 VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357 VDD/2 – 0.055 VDD/2 VDD/2 + 0.052 VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353 VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033 V VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225 P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + – 0.076 0.021 0.041 V V VAGND AGND VREFLO Ref Low VDD/2 – Bandgap VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VAGND AGND VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + – 0.025 0.011 0.085 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + – 0.069 0.014 0.043 V VAGND AGND VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + – 0.029 0.005 0.052 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + – 0.072 0.011 0.048 V VDD/2 P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] V V – – VAGND AGND VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + – 0.031 0.002 0.057 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] + – 0.070 0.009 0.047 V VAGND AGND VREFLO Ref Low Document Number: 001-44369 Rev. *G P2[4] P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] + – 0.033 0.001 0.039 – – V Page 21 of 53 CY8C23433, CY8C23533 Table 16. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b010 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High VAGND AGND RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b011 RefPower = high Opamp bias = high RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Description VDD VDD/2 Min Typ Max Units VDD – 0.121 VDD – 0.003 VDD V VDD/2 – 0.040 VDD/2 VDD/2 + 0.034 V VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.019 V VREFHI Ref High VDD VDD – 0.083 VDD – 0.002 VDD V VAGND AGND VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033 V VDD/2 VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.016 V VREFHI Ref High VDD VDD – 0.075 VDD – 0.002 VDD V VAGND AGND VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032 V VDD/2 VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.015 V VREFHI Ref High VDD VDD – 0.074 VDD – 0.002 VDD V VAGND AGND VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032 V VDD/2 VREFLO Ref Low VSS VREFHI Ref High 3 × Bandgap VSS VSS + 0.002 VSS + 0.014 V 3.753 3.874 3.979 V VAGND AGND 2 × Bandgap 2.511 2.590 2.657 V VREFLO Ref Low Bandgap 1.243 1.297 1.333 V VREFHI Ref High 3 × Bandgap 3.767 3.881 3.974 V VAGND AGND 2 × Bandgap 2.518 2.592 2.652 V VREFLO Ref Low Bandgap 1.241 1.295 1.330 V VREFHI Ref High 3 × Bandgap 2.771 3.885 3.979 V VAGND AGND 2 × Bandgap 2.521 2.593 2.649 V VREFLO Ref Low Bandgap 1.240 1.295 1.331 V VREFHI Ref High 3 × Bandgap 3.771 3.887 3.977 V VAGND AGND 2 × Bandgap 2.522 2.594 2.648 V VREFLO Ref Low Bandgap 1.239 1.295 1.332 V Document Number: 001-44369 Rev. *G Page 22 of 53 CY8C23433, CY8C23533 Table 16. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b100 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High VAGND AGND VREFLO Ref Low 2 × Bandgap – P2[6] 2.515 – P2[6] 2.602 – P2[6] 2.654 – P2[6] (P2[6] = 1.3 V) V VREFHI Ref High 2 × Bandgap + P2[6] 2.498 + P2[6] 2.579 + P2[6] 2.642 + P2[6] (P2[6] = 1.3 V) V RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b101 RefPower = high Opamp bias = high RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Description Min Typ Max Units 2 × Bandgap + P2[6] 2.481 + P2[6] 2.569 + P2[6] 2.639 + P2[6] (P2[6] = 1.3 V) V 2 × Bandgap V 2 × Bandgap 2.511 VAGND AGND Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.598 – P2[6] 2.650 – P2[6] (P2[6] = 1.3 V) V VREFHI Ref High 2 × Bandgap + P2[6] 2.504 + P2[6] 2.583 + P2[6] 2.646 + P2[6] (P2[6] = 1.3 V) V VAGND AGND 2 × Bandgap V VREFLO Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.596 – P2[6] 2.649 – P2[6] (P2[6] = 1.3 V) V VREFHI Ref High 2 × Bandgap + P2[6] 2.505 + P2[6] 2.586 + P2[6] 2.648 + P2[6] (P2[6] = 1.3 V) V 2.521 2.592 2.650 AGND Ref Low 2 × Bandgap – P2[6] 2.513 – P2[6] 2.595 – P2[6] 2.648 – P2[6] (P2[6] = 1.3 V) V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.228 P2[4] + 1.284 P2[4] + 1.332 V VAGND AGND VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.358 P2[4] – 1.293 P2[4] – 1.226 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.236 P2[4] + 1.289 P2[4] + 1.332 V AGND Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.357 P2[4] – 1.297 P2[4] – 1.229 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.237 P2[4] + 1.291 P2[4] + 1.337 V VAGND AGND VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.356 P2[4] – 1.299 P2[4] – 1.232 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.237 P2[4] + 1.292 P2[4] + 1.337 V VAGND AGND Ref Low Document Number: 001-44369 Rev. *G P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] – VAGND P2[4] P2[4] P2[4] V VREFLO VREFLO P2[4] P2[4] 2.648 V VAGND P2[4] 2.594 2.652 VREFLO P2[4] 2.521 2.592 2.658 VREFLO 2 × Bandgap 2.518 2.590 P2[4] P2[4] P2[4] – 1.357 P2[4] – 1.300 P2[4] – 1.233 – – – V Page 23 of 53 CY8C23433, CY8C23533 Table 16. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b110 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b111 RefPower = high Opamp bias = high RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Description Min Typ Max Units 2 × Bandgap 2.512 2.594 2.654 V Bandgap 1.250 1.303 1.346 V VSS VSS + 0.011 VSS + 0.027 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 2 × Bandgap 2.515 2.592 2.654 V VAGND AGND Bandgap 1.253 1.301 1.340 V VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.02 V VREFHI Ref High 2 × Bandgap 2.518 2.593 2.651 V Bandgap 1.254 1.301 1.338 V VSS VSS + 0.004 VSS + 0.017 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 2 × Bandgap 2.517 2.594 2.650 V VAGND AGND Bandgap 1.255 1.300 1.337 V VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.015 V VREFHI Ref High 3.2 × Bandgap 4.011 4.143 4.203 V 1.6 × Bandgap 2.020 2.075 2.118 V VSS VSS + 0.011 VSS + 0.026 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 3.2 × Bandgap 4.022 4.138 4.203 V VAGND AGND 1.6 × Bandgap 2.023 2.075 2.114 V VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.017 V VREFHI Ref High 3.2 × Bandgap 4.026 4.141 4.207 V 1.6 × Bandgap 2.024 2.075 2.114 V VSS VSS + 0.004 VSS + 0.015 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 3.2 × Bandgap 4.030 4.143 4.206 V VAGND AGND 1.6 × Bandgap 2.024 2.076 2.112 V VREFLO Ref Low VSS VSS + 0.003 VSS + 0.013 V Document Number: 001-44369 Rev. *G VSS Page 24 of 53 CY8C23433, CY8C23533 Table 17. 3.3-V DC Analog Reference Specifications Reference ARF_CR [5:3] 0b000 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High VAGND AGND VREFLO RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b001 RefPower = high Opamp bias = high RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Min Typ Max Units VDD/2 + Bandgap VDD/2 + 1.170 VDD/2 + 1.288 VDD/2 + 1.376 V VDD/2 VDD/2 – 0.098 VDD/2 + 0.003 VDD/2 + 0.097 V Ref Low VDD/2 – Bandgap VDD/2 – 1.386 VDD/2 – 1.287 VDD/2 – 1.169 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.210 VDD/2 + 1.290 VDD/2 + 1.355 V VAGND AGND VDD/2 VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.054 V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.359 VDD/2 – 1.292 VDD/2 – 1.214 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.198 VDD/2 + 1.292 VDD/2 + 1.368 V VAGND AGND VDD/2 VDD/2 – 0.041 VDD/2 VDD/2 + 0.04 V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.362 VDD/2 – 1.295 VDD/2 – 1.220 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.202 VDD/2 + 1.292 VDD/2 + 1.364 V VAGND AGND VDD/2 VDD/2 – 0.033 VDD/2 VDD/2 + 0.030 V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.364 VDD/2 – 1.297 VDD/2 – 1.222 V VREFHI Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 0.5 V) – 0.072 – 0.017 P2[4] + P2[6] + 0.041 V VAGND AGND P2[4] – VREFLO Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 0.5 V) – 0.029 + 0.010 P2[4] – P2[6] + 0.048 V VREFHI Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 0.5 V) – 0.066 – 0.010 P2[4] + P2[6] + 0.043 V VAGND AGND P2[4] – VREFLO Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 0.5 V) – 0.024 + 0.004 P2[4] – P2[6] + 0.034 V VREFHI Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 0.5 V) – 0.073 – 0.007 P2[4] + P2[6] + 0.053 V VAGND AGND P2[4] – VREFLO Ref Low P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 0.5 V) – 0.028 + 0.002 P2[4] – P2[6] + 0.033 V VREFHI Ref High P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 0.5 V) – 0.073 – 0.006 P2[4] + P2[6] + 0.056 V VAGND AGND P2[4] – VREFLO Ref Low Document Number: 001-44369 Rev. *G Description P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 0.5 V) – 0.030 + 0.032 V Page 25 of 53 CY8C23433, CY8C23533 Table 17. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b010 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High VAGND AGND VREFLO Ref Low VREFHI Ref High VAGND AGND VREFLO Ref Low VREFHI Ref High VAGND AGND RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Description Min Typ Max Units VDD – 0.102 VDD – 0.003 VDD V VDD/2 – 0.040 VDD/2 + 0.001 VDD/2 + 0.039 V VSS VSS VSS + 0.005 VSS + 0.020 V VDD VDD – 0.082 VDD – 0.002 VDD V VDD/2 – 0.031 VDD/2 VDD/2 + 0.028 V VSS VSS VSS + 0.003 VSS + 0.015 V VDD VDD – 0.083 VDD – 0.002 VDD V VDD/2 – 0.032 VDD/2 – 0.001 VDD/2 + 0.029 V VDD VDD/2 VDD/2 VDD/2 VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.014 V VREFHI Ref High VDD VDD – 0.081 VDD – 0.002 VDD V VAGND AGND VDD/2 – 0.033 VDD/2 – 0.001 VDD/2 + 0.029 V VDD/2 VREFLO Ref Low VSS VSS + 0.002 VSS + 0.013 V 0b011 All power settings Not allowed at 3.3 V – – – – – – – 0b100 All power settings Not allowed at 3.3 V – – – – – – – 0b101 RefPower = high Opamp bias = high VREFHI Ref High RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low VSS P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.211 P2[4] + 1.285 P2[4] + 1.348 V VAGND AGND VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.354 P2[4] – 1.290 P2[4] – 1.197 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.209 P2[4] + 1.289 P2[4] + 1.353 V P2[4] P2[4] P2[4] P2[4] – VAGND AGND VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.352 P2[4] – 1.294 P2[4] – 1.222 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.351 V P2[4] P2[4] P2[4] P2[4] – VAGND AGND VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.351 P2[4] – 1.296 P2[4] – 1.224 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.215 P2[4] + 1.292 P2[4] + 1.354 V VAGND AGND VREFLO Ref Low Document Number: 001-44369 Rev. *G P2[4] P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] – 1.352 P2[4] – 1.297 P2[4] – 1.227 – – V Page 26 of 53 CY8C23433, CY8C23533 Table 17. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b110 Reference Power Settings Symbol Reference RefPower = high Opamp bias = high VREFHI Ref High RefPower = high Opamp bias = low RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low 0b111 All power settings Not allowed at 3.3 V Description Min Typ Max Units 2 × Bandgap 2.460 2.594 2.695 V Bandgap 1.257 1.302 1.335 V VSS VSS + 0.01 VSS + 0.029 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 2 × Bandgap 2.462 2.592 2.692 V VAGND AGND Bandgap 1.256 1.301 1.332 V VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.017 V VREFHI Ref High 2 × Bandgap 2.473 2.593 2.682 V Bandgap 1.257 1.301 1.330 V VSS VSS + 0.003 VSS + 0.014 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 2 × Bandgap 2.470 2.594 2.685 V VAGND AGND Bandgap 1.256 1.300 1.332 V VREFLO Ref Low VSS VSS + 0.002 VSS + 0.012 V – – – – – – VSS – DC Analog PSoC Block Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and–40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 18. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units RCT Resistor unit value (continuous time) – 12.2 – k CSC Capacitor unit value (switch cap) – 80[9] – fF Document Number: 001-44369 Rev. *G Page 27 of 53 CY8C23433, CY8C23533 DC POR and LVD Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 19. DC POR and LVD Specifications Symbol Description VPPOR1 VPPOR2 VDD value for PPOR trip PORLEV[1:0] = 01b PORLEV[1:0] = 10b VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Vdd value for LVD trip VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units Notes – 2.82 4.55 2.95 4.70 V V VDD must be greater than or equal to 2.5 V during startup or reset from watchdog. 2.850 2.95 3.06 4.37 4.50 4.62 4.71 2.920 3.02 3.13 4.48 4.64 4.73 4.81 2.99[10] 3.09 3.20 4.55 4.75 4.83 4.95 V0 V0 V0 V0 V0 V V Notes 9. CSC is a design guarantee parameter, not tested value 10. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. Document Number: 001-44369 Rev. *G Page 28 of 53 CY8C23433, CY8C23533 DC Programming Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 20. DC Programming Specifications Min Typ Max Units Notes VDDP Symbol VDD for programming and erase Description 4.5 5 5.5 V This specification applies to the functional requirements of external programmer tools VDDLV Low VDD for verify 3.0 3.1 3.2 V This specification applies to the functional requirements of external programmer tools VDDHV High VDD for verify 5.1 5.2 5.3 V This specification applies to the functional requirements of external programmer tools 3.0 – 5.25 V This specification applies to this device when it is executing internal flash writes VDDIWRITE Supply voltage for flash write operation IDDP Supply current during programming or verify – 5 25 mA VILP Input low voltage during programming or verify – – 0.8 V VIHP Input high voltage during programming or verify 2.1 – – V IILP Input current when applying vilp to P1[0] or P1[1] during programming or verify – – 0.2 mA Driving internal pull down resistor IIHP Input current when applying vihp to P1[0] or P1[1] during programming or verify – – 1.5 mA Driving internal pull down resistor VOLV Output low voltage during programming or verify – – VSS + 0.75 V VOHV Output high voltage during programming or verify VDD - 1.0 – VDD V 50,000 – – – Erase/write cycles per block 1,800,000 – – – Erase/write cycles 10 – – Years FlashENPB Flash endurance (per block) (total)[11] FlashENT Flash endurance FlashDR Flash data retention DC I2C Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 21. DC I2C Specifications[12] Symbol VILI2C Input low level Description VIHI2C Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 3.0 V VDD 3.6 V 4.75 V VDD 5.25 V 3.0 V VDD 5.25 V Notes 11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to 0xthe Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. 12. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-44369 Rev. *G Page 29 of 53 CY8C23433, CY8C23533 SAR8 ADC DC Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 22. SAR8 ADC DC Specifications Symbol Description VADCVREF Reference voltage at pin P3[0] when configured as ADC reference voltage IADCVREF Current when P3[0] is configured as ADC VREF INL Integral non-linearity INL (limited range) Integral non-linearity accommodating a shift in the offset at 0x80 DNL Differential non-linearity DNL (limited range) Differential non-linearity excluding 0x7F-0x80 transition Min Typ Max Units Notes 3.0 – 5.25 V The voltage level at P3[0] (when configured as ADC reference voltage) must always be maintained to be less than chip supply voltage level on VDD pin. VADCVREF < VDD. 3 – – mA –1.5 – +1.5 LSB –1.2[12] – +1.2 LSB The maximum LSB is over a sub-range not exceeding 1/16 of the full-scale range. 0x7F and 0x80 points specs are excluded here –2.3 – +2.3 LSB ADC conversion is monotonic over full range –1 – +1 LSB ADC conversion is monotonic over full range. 0x7F to 0x80 transition specs are excluded here. Note 12. SAR converters require a stable input voltage during the sampling period. If the voltage into the SAR8 changes by more than 1 LSB during the sampling period then the accuracy specifications may not be met Document Number: 001-44369 Rev. *G Page 30 of 53 CY8C23433, CY8C23533 AC Electrical Characteristics AC Chip-Level Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 23. 5-V and 3.3-V AC Chip-Level Specifications Description Min Typ FIMO24 Symbol Internal main oscillator frequency for 24 MHz 23.4 24 FIMO6 Internal main oscillator frequency for 6 MHz 5.5 6 FCPU1 CPU frequency (5-V nominal) 0.093 24 FCPU2 CPU Frequency (3.3-V nominal) 0.093 12 12.3[13],[14] F48M Digital PSoC block frequency 0 48 49.2[13],[14],[1 6] F24M Digital PSoC block frequency 0 24 F32K1 F32K2 Internal low speed oscillator frequency External crystal oscillator 15 – 32 32.768 24.6[14],[16] 75 – F32K_U Internal low speed oscillator (ILO) untrimmed frequency 5 – 100 FPLL PLL frequency – 23.986 – 0.5 0.5 – – 10 50 – – 1700 2800 2620 3800 10 40 20 – 46.8 – 50 50 50 48.0 – 60 80 – TPLLSLEW PLL lock time TPLLSLEWSLO PLL lock time for low gain setting Max Units Notes 24.6[13],[14],[1 MHz Trimmed for 5V or 3.3V 5] operation using factory trim values. See Figure 8 on page 14. SLIMO mode = 0. 6.5[13],[14],[15] MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8 on page 14. SLIMO mode = 1. 24.6[13],[14] MHz SLIMO mode = 0. MHz SLIMO mode = 0. MHz Refer to the AC digital block Specifications. MHz kHz kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. kHz After a reset and before the m8c starts to run, the ILO is not trimmed. See the system resets section of the PSoC technical reference manual for details on timing this MHz Is a multiple (x732) of crystal frequency. ms ms W TOS TOSACC External crystal oscillator startup to 1% External crystal oscillator startup to 100 ppm TXRST DC24M DCILO Step24M Fout48M External reset pulse width 24 MHz duty cycle Internal low speed oscillator duty cycle 24 MHz trim step size 48 MHz output frequency 49.2[13],[15] ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V £ VDD £ 5.5V, –40 °C £ TA £ 85°C. ms % % kHz MHz Trimmed. Using factory trim values. Notes 13. 4.75V < Vdd < 5.25V. 14. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 15. 3.0V < Vdd < 3.6V. 16. See the individual user module data sheets for information on maximum frequencies for user modules. 17. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 001-44369 Rev. *G Page 31 of 53 CY8C23433, CY8C23533 Table 23. 5-V and 3.3-V AC Chip-Level Specifications (continued) Description Min Typ Max Units FMAX Symbol Maximum frequency of signal on row input or row output. – – 12.3 MHz SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during power up. TPOWERUP Time from end of POR to CPU executing code – 16 100 ms tjit_IMO [17] 24 MHz IMO cycle-to-cycle jitter (RMS) – 200 700 ps 24 MHz IMO long term N cycle-to-cycle jitter (RMS) – 300 900 ps 24 MHz IMO period jitter (RMS) – 100 400 ps 24 MHz IMO cycle-to-cycle jitter (RMS) – 200 800 ps 24 MHz IMO long term N cycle-to-cycle jitter (RMS) – 300 1200 ps 24 MHz IMO period jitter (RMS) – 100 700 ps tjit_PLL [17] Notes Power up from 0V. See the System Resets section of the PSoC technical reference manual. N = 32 N = 32 Figure 9. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 10. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 11. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz TOS F32K2 Document Number: 001-44369 Rev. *G Page 32 of 53 CY8C23433, CY8C23533 AC GPIO Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 24. 5-V and 3.3-V AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO GPIO operating frequency 0 – 12.3 MHz TRiseF Rise time, normal strong mode, cload = 50 pF 3 – 18 ns VDD = 4.5 V to 5.25 V, 10% - 90% Normal strong mode TFallF Fall time, normal strong mode, cload = 50 pF 2 – 18 ns VDD = 4.5 V to 5.25 V, 10% - 90% TRiseS Rise time, slow strong mode, cload = 50 pF 10 27 – ns VDD = 3 V to 5.25 V, 10% - 90% TFallS Fall time, slow strong mode, cload = 50 pF 10 22 – ns VDD = 3 V to 5.25 V, 10% - 90% Figure 12. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS Document Number: 001-44369 Rev. *G TFallF TFallS Page 33 of 53 CY8C23433, CY8C23533 AC Operational Amplifier Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V. Table 25. 5-V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units TROA Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high – – – – – – 3.9 0.72 0.62 s s s TSOA Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high – – – – – – 5.9 0.92 0.72 s s s SRROA Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high 0.15 1.7 6.5 – – – – – – V/s V/s V/s SRFOA Falling slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high 0.01 0.5 4.0 – – – – – – V/s V/s V/s BWOA Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high 0.75 3.1 5.4 – – – – – – MHz MHz MHz Min Typ Max Units – – – – 3.92 0.72 s s – – – – 5.41 0.72 s s 0.31 2.7 – – – – V/s V/s 0.24 1.8 – – – – V/s V/s 0.67 2.8 – – – – MHz MHz Table 26. 3.3-V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Document Number: 001-44369 Rev. *G Page 34 of 53 CY8C23433, CY8C23533 When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 13. Typical AGND Noise with P2[4] Bypass nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 14. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 Document Number: 001-44369 Rev. *G 0.01 0.1 Freq (kHz) 1 10 100 Page 35 of 53 CY8C23433, CY8C23533 AC Low Power Comparator Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 27. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – Typ – Max 50 Units ms Notes ³ 50 mV overdrive comparator reference set within VREFLPC AC Digital Block Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 28. 5-V and 3.3-V AC Digital Block Specifications Function All functions Timer Description Max Unit – – 49.2 MHz VDD < 4.75 V – – 24.6 MHz Notes No capture, VDD 4.75 V – – 49.2 MHz No capture, VDD < 4.75 V – – 24.6 MHz With capture – – 24.6 MHz 50[18] – – ns Input clock frequency Input clock frequency No enable input, VDD 4.75 V – – 49.2 MHz No enable input, VDD < 4.75 V – – 24.6 MHz With enable input – – 24.6 MHz 50[18] – – ns Enable input pulse width Dead Band Typ VDD 4.75 V Capture pulse width Counter Min Block input clock frequency Kill pulse width Asynchronous restart mode 20 – – ns Synchronous restart mode 50[18] – – ns Disable mode 50[18] – – ns – – 49.2 MHz – – 24.6 MHz VDD 4.75 V – – 49.2 MHz VDD < 4.75 V – – 24.6 MHz Input clock frequency VDD 4.75 V VDD < 4.75 V CRCPRS (PRS Mode) Input clock frequency CRCPRS (CRC Mode) Input clock frequency – – 24.6 MHz SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode. SPIS Input clock (SCLK) frequency Width of SS_negated between transmissions Transmitter – 4.1 MHz – – ns – – 49.2 MHz Input clock frequency VDD 4.75 V, 2 stop bits Receiver – 50[18] The baud rate is equal to the input clock frequency divided by 8. VDD 4.75 V, 1 stop bit – – 24.6 MHz VDD < 4.75 V – – 24.6 MHz – – 49.2 MHz Input clock frequency VDD 4.75 V, 2 stop bits The baud rate is equal to the input clock frequency divided by 8. VDD 4.75 V, 1 stop bit – – 24.6 MHz VDD < 4.75 V – – 24.6 MHz Note 18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-44369 Rev. *G Page 36 of 53 CY8C23433, CY8C23533 AC Analog Output Buffer Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 29. 5-V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units TROB Rising settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high – – – – 2.5 2.5 s s TSOB Falling settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high – – – – 2.2 2.2 s s SRROB Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = low Power = high 0.65 0.65 – – – – V/s V/s SRFOB Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = low Power = high 0.65 0.65 – – – – V/s V/s BWOB Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high 0.8 0.8 – – – – MHz MHz BWOB Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high 300 300 – – – – kHz kHz Min Typ Max Units Table 30. 3.3-V AC Analog Output Buffer Specifications Symbol Description TROB Rising settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high – – – – 3.8 3.8 s s TSOB Falling settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high – – – – 2.6 2.6 s s SRROB Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = low Power = high 0.5 0.5 – – – – V/s V/s SRFOB Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = low Power = high 0.5 0.5 – – – – V/s V/s BWOB Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high 0.7 0.7 – – – – MHz MHz BWOB Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high 200 200 – – – – kHz kHz Document Number: 001-44369 Rev. *G Page 37 of 53 CY8C23433, CY8C23533 AC External Clock Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 31. 5-V AC External Clock Specifications Symbol Description Min Typ Max Units FOSCEXT Frequency 0.093 – 24.6 MHz – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power up IMO to switch 150 – – s Table 32. 3.3-V AC External Clock Specifications Symbol Description Min Typ Max Units 0.093 – 12.3 MHz Frequency with CPU clock divide by 2 or greater[20] 0.186 – 24.6 MHz – High period with CPU clock divide by 1 41.7 – 5300 ns – Low period with CPU clock divide by 1 41.7 – – ns – Power up IMO to switch 150 – – s FOSCEXT Frequency with CPU clock divide by FOSCEXT 1[19] AC Programming Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 33. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise time of SCLK 1 – 20 ns TFSCLK Fall time of SCLK 1 – 20 ns TSSCLK Data set up time to falling edge of SCLK 40 – – ns THSCLK Data hold time from falling edge of SCLK 40 – – ns FSCLK Frequency of SCLK 0 – 8 MHz TERASEB Flash erase time (block) – 20 – ms TWRITE Flash block write time – 20 – ms TDSCLK Data out delay from falling edge of SCLK – – 45 ns VDD 3.6 TDSCLK3 Data out delay from falling edge of SCLK – – 50 ns 3.0 VDD 3.6 TERASEALL Flash erase time (bulk) – 80 – ms Erase all Blocks and protection fields at once TPROGRAM_HOT Flash block erase + Flash block write time – – 100[22] ms 0 °C <= Tj <= 100°C TPROGRAM_COLD Flash block erase + Flash block write time – – 200[22] ms –40 °C <= Tj <= 0 °C Notes 19. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 20. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 21. The max sample rate in this R2R ADC is 3.0/8=375KSPS 22. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-44369 Rev. *G Page 38 of 53 CY8C23433, CY8C23533 SAR8 ADC AC Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 34. SAR8 ADC AC Specifications[21] Symbol Description Min Typ Max Units Freq3 Input clock frequency 3 V – – 3.075 MHz Freq5 Input clock frequency 5 V – – 3.075 MHz AC I2C Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 35. AC Characteristics of the I2C SDA and SCL Pins for VDD > 3.0 V Symbol Description Standard Mode Fast Mode Units Min Max Min Max 0 100 0 400 kHz FSCLI2C SCL clock frequency THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 – 0.6 – s TLOWI2C LOW period of the SCL clock 4.7 – 1.3 – s THIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – s TSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – s 0 – 0 – s – ns THDDATI2C Data hold time TSUDATI2C Data setup time 250 – 100 [23] TSUSTOI2C Setup Time for STOP condition 4.0 – 0.6 – s TBUFI2C Bus free time between a STOP and START condition 4.7 – 1.3 – s TSPI2C Pulse width of spikes are suppressed by the input filter. – – 0 50 ns Note 23. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-44369 Rev. *G Page 39 of 53 CY8C23433, CY8C23533 Table 36. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V (Fast Mode Not Supported) Symbol Standard Mode Description Fast Mode Min Max Min Max Units FSCLI2C SCL clock frequency 0 100 – – kHz THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4.0 – – – s TLOWI2C LOW period of the SCL clock 4.7 – – – s THIGHI2C HIGH period of the SCL clock 4.0 – – – s TSUSTAI2C Setup time for a repeated START condition 4.7 – – – s 0 – – – s 250 – – – ns TSUSTOI2C Setup time for STOP condition 4.0 – – – s TBUFI2C Bus free time between a STOP and START condition 4.7 – – – s TSPI2C Pulse width of spikes are suppressed by the input filter. – – – – ns THDDATI2C Data hold time TSUDATI2C Data setup time Figure 15. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C TSPI2C THDDATI2CTSUSTAI2C TBUFI2C I2C_SCL THIGHI2C TLOWI2C S START Condition Document Number: 001-44369 Rev. *G TSUSTOI2C Sr Repeated START Condition P S STOP Condition Page 40 of 53 CY8C23433, CY8C23533 Packaging Information This section illustrates the packaging specifications for the CY8C23x33 PSoC device, along with the thermal impedances for each package, solder reflow peak temperature, and the typical package capacitance on crystal pins. Figure 16. 32-Pin (5x5 mm) QFN 001-42168 *E Document Number: 001-44369 Rev. *G Page 41 of 53 CY8C23433, CY8C23533 Figure 17. 28-Pin (210-Mil) SSOP 51-85079 *E Thermal Impedances Capacitance on Crystal Pins Table 37. Thermal Impedances by Package Package Typical Table 38. Typical Package Capacitance on Crystal Pins JA[22] Package 32 QFN 19.4 °C/W 32 QFN 28 SSOP 95 °C/W 28 SSOP Package Capacitance 2.0 pF 2.8 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 39. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Peak Temperature 32 QFN 260 °C 30 s 28 SSOP 260 °C 30 s Note 22. TJ = TA + POWER x JA. Document Number: 001-44369 Rev. *G Page 42 of 53 CY8C23433, CY8C23533 Ordering Information The following table lists the CY8C23X33 PSoC device family key package features and ordering codes. RAM (Bytes) Temperature Range Digital Blocks (Rows of 4) Analog Blocks (Columns of 3) Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 32 Pin QFN 32 Pin QFN (Tape and Reel) 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) Flash (Kbytes) Package Ordering Code Table 40. CY8C23X33 PSoC Device Family Key Features and Ordering Information 8 8 8 8 256 256 256 256 –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C 4 4 4 4 4 4 4 4 26 26 26 26 12 12 12 12 2 2 2 2 Yes Yes No No CY8C23533-24LQXI CY8C23533-24LQXIT CY8C23433-24PVXI CY8C23433-24PVXIT Ordering Code Definitions CY 8 C 23 xxx-24xx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LKX/LTX /LQX/LCX= QFN Pb-free AX = TQFP Pb-free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-44369 Rev. *G Page 43 of 53 CY8C23433, CY8C23533 Acronyms Acronyms Used Table 41 lists the acronyms that are used in this document. Table 41. Acronyms Used in this Datasheet Acronym AC ADC Description Acronym Description alternating current MIPS million instructions per second analog-to-digital converter PCB printed circuit board API application programming interface PGA programmable gain amplifier CPU central processing unit PLL phase-locked loop CRC cyclic redundancy check POR power on reset CT DAC continuous time digital-to-analog converter PPOR PRS DC direct current DNL differential nonlinearity PWM pulse width modulator DTMF dual-tone multi-frequency QFN quad flat no leads ECO external crystal oscillator RTC real time clock electrically erasable programmable read-only memory SAR successive approximation EEPROM GPIO general purpose I/O ICE in-circuit emulator IDE integrated development environment PSoC® precision power on reset pseudo-random sequence SC SLIMO Programmable System-on-Chip switched capacitor slow IMO SMP switch mode pump ILO internal low speed oscillator SOIC small-outline integrated circuit IMO internal main oscillator SPITM serial peripheral interface INL integral nonlinearity SRAM static random access memory I/O input/output SROM supervisory read only memory infrared data association SSOP shrink small-outline package ISSP in-system serial programming UART LPC low power comparator USB universal serial bus LVD low voltage detect WDT watchdog timer MAC multiply-accumulate XRES external reset MCU microcontroller unit IrDA universal asynchronous reciever / transmitter Reference Documents Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Document Number: 001-44369 Rev. *G Page 44 of 53 CY8C23433, CY8C23533 Document Conventions Units of Measure Table 42 lists the unit sof measures. Table 42. Units of Measure Symbol Unit of Measure Symbol Unit of Measure kB 1024 bytes ms millisecond dB decibels ns nanosecond °C degree Celsius ps picosecond fF femto farad µV microvolts pF picofarad mV millivolts mVpp kHz kilohertz MHz megahertz LSB least significant bit nV V millivolts peak-to-peak nanovolts volts k kilohm µW microwatts µA microampere W watt mA milliampere mm millimeter nA nanoampere ppm parts per million pA pikoampere % µs microsecond percent Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Document Number: 001-44369 Rev. *G Page 45 of 53 CY8C23433, CY8C23533 Glossary active high 5. A logic signal having its asserted state as the logic 1 state. 6. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. API (Application Programming Interface) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. Bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. Document Number: 001-44369 Rev. *G Page 46 of 53 CY8C23433, CY8C23533 Glossary (continued) compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. Document Number: 001-44369 Rev. *G Page 47 of 53 CY8C23433, CY8C23533 Glossary (continued) ICE The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a (LVD) selected threshold. M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. Document Number: 001-44369 Rev. *G Page 48 of 53 CY8C23433, CY8C23533 Glossary (continued) port A group of pins, usually eight. power on reset (POR) A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. Document Number: 001-44369 Rev. *G Page 49 of 53 CY8C23433, CY8C23533 Glossary (continued) tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-44369 Rev. *G Page 50 of 53 CY8C23433, CY8C23533 Silicon Errata for the CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip This section describes the errata for the CY8C23433, CY8C23533 PSoC® programmable system-on-chip family. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number CY8C23433 Ordering Information CY8C23433-24PVXI CY8C23433-24PVXIT CY8C23533 CY8C23533-24LQXI CY8C23533-24LQXIT CY8C23433 Qualification Status Product Status: Production CY8C23433 Errata Summary The following table defines the errata applicability to available CY8C23433 family devices. An "X" indicates that the errata pertains to the selected device. Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description. Items Part Number Silicon Revision [1.]. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes CY8C23433 A Fix Status Silicon fix is planned. 1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes ■ Problem Definition Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70°C. This problem does not affect end-product usage between 0 and 70 °C. ■ Parameters Affected The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%. ■ Trigger Condition(S) The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when operated beyond the temperature range of 0 to +70 °C. ■ Scope of Impact This problem may affect UART, IrDA, and FSK implementations. ■ Workaround Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface. ■ Fix Status The cause of this problem and its solution has been identified. Silicon fix is planned to correct the deficiency in silicon. Document Number: 001-44369 Rev. *G Page 51 of 53 CY8C23433, CY8C23533 Document History Page Document Title: CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip™ Document Number: 001-44369 Revision ECN Orig. of Change Submission Date ** 2044848 KIY/AESA 01/30/2008 Data sheet creation *A 2482967 HMI/AESA 05/14/2008 Moved from Preliminary to Final. Part number changed to CY8C23433, CY8C23533. Adjusted placement of the block diagram; updated description of DAC; updated package pinout description, updated POR and LVD spec, Added Csc , Flash Vdd, SAR ADC spec. Updated package diagram 001-42168 to *A. Updated data sheet template. *B 2616862 OGNE/AESA 12/05/2008 Changed title to: “CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip™” Updated package diagram 001-42168 to *C. Changed names of registers on page 11. "SARADC_C0" to "SARADC_CR0" "SARADC_C1" to "SARADC_CR1" *C 2883928 JVY 02/24/2010 Updated the following parameters: DCILO, SRPOWERUP, F32K_U, FIMO6, TPOWERUP, TERASE_ALL, TPROGRAM_HOT, TPROGRAM_COLD Updated package diagrams Added Table of Contents *D 3118801 NJF 12/23/10 Updated PSoC Device Characteristics table . Added DC I2C Specifications table. Added Tjit_IMO specification, removed existing jitter specifications. Updated 3.3 V operational amplifier specifications and DC analog reference specifications tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 13 since the labelling for y-axis was incorrect. Added ordering code definitions. *E 3283782 SHOB 08/16/11 Updated Getting Started, Development Tools and Designing with PSoC Designer. Updated Solder Reflow Peak Temperature Removed reference to obsolete Application Note AN2012. *F 3598316 LURE/XZNG 04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”. *G 3993381 05/08/2013 Updated Packaging Information: spec 001-42168 – Changed revision from *D to *E. GVH Description of Change Updated Reference Documents (Removed 001-14503 spec related information). Added Silicon Errata for the CY8C23433, CY8C23533 PSoC® Programmable System-on-Chip. Document Number: 001-44369 Rev. *G Page 52 of 53 CY8C23433, CY8C23533 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-44369 Rev. *G Revised May 7, 2013 Page 53 of 53 PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. 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