CYPRESS CY8C24533

CY8C24533
PSoC® Programmable System-on-Chip™
Features
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐ 4 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO pins
❐ Complex Peripherals by Combining Blocks
❐ High-Speed 8-Bit SAR ADC Optimized for Motor Control
■
■
■
■
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Logic Block Diagram
Port 3
Port 2
Port 1 Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Global Analog Interconnect
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Precision, Programmable Clocking
❐ Internal ±5% 24/48 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
DIGITAL SYSTEM
Digital
Block
Array
Flexible On-Chip Memory
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Digital
Clocks
Programmable Pin Configurations
❐ 25 mA Sink on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Additional System Resources
2
❐ I C™ Slave, Master, and Multi-master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-chip Precision Voltage Reference
Cypress Semiconductor Corporation
Document Number: 001-14643 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 05, 2008
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PSoC Functional Overview
Digital System
The PSoC family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and
packages.
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
To System Bus
Digital Clocks
FromCore
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC CY8C24x33 family can
have up to three IO ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
Port 1
Port 0
ToAnalog
System
DIGITAL SYSTEM
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
Row Output
Configuration
8
Row Input
Configuration
Digital PSoC Block Array
8
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 11 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Document Number: 001-14643 Rev. *D
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
The digital peripheral configurations include:
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 1)
■
SPI master and slave (up to 1)
■
I2C slave and master (one available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to one)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled PSoC Device Characteristics on page 4.
Page 2 of 34
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The Analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog
functions (most available as user modules) are:
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
Analog System
P2[3]
P2[6]
P2[4]
P2[1]
■
Filters (2 and 4 pole band pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
P0[7:0]
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-14643 Rev. *D
Page 3 of 34
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Getting Started
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource follow:
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SAR8
ADC
Table 1. PSoC Device Characteristics
CY8C29x66
up to
64
4
16
12
4
4
12
No
CY8C27x43
up to
44
2
8
12
4
4
12
No
CY8C24x94
56
1
4
48
2
2
6
No
CY8C24533
up to
26
1
4
12
2
2
4
Yes
CY8C24x23A
up to
24
1
4
12
2
2
6
No
CY8C21x34
up to
28
1
4
28
0
2
4[1]
No
No
No
PSoC Part
Number
CY8C21x23
16
1
4
8
0
2
4[1]
CY8C20x34
up to
28
0
0
28
0
0
3[2]
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the PSoC
CY8C24533 Mixed-Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application Note
AN2209 at http://www.cypress.com and select Application Notes
under the Design Resources.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/onlinestore.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
analog
and
CapSense.
Go
to
http://www.cypress.com.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located at the top of the web page, and select CYPros
Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com/psocapnotes.
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense.
Document Number: 001-14643 Rev. *D
Page 4 of 34
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Development Tools
PSoC Designer Software Subsystems
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (Refer Figure 3).
Device Editor
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Graphical Designer
Interface
Context
Sensitive
Help
Results
Commands
PSoC
Designer
Application
Database
PSoC
Designer
Core
Engine
Project
Database
PSoC
Configuration
Sheet
Manufacturing
Information
File
PSoC Designer sets up power on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, compile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
User
Modules
Library
Emulation
Pod
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
Design Browser
Importable
Design
Database
Device
Database
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
In-Circuit
Emulator
Device
Programmer
C Language Compiler. A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Document Number: 001-14643 Rev. *D
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Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
Document Number: 001-14643 Rev. *D
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and enter
parameter values directly or by selecting values from drop-down
menus. When you are ready to test the hardware configuration
or move on to developing code for the project, you perform the
“Generate Application” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the high-level user module API
functions.
Figure 4. User Module/Source Code Development Flows
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
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The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you to define complex
breakpoint events that include monitoring address and data bus
values, memory locations, and external signals.
Table 2. Acronyms Used (continued)
Acronym
Description
PWM
pulse width modulator
RAM
random access memory
ROM
read only memory
SC
switched capacitor
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 6 on page 13 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms Used
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
Document Number: 001-14643 Rev. *D
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Pinouts
The PSoC CY8C24533 is available in a 28-pin SSOP package. Every port pin (labeled with a “P”), except for Vss and Vdd in the
following table and figure, is capable of Digital IO.
28-Pin Part Pinout
Figure 5. CY8C24533 PSoC Device
Pin Name
Analog
Digital
Pin Number
CY8C24533
Table 3. 28-Pin Part Pinout (SSOP)
Description
1
IO
I
P0[7]
Analog Col Mux IP and ADC IP
2
IO
IO
P0[5]
Analog Col Mux IP and Column O/P and ADC
IP
3
4
IO
IO
IO
I
P0[3]
P0[1]
Analog Col Mux IP and Column O/P and ADC
IP
Analog Col Mux IP and ADC IP
5
IO
P2[7]
GPIO
6
IO
P2[5]
GPIO
7
IO
P2[3]
Direct switched capacitor input
8
IO
I
I
P2[1]
Direct switched capacitor input
IO
AVref P3[0]
IO
P1[7]
11
IO
P1[5]
I2C SDA
12
IO
P1[3]
GPIO
13
IO
P1[1][4]
GPIO, Xtal input, I2C SCL, ISSP SCL
14
Power
Vss
Vdd
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], IO
AIO, P2[3]
7
22
P2[4], IO
AIO, P2[1]
8
21
P2[2], AIO
AVref, IO, P3[0]
9
20
P2[0], AIO
I2C SCL, IO, P1[7]
10
19
P3[1], IO
I2C SDA, IO, P1[5]
11
18
P1[6], IO
IO, P1[3]
12
17
P1[4], IO, EXTCLK
I2C SCL, ISSP SCL, XTALin, IO, P1[1]
13
16
P1[2], IO
14
15
P1[0], IO, XTALout, ISSP SDA, I2CSDA
Vss
SSOP
Ground pin
IO
P1[0]
GPIO, Xtal output, I2C SDA, ISSP SDA
16
IO
P1[2]
GPIO
17
IO
P1[4]
GPIO, external clock IP
18
IO
P1[6]
GPIO
[4]
19
IO
P3[1][5]
GPIO
20
IO
I
P2[0]
Direct switched capacitor input
21
IO
I
P2[2]
Direct switched capacitor input
22
IO
P2[4]
GPIO
23
IO
P2[6]
GPIO
24
IO
I
P0[0]
Analog Col Mux IP and ADC IP
25
IO
I
P0[2]
Analog Col Mux IP and ADC IP
26
IO
I
P0[4]
Analog Col Mux IP and ADC IP
27
IO
I
P0[6]
Analog Col Mux IP and ADC IP
Vdd
Supply voltage
Power
28
2
I2C SCL
15
28
1
IO, P0[5]
GPIO/ADC Vref (optional)
9
10
[3]
AIO, P0[7]
LEGEND: A = Analog, I = Input, and O = Output.
Notes
3. Even though P3[0] is an odd port, it resides on the left side of the pinout.
4. ISSP pin, which is not High Z at POR.
5. Even though P3[1] is an even port, it resides on the right side of the pinout.
Document Number: 001-14643 Rev. *D
Page 8 of 34
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CY8C24533
Register Reference
This chapter lists the registers of the CY8C24533 PSoC device by using mapping tables, in offset order. For detailed register information, refer the PSoC CY8C24533 Mixed-Signal Array Technical Reference Manual.
Register Conventions
Register Mapping Tables
Abbreviations Used
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
The register conventions specific to this section are listed in the
following table.
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-14643 Rev. *D
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Page 9 of 34
[+] Feedback
CY8C24533
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
Gray fields are reserved.
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
SARADC_DL
SARADC_CR0
SARADC_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1 *
ACB01CR2 *
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
Name
Access
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Addr
(0,Hex)
Name
Table 4. Register Map Bank 0 Table: User Space
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
# Access is bit specific.
Document Number: 001-14643 Rev. *D
Page 10 of 34
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CY8C24533
Gray fields are reserved.
CPU_SCR1
CPU_SCR0
Access
BE
BF
Name
Access
Addr
(0,Hex)
Name
Access
7E
7F
Addr
(0,Hex)
3E
3F
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
Table 4. Register Map Bank 0 Table: User Space (continued)
FE
FF
#
#
# Access is bit specific.
DBB00FN
DBB00IN
DBB00OU
DBB01FN
DBB01IN
DBB01OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
Gray fields are reserved.
RW
RW
RW
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SARADC_TRS
SARADC_TRCL
SARADC_TRCH
SARADC_CR2
SARADC_LCR
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
RW
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
Access
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(1,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
Name
Access
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
Addr
(1,Hex)
Name
Table 5. Register Map Bank 1 Table: Configuration Space
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
# Access is bit specific.
Document Number: 001-14643 Rev. *D
Page 11 of 34
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CY8C24533
Gray fields are reserved.
FLS_PR1
CPU_SCR1
CPU_SCR0
Access
Name
CPU_F
Addr
(1,Hex)
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
RW
Addr
(1,Hex)
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Name
ACB01CR2 *
Addr
(1,Hex)
37
38
39
3A
3B
3C
3D
3E
3F
Access
Addr
(1,Hex)
Name
Table 5. Register Map Bank 1 Table: Configuration Space (continued)
F7
F8
F9
FA
FB
FC
FD
FE
FF
RL
RW
#
#
# Access is bit specific.
Document Number: 001-14643 Rev. *D
Page 12 of 34
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CY8C24533
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24533 PSoC device. For the latest electrical specifications,
visit http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted.
Refer to Table 21 on page 22 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 7. IMO Frequency Trim Options
5.25
SLIMO Mode = 0
Figure 6. Voltage versus CPU Frequency
5.25
SLIMO
Mode=1
SLIMO
Mode=0
Vdd Voltage
Vdd Voltage
SLIMO
Mode=0
4.75
lid g
Va ratin n
pe io
O Reg
4.75
SLIMO
Mode=1
3.60
3.00
3.00
93 kHz
12 MHz
3 MHz
93 kHz
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 6. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
°C
degree Celsius
μW
micro watts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nano ampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
W
ohm
MHz
megahertz
pA
pico ampere
MΩ
megaohm
pF
pico farad
μA
micro ampere
pp
peak-to-peak
μF
micro farad
ppm
μH
micro henry
ps
picosecond
μs
microsecond
sps
samples per second
μV
micro volts
s
sigma: one standard deviation
micro volts root-mean-square
V
volts
μVrms
Document Number: 001-14643 Rev. *D
parts per million
Page 13 of 34
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CY8C24533
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
Notes
-55
25
+100
°C
Higher storage temperatures reduces
data retention time. Recommended
storage temperature is +25°C ± 25°C.
Extended duration storage temperatures above 65°C degrades reliability.
Ambient Temperature with Power Applied
-40
–
+85
°C
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5
V
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
TSTG
Storage Temperature
TA
Vdd
VIO
VIOZ
IMIO
Maximum Current into any Port Pin
ESD
Electro Static Discharge Voltage
LU
Latch-up Current
-25
–
+50
mA
2000
–
–
V
–
–
200
mA
Min
Typ
Max
Units
Human Body Model ESD
Operating Temperature
Table 8. Operating Temperature
Symbol
Description
TA
Ambient Temperature
-40
–
+85
°C
TJ
Junction Temperature
-40
–
+100
°C
Document Number: 001-14643 Rev. *D
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances by Package on
page 32. The user must limit the power
consumption to comply with this
requirement.
Page 14 of 34
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CY8C24533
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
3.0
–
Typ
–
5
Max
5.25
8
Units
V
mA
IDD3
Supply Current
–
3.3
6.0
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[6]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[6]
–
4
25
μA
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[6]
–
4
7.5
μA
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[6]
–
5
26
μA
1.28
1.30
1.33
V
VREF
Reference Voltage (Bandgap)
Notes
See Table 19 on page 21.
Conditions are Vdd = 5.0V, TA = 25
°C, CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz.
Conditions are Vdd = 3.3V, TA =
25°C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40°C ≤
TA ≤ 55°C, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55°C <
TA ≤ 85°C, analog power = off.
Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3V, -40°C ≤ TA ≤ 55°C,
analog power = off.
Conditions are with properly loaded,
1μW max, 32.768 kHz crystal.
Vdd = 3.3 V, 55°C < TA ≤ 85°C,
analog power = off.
Trimmed for appropriate Vdd.
Vdd > 3.0V
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have
similar functions enabled.
Document Number: 001-14643 Rev. *D
Page 15 of 34
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CY8C24533
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Pull up Resistor
RPU
Pull down Resistor
RPD
High Output Level
VOH
VOL
Low Output Level
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
COUT
Capacitive Load on Pins as Output
Document Number: 001-14643 Rev. *D
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
–
–
0.75
V
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
–
3.5
10
pF
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
maximum 40 mA on odd port pins (for
example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port pins
(for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 100 mA
maximum combined IOH budget.
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
Gross tested to 1 μA
Package and pin dependent.
Temp = 25°C
Package and pin dependent.
Temp = 25°C
Page 16 of 34
[+] Feedback
CY8C24533
DC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 11. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
Input Capacitance (Port 0 Analog Pins)
CINOA
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
20
4.5
0.0
0.5
–
–
–
60
60
80
VOHIGHOA High Output Voltage Swing (internal signals)
Vdd - 0.2
Power = Low, Opamp Bias = High
Vdd - 0.2
Power = Medium, Opamp Bias = High
Vdd - 0.5
Power = High, Opamp Bias = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
–
Power = Medium, Opamp Bias = High
–
Power = High, Opamp Bias = High
–
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = High
–
Power = Medium, Opamp Bias = Low
–
Power = Medium, Opamp Bias = High
–
Power = High, Opamp Bias = Low
–
Power = High, Opamp Bias = High
–
PSRROA Supply Voltage Rejection Ratio
52
Document Number: 001-14643 Rev. *D
Notes
μV/°C
pA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
Vdd
V
The common-mode input
Vdd - 0.5
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics of the analog output
buffer.
–
dB Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum
is 60 dB.
35.0
–
9.5
–
–
–
–
–
–
V
V
V
–
–
–
0.2
0.2
0.5
V
V
V
300
600
1200
2400
4600
80
400
800
1600
3200
6400
–
μA
μA
μA
μA
μA
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Page 17 of 34
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CY8C24533
Table 12. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
TCVOSOA Average Input Offset Voltage Drift
Min
Typ
Max
Units
–
–
1.65
1.32
10
8
mV
mV
–
7.0
35.0
μV/°
C
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics of the analog output
buffer.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
dB
60
60
80
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
μA
μA
μA
μA
μA
PSRROA
Supply Voltage Rejection Ratio
52
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 13. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
0.2
–
Vdd - 1
V
LPC supply current
–
10
40
μA
LPC voltage offset
–
2.5
30
mV
VREFLPC
Low power comparator (LPC) reference voltage
range
ISLPC
VOSLPC
Document Number: 001-14643 Rev. *D
Notes
Page 18 of 34
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CY8C24533
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 14. 5V DC Analog Output Buffer Specifications
Symbol
Typ
Max
–
3
12
mV
–
+6
–
μV/°C
0.5
–
Vdd - 1.0
V
–
–
1
1
–
–
W
W
VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd + 1.1
Power = High
0.5 x Vdd + 1.1
–
–
–
–
V
V
VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
VOSOB
Description
Input Offset Voltage (Absolute Value)
TCVOSOB Average Input Offset Voltage Drift
VCMOB
Common-Mode Input Voltage Range
ROUTOB
Output Resistance
Power = Low
Power = High
Min
Units
Notes
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRROB
Supply Voltage Rejection Ratio
52
64
–
dB
VOUT > (Vdd - 1.25)
Min
Typ
Max
Units
Notes
–
3
12
mV
Table 15. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
Description
Input Offset Voltage (Absolute Value)
–
+6
–
μV/°C
0.5
-
Vdd - 1.0
V
–
–
1
1
–
–
W
W
VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2)
0.5 x Vdd + 1.0
Power = Low
0.5 x Vdd + 1.0
Power = High
–
–
–
–
V
V
VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
0.8
2.0
2.0
4.3
mA
mA
Supply Voltage Rejection Ratio
52
64
–
dB
TCVOSOB Average Input Offset Voltage Drift
VCMOB
Common-Mode Input Voltage Range
ROUTOB
Output Resistance
Power = Low
Power = High
ISOB
PSRROB
Document Number: 001-14643 Rev. *D
VOUT > (Vdd - 1.25)
Page 19 of 34
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CY8C24533
DC Analog Reference Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 16. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
–
AGND = Vdd/2
1.28
1.30
1.33
V
Vdd/2 - 0.04
Vdd/2 - 0.01
Vdd/2 + 0.007
V
–
AGND = 2 x BandGap
–
AGND = P2[4] (P2[4] = Vdd/2)
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
–
AGND = BandGap
–
AGND = 1.6 x BandGap
–
AGND Block to Block Variation
(AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
–
RefHi = 3 x BandGap
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG + 0.098
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
P2[4] + P2[6]+ 0.100
V
–
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
V
–
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
BG - 0.009
BG + 0.008
BG + 0.016
V
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
-0.034
0.000
0.034
V
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
V
3 x BG - 0.06
3 x BG
3 x BG + 0.06
V
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
P2[4] - P2[6] - 0.057
P2[4] - P2[6] + 0.026
P2[4] - P2[6] + 0.110
V
Typ
Max
Units
Table 17. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
BG
Bandgap Voltage Reference
–
AGND = Vdd/2
–
AGND = 2 x BandGap
–
AGND = P2[4] (P2[4] = Vdd/2)
–
AGND = BandGap
–
AGND = 1.6 x BandGap
–
AGND Column to Column Variation
(AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
Document Number: 001-14643 Rev. *D
1.28
1.30
1.33
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
V
P2[4] - 0.008
P2[4] + 0.001
P2[4] + 0.009
V
Not Allowed
BG - 0.009
BG + 0.005
BG + 0.015
V
1.6 x BG - 0.027
1.6 x BG - 0.010
1.6 x BG + 0.018
V
-0.034
0.000
0.034
mV
P2[4] + P2[6] + 0.057
V
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009
Page 20 of 34
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CY8C24533
Table 17. 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
Min
Typ
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
Max
Units
P2[4] - P2[6] + 0.092
V
Not Allowed
P2[4] - P2[6] - 0.048
P2[4]- P2[6] + 0.022
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. DC Analog PSoC Block Specifications
Symbol
Description
RCT
Resistor Unit Value (Continuous Time)
Min
–
Typ
12.2
Max
–
Units
kΩ
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. Refer the PSoC CY8C24533 Mixed-Signal
Array Technical Reference Manual for more information on the VLT_CR register.
Table 19. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.400
2.850
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V0
V0
V0
V0
V0
V
V
V
Vdd Value for PPOR Trip
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Notes
Vdd must be greater than or
equal to 2.5V during startup or
reset from Watchdog.
Notes
7. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-14643 Rev. *D
Page 21 of 34
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CY8C24533
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC Programming Specifications
Symbol
Description
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)
FlashENT
FlashDR
Flash Endurance (total)[9]
Flash Data Retention
Min
3.3
–
–
Typ
–
5
–
Max
–
25
0.8
Units
V
mA
V
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
Vss + 0.75
V
Vdd - 1.0
–
Vdd
V
50,000
–
–
–
1,800,000
10
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
Erase/write cycles per
block.
Erase/write cycles.
SAR8 ADC DC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. SAR8 ADC DC Specifications
Symbol
Description
VADCVREF
Reference voltage at pin P3[0] when
configured as ADC reference voltage
IADCVREF
Current when P3[0] is configured as ADC VREF
Non-linearity[10]
INL
R-2R Integral
DNL
R-2R Differential Non-linearity[11]
Min
Typ
Max
Units
Notes
3.0
–
5.25
V
The voltage level at P3[0]
(when configured as ADC
reference voltage) must
always be maintained to
be less than chip supply
voltage level on Vdd pin.
VADCVREF < Vdd.
3
–
–
mA
-1.2
–
+1.2
LSB
The maximum LSB is
over a sub-range not
exceeding 1/16 of the full
scale range.
-1
–
+1
LSB
Output is monatonic.
Note
9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each,
36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no
single block ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before
writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
10. At the 7F and 80 points, the maximum INL is 1.5 LSB.
11. For the 7F to 80 transition, the DNL specification is waived.
Document Number: 001-14643 Rev. *D
Page 22 of 34
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CY8C24533
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. 5V and 3.3V AC Chip-Level Specifications
Description
Min
Typ
FIMO24
Symbol
Internal Main Oscillator
Frequency for 24 MHz
22.8
24
25.2[12],[13],[14] MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 7 on
page 13. SLIMO mode = 0.
FIMO6
Internal Main Oscillator
Frequency for 6 MHz
5.75
6
6.35[12],[13],[14] MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 7 on
page 13. SLIMO mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.093
24
24.6[12],[13]
MHz
12
12.3[13],[14]
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.093
Max
Units
Notes
F48M
Digital PSoC Block Frequency
0
48
49.2[12],[13],[15]
F24M
Digital PSoC Block Frequency
0
24
24.6[13],[15]
MHz
F32K1
Internal Low Speed Oscillator
Frequency
15
32
75
kHz
F32K2
External Crystal Oscillator
–
32.76
8
–
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
FPLL
PLL Frequency
–
23.98
6
–
MHz Is a multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
0.5
–
50
ms
TPLLSLEWSLOW PLL Lock Time for Low Gain
Setting
MHz Refer to the AC Digital Block Specifications.
TOS
External Crystal Oscillator Startup
to 1%
–
1700
2620
ms
TOSACC
External Crystal Oscillator Startup
to 100 ppm
–
2800
3800
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
Fout48M
48 MHz Output Frequency
Jitter24M1R
The crystal oscillator frequency is within
100 ppm of its final value by the end of the
Tosacc period. Correct operation assumes
a properly loaded 1 uW maximum drive
level 32.768 kHz crystal. 3.0V≤ Vdd≤5.5V,
-40°C ≤TA≤ 85°C
ns
–
50
–
46.8
48.0
49.2[12],[14]
kHz
24 MHz Period Jitter (IMO) Root
Mean Squared
–
–
600
ps
FMAX
Maximum frequency of signal on
row input or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
MHz Trimmed. Using factory trim values.
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for
operation at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-14643 Rev. *D
Page 23 of 34
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CY8C24533
Figure 8. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 9. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 10. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 001-14643 Rev. *D
Page 24 of 34
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CY8C24533
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-14643 Rev. *D
TFallF
TFallS
Page 25 of 34
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CY8C24533
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 24. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
–
MHz
MHz
Table 25. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Document Number: 001-14643 Rev. *D
Page 26 of 34
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CY8C24533
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 14. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 15. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-14643 Rev. *D
0.01
0.1
Freq (kHz)
1
10
100
Page 27 of 34
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CY8C24533
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. 5V and 3.3V AC Digital Block Specifications
Symbol
Min
Typ
Max
Units
50[16]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
50[16]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[16]
–
–
ns
Disable Mode
50[16]
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
Timer
Counter
Dead Band
CRCPRS
(PRS Mode)
Description
Capture Pulse Width
Enable Pulse Width
Receiver
4.75V < Vdd < 5.25V
4.75V < Vdd < 5.25V
Kill Pulse Width:
–
–
4.1
MHz
50[16]
–
–
ns
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz
Width of SS_ Negated Between Transmissions
Transmitter
Notes
Maximum data rate at 4.1 MHz
due to 2 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Note
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-14643 Rev. *D
Page 28 of 34
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CY8C24533
AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Table 29. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
Document Number: 001-14643 Rev. *D
Page 29 of 34
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CY8C24533
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Table 31. 3.3V AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU Clock divide by 1[17]
greater[18]
Min
Typ
Max
Units
0.093
–
12.3
MHz
0.186
–
24.6
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
Notes
0
–
8
MHz
TERASEB Flash Erase Time (Block)
–
20
–
ms
TWRITE
Flash Block Write Time
–
20
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
SAR8 ADC AC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. SAR8 ADC AC Specifications
Min
Typ
Max
Units
Freq3
Symbol
Input clock frequency 3V
Description
–
–
3.0
MHz
Freq5
Input clock frequency 5V
–
–
3.0
MHz
Notes
17. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
18. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-14643 Rev. *D
Page 30 of 34
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CY8C24533
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 34. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100
0
400
kHz
4.0
–
0.6
–
μs
FSCLI2C
SCL Clock Frequency
THDSTAI2C
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
–
ns
[19]
TSUDATI2C
Data Setup Time
250
–
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
Table 35. AC Characteristics of the
Symbol
I 2C
100
SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100
–
–
kHz
4.0
–
–
–
μs
FSCLI2C
SCL Clock Frequency
THDSTAI2C
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
4.7
–
–
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
–
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
–
–
μs
THDDATI2C
Data Hold Time
0
–
–
–
μs
TSUDATI2C
Data Setup Time
250
–
–
–
ns
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
–
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
–
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
–
–
ns
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-14643 Rev. *D
Page 31 of 34
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CY8C24533
Packaging Information
This section illustrates the packaging specifications for the CY8C24533 PSoC device, along with the thermal impedances for each
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.
Figure 17. 28-Pin (210-Mil) SSOP
51-85079 *C
Thermal Impedances
Capacitance on Crystal Pins
Table 36. Thermal Impedances by Package
Package
Typical θJA
28 SSOP
95°C/W
[20]
Table 37. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 SSOP
2.8 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 38. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature [21]
Maximum Peak Temperature
28 SSOP
240°C
260°C
Notes
20. TJ = TA + POWER x θJA .
21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 001-14643 Rev. *D
Page 32 of 34
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CY8C24533
Ordering Information
The following table lists the CY8C24533 PSoC device family key package features and ordering codes.
RAM
(Bytes)
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital IO Pins
Analog Inputs
Analog Outputs
XRES Pin
28 Pin (210 Mil) SSOP
CY8C24533-24PVXI
8
256
-40°C to +85°C
4
4
26
12
2
No
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C24533-24PVXIT
8
256
-40°C to +85°C
4
4
26
12
2
No
Package
Ordering
Code
Flash
(Kbytes)
Table 39. CY8C24533 PSoC Device Family Key Features and Ordering Information
Document Number: 001-14643 Rev. *D
Page 33 of 34
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CY8C24533
Document History Page
Document Title: CY8C24533 PSoC® Programmable System-on-Chip™
Document Number: 001-14643
Rev
ECN
Orig. of
Change
Submission
Date
**
998721
VED
See ECN
New spec.
*A
1149184
HMT
See ECN
Update Advance to Preliminary. Update features, pinouts, registers, specs.,
packages, package data, and order information. Convert to new Cypress template.
*B
1411003
HMT
See ECN
Update formatting edits. Split out device. Update registers and electrical specs.
Convert Table Notes to Cypress template style.
*C
1648723
HMT
See ECN
Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune
specs. Make data sheet Final.
*D
2616862 OGNE/AESA
12/05/2008
Description of Change
Changed title to: “CY8C24533 PSoC® Programmable System-on-Chip™”
Changed names of registers on page 10.
"SARADC_C0" to "SARADC_CR0"
"SARADC_C1" to "SARADC_CR1"
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-14643 Rev. *D
Revised December 05, 2008
Page 34 of 34
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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