CYPRESS CYDM064B16

CYDM064B16, CYDM128B16, CYDM256B16
1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL®
Dual-Port Static RAM
Features
■
True dual-ported memory cells that allow simultaneous access
of the same memory location
■
Expandable data bus to 32 bits with Master or Slave chip select
when using more than one device
■
4, 8, or 16K × 16 organization
■
On-chip arbitration logic
■
Ultra Low operating power
❐ Active: ICC = 15 mA (typical) at 55 ns
❐ Standby: ISB3 = 2 μA (typical)
■
Semaphores included to permit software handshaking
between ports
■
Input read registers and output drive registers
■
Small footprint: Available in a 6x6 mm 100-pin Pb-free vfBGA
■
INT flag for port-to-port communication
■
Port independent 1.8V, 2.5V, and 3.0V IOs
■
Separate upper-byte and lower-byte control
■
Full asynchronous operation
■
Industrial temperature ranges
■
Automatic power down
■
Pin select for Master or Slave
Selection Guide for VCC = 1.8V
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
(-55)
Port IO Voltages (P1-P2)
Unit
1.8V -1.8V
V
Maximum Access Time
55
ns
Typical Operating Current
15
mA
Typical Standby Current for ISB1
2
μA
Typical Standby Current for ISB3
2
μA
Selection Guide for VCC = 2.5V
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
(-55)
Port IO Voltages (P1-P2)
Unit
2.5V-2.5V
V
Maximum Access Time
55
ns
Typical Operating Current
28
mA
Typical Standby Current for ISB1
6
μA
Typical Standby Current for ISB3
4
μA
Selection Guide for VCC = 3.0V
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
(-55)
Port IO Voltages (P1-P2)
Unit
3.0V-3.0V
V
Maximum Access Time
55
ns
Typical Operating Current
42
mA
Typical Standby Current for ISB1
7
μA
Typical Standby Current for ISB3
6
μA
Cypress Semiconductor Corporation
Document #: 001-00217 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 31, 2008
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CYDM064B16, CYDM128B16, CYDM256B16
Logic Block Diagram [1, 2]
IO[15:0]R
IO[15:0]L
UBR
UBL
LBL
LBR
IO
Control
IO
Control
16K X 16
Dual Ported Array
Address Decode
Address Decode
A[13:0]L
CE L
A [13:0]R
CE R
Interrupt
Arbitration
Semaphore
OE L
R/W L
SEML
BUSY L
INTL
Mailboxes
CEL
OEL
R/WL
INTR
OE R
R/W R
SEMR
BUSY R
M/S
Input Read
Register and
Output Drive
Register
IRR0 ,IRR1
CE R
OE R
R/W R
ODR0 - ODR4
SFEN
Notes
1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
Document #: 001-00217 Rev. *F
Page 2 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Pinouts
Figure 1. Ball Diagram - 100-Ball 0.5 mm Pitch BGA (Top View) [3, 4, 5, 6, 7]
CYDM064B16, CYDM128B16, CYDM256B16
1
2
3
4
5
6
7
8
9
10
A
A5R
A8R
A11R
UBR
VSS
SEMR
IO15R
IO12R
IO10R
VSS
A
B
A3R
A4R
A7R
A9R
CER
R/WR
OER
VDDIOR
IO9R
IO6R
B
C
A0R
A1R
A2R
A6R
LBR
IRR1[6] IO14R
IO11R
IO7R
VSS
C
ODR4 ODR2 BUSYR INTR
A10R
A12R[3] IO13R
IO8R
IO5R
IO2R
D
IO1R
VSS
E
D
ODR3
INTL
VSS
VSS
IO4R
VDDIOR
F
SFEN ODR1 BUSYL
A1L
VCC
VSS
IO3R
IO0R
IO15L VDDIOL
F
G
ODR0
A2L
A5L
A12L[3]
OEL
IO3L
IO11L
IO12L
IO14L
IO13L
G
H
A0L
A4L
A9L
LBL
CEL
IO1L
VDDIOL NC[7]
NC[7]
IO10L
H
J
A3L
A7L
A10L
IRR0[5]
VCC
VSS
IO4L
IO6L
IO8L
IO9L
J
K
A6L
A8L
A11L
UBL
SEML
R/WL
IO0L
IO2L
IO5L
IO7L
K
1
2
3
4
5
6
7
8
9
10
E
VSS
M/S
Notes
3. A12L and A12R are NC pins for CYDM064B16.
4. IRR functionality is not supported for the CYDM256B16 device.
5. This pin is A13L for CYDM256B16 device.
6. This pin is A13R for CYDM256B16 device.
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document #: 001-00217 Rev. *F
Page 3 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Table 1. Pin Definitions - 100-Ball 0.5 mm Pitch BGA (CYDM064B16, CYDM128B16, CYDM256B16)
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read or Write Enable
OEL
OER
Output Enable
A0L–A13L
A0R–A13R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices)
IO0L–IO15L
IO0R–IO15R
Data Bus Input or Output for x16 devices
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select (IO8–IO15)
LBL
LBR
Lower Byte Select (IO0–IO7)
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
IRR0, IRR1
ODR0-ODR4
SFEN
Input Read Register for CYDM064B16 and CYDM128B16
A13L and A13R for CYDM256B16.
Output Drive Register. These outputs are Open Drain.
Special Function Enable
M/S
Master or Slave Select
VCC
Core Power
GND
Ground
VDDIOL
Left Port IO Voltage
VDDIOR
Right Port IO Voltage
NC
Document #: 001-00217 Rev. *F
No Connect. Leave this pin Unconnected.
Page 4 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Functional Description
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multiprocessor designs, communications status buffering, and
dual-port video or graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V, or 3.0V, as long as it
is lower than or equal to the IO voltage.
Each port can operate on independent IO voltages. This is
determined by what is connected to the VDDIOL and VDDIOR pins.
The supported IO standards are 1.8V or 2.5V LVCMOS and 3.0V
LVTTL.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the
CYDM256B16) is the mailbox for the right port and the
second-highest memory location (FFE for the CYDM064B16,
1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program must be run and
the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy are
summarized in Table 3 on page 7.
Busy
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (contention). If both port CEs are asserted and an
address match occurs within tPS of each other, the busy logic
determines which port has access. If tPS is violated, one port
definitely gains permission to the location. However, which port
gets this permission cannot be predicted. BUSY is asserted tBLA
after an address match or tBLC after CE is taken LOW.
Write Operation
Master/Slave
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 5 on page 18) or the CE pin
(see Figure 6 on page 18). Required inputs for noncontention
operations are summarized in Table 2 on page 7.
An M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, as a result, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output. Otherwise, the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Document #: 001-00217 Rev. *F
Page 5 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits and
DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is available
for memory accesses.
The inputs are 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending
on the core voltage supply (VCC). Refer to Table 4 on page 8 for
Input Read Register operation.
IRR is not available in the CYDM256B16, because the IRR pins
are used as extra address pins A13L and A13R.
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages (1.5V
≤ VDDIO ≤ 3.5V) but the combined current cannot exceed 40 mA
(8 mA max for each external device). The status of the ODR bits
are set using standard write accesses from either port to address
x0001 with a “1” corresponding to on and “0” corresponding to
off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses. When
SFEN = VIH, the ODR is inactive and address x0001 can be used
for standard accesses.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 5 on page 8 for Output
Drive Register operation.
Semaphore Operation
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
eight semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port is successful (reads a zero), it assumes
control of the shared resource. Otherwise (reads a one), it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Document #: 001-00217 Rev. *F
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port requests the semaphore
(written a zero) while the left port has control, the right port
immediately owns the semaphore as soon as the left port
releases it. Table 6 on page 8 shows sample semaphore
operations.
When reading a semaphore, all sixteen data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore. On power up, both ports must write
“1” to all eight semaphores.
Architecture
The CYDM256B16, CYDM128B16, and CYDM064B16 consist
of an array of 4K, 8K, or 16K words of 16 dual-port RAM cells,
IO and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes or reads to
the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be used for port-to-port communication.
Two Semaphore (SEM) control pins are used to allocate shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the
device.
Page 6 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Table 2. NonContending Read/Write
Inputs
Outputs
UB
LB
IO8–IO15
SEM
Operation
IO0–IO7
CE
R/W
OE
H
X
X
X
X
H
High Z
High Z
Deselected: Power down
X
X
X
H
H
H
High Z
High Z
Deselected: Power down
L
L
X
L
H
H
Data In
High Z
Write to Upper Byte Only
L
L
X
H
L
H
High Z
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
High Z
Read Upper Byte Only
L
H
L
H
L
H
High Z
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 3. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[8]
Left Port
Function
R/WL
CEL
Right Port
OEL
A0L–13L
INTL
R/WR
CER
OER
A0R–13R
INTR
X
X
X
X
X
L[10]
Set Right INTR Flag
L
L
X
3FFF[11]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
3FFF[11]
H[9]
Set Left INTL Flag
X
X
X
X
L[9]
L
L
X
3FFE[11]
X
Reset Left INTL Flag
X
L
L
3FFE[11]
H[10]
X
X
X
X
X
Notes
8. See Interrupts Functional Description for specific highest memory locations by device.
9. If BUSYR = L, then no change.
10. If BUSYL = L, then no change.
11. See section Functional Description on page 5 for specific addresses by device.
Document #: 001-00217 Rev. *F
Page 7 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Table 4. Input Read Register Operation[12, 15]
SFEN
H
L
CE
L
L
R/W
OE
H
L
H
L
UB
LB
L
L
ADDR
IO0–IO1
[13]
x0000-Max VALID
X
L
x0000
ADDR
[14]
VALID
IO2–IO15
[13]
VALID
X
Mode
Standard Memory Access
IRR Read
Table 5. Output Drive Register [16]
SFEN
CE
R/W
OE
UB
LB
IO0–IO4
IO5–IO15
Mode
H
L
H
X[17]
L[13]
L[13]
L
L
L
X
X
L
x0001
VALID[14]
X
ODR Write[16, 18]
L
L
H
L
X
L
x0001
VALID[14]
X
ODR Read[16]
x0000-Max VALID[13] VALID[13] Standard Memory Access
Table 6. Semaphore Operation Example
Function
IO0–IO15 Left
IO0–IO15 Right
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access
to semaphore.
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access
to semaphore.
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
No action
Status
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Notes
12. SFEN = VIL for IRR reads
13. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
14. LB must be active (LB = VIL) for these bits to be valid.
15. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
16. SFEN = VIL for ODR reads and writes.
17. Output enable must be low (OE = VIL) during reads for valid data to be output.
18. During ODR writes data are also written to the memory.
Document #: 001-00217 Rev. *F
Page 8 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Maximum Ratings
Static Discharge Voltage .......................................... > 2000V
Latch-up Current ................................................... > 200 mA
Exceeding maximum ratings[19] may shorten the useful life of the
device. User guidelines are not tested.
Operating Range
Storage Temperature ................................. –65°C to +150°C
Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Commercial
Ambient Temperature
VCC
0°C to +70°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
–40°C to +85°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Supply Voltage to Ground Potential ............... –0.5V to +3.3V
Industrial
DC Voltage Applied to
Outputs in High-Z State.......................... –0.5V to VCC + 0.5V
DC Input Voltage[20] ...............................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW) .............................90 mA
Electrical Characteristics for VCC = 1.8V
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
VOH
VOL
VOL ODR
VIH
VIL
IOZ
ICEX ODR
IIX
Description
-55
Unit
P1 IO Voltage P2 IO Voltage
Min
Output HIGH Voltage (IOH = –100 μA)
1.8V (any port)
VDDIO – 0.2
V
Output HIGH Voltage (IOH = –2 mA)
2.5V (any port)
2.0
V
Output HIGH Voltage (IOH = –2 mA)
3.0V (any port)
2.1
Output LOW Voltage (IOL = 100 μA)
1.8V (any port)
0.2
V
Output HIGH Voltage (IOL = 2 mA)
2.5V (any port)
0.4
V
Output HIGH Voltage (IOL = 2 mA)
3.0V (any port)
0.4
V
ODR Output LOW Voltage (IOL = 8 mA)
1.8V (any port)
0.2
V
2.5V (any port)
0.2
V
3.0V (any port)
0.2
V
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
ODR Output Leakage Current.
VOUT = VDDIO
Input Leakage Current
Typ.
Max
V
1.8V (any port)
1.2
VDDIO + 0.2
V
2.5V (any port)
1.7
VDDIO + 0.3
V
3.0V (any port)
2.0
VDDIO + 0.2
V
1.8V (any port)
–0.2
0.4
V
2.5V (any port)
–0.3
0.6
V
3.0V (any port)
–0.2
0.7
V
1.8V
1.8V
–1
1
μA
2.5V
2.5V
–1
1
μA
3.0V
3.0V
–1
1
μA
1.8V
1.8V
–1
1
μA
2.5V
2.5V
–1
1
μA
3.0V
3.0V
–1
1
μA
1.8V
1.8V
–1
1
μA
2.5V
2.5V
–1
1
μA
3.0V
3.0V
–1
1
μA
Notes
19. The voltage on any input or IO pin can not exceed the power pin during power up.
20. Pulse width < 20 ns.
Document #: 001-00217 Rev. *F
Page 9 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for VCC = 1.8V
(continued)
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
P1 IO Voltage P2 IO Voltage
Unit
Min
Typ.
Max
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind.
1.8V
1.8V
15
25
mA
ISB1
Standby Current (Both Ports TTL
Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
1.8V
1.8V
2
6
μA
ISB2
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind.
1.8V
1.8V
8.5
14
mA
ISB3
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
1.8V
1.8V
2
6
μA
ISB4
Standby Current (One Port CMOS Ind.
Level) CEL | CER ≥ VIH, f = fMAX[21]
1.8V
1.8V
8.5
14
mA
Electrical Characteristics for VCC = 2.5V
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Unit
P1 IO Voltage P2 IO Voltage
Min
VOH
Output HIGH Voltage (IOH = –2 mA)
2.5V (any port)
2.0
Typ.
3.0V (any port)
2.1
VOL
Output LOW Voltage (IOL = 2 mA)
2.5V (any port)
0.4
V
3.0V (any port)
0.4
V
VOL ODR
ODR Output LOW Voltage (IOL = 8 mA)
2.5V (any port)
0.2
V
VIH
Input HIGH Voltage
2.5V (any port)
VIL
Input LOW Voltage
3.0V (any port)
IOZ
Output Leakage Current
2.5V
3.0V
3.0V
ICEX ODR
ODR Output Leakage Current.
VOUT = VCC
2.5V
2.5V
3.0V
3.0V
IIX
Input Leakage Current
2.5V
2.5V
3.0V
3.0V
–1
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
2.5V
2.5V
V
V
3.0V (any port)
Ind.
Max
0.2
V
1.7
VDDIO + 0.3
V
3.0V (any port)
2.0
VDDIO + 0.2
V
2.5V (any port)
–0.3
0.6
V
–0.2
0.7
V
–1
1
μA
–1
1
μA
–1
1
μA
–1
1
μA
–1
1
μA
2.5V
28
1
μA
40
mA
Notes
21. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document #: 001-00217 Rev. *F
Page 10 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for VCC = 2.5V
(continued)
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
P1 IO Voltage P2 IO Voltage
Unit
Min
Typ.
Max
ISB1
Standby Current (Both Ports TTL
Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML= SEMR = VCC – 0.2, f = fMAX
2.5V
2.5V
6
8
μA
ISB2
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind.
2.5V
2.5V
18
25
mA
ISB3
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
2.5V
2.5V
4
6
μA
ISB4
Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX[21]
2.5V
2.5V
18
25
mA
Ind.
Electrical Characteristics for 3.0V Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Unit
P1 IO Voltage P2 IO Voltage
Min
2.1
VOH
Output HIGH Voltage (IOH = –2 mA)
3.0V (any port)
VOL
Output LOW Voltage (IOL = 2 mA)
3.0V (any port)
Typ.
Max
V
0.4
V
VOL ODR
ODR Output LOW Voltage (IOL = 8 mA)
3.0V (any port)
0.2
V
VIH
Input HIGH Voltage
3.0V (any port)
2.0
VDDIO + 0.2
V
3.0V (any port)
VIL
Input LOW Voltage
–0.2
0.7
V
IOZ
Output Leakage Current
3.0V
3.0V
–1
1
μA
ICEX ODR
ODR Output Leakage Current.
VOUT = VCC
3.0V
3.0V
–1
1
μA
IIX
Input Leakage Current
3.0V
3.0V
–1
1
μA
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind.
3.0V
3.0V
42
60
mA
ISB1
Standby Current (Both Ports TTL
Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
3.0V
3.0V
7
10
μA
ISB2
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind.
3.0V
3.0V
25
35
mA
ISB3
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
3.0V
3.0V
6
8
μA
ISB4
Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX[21]
3.0V
3.0V
25
35
mA
Max
Unit
9
pF
10
pF
Ind.
Capacitance[22]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Note
22. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00217 Rev. *F
Page 11 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
AC Test Loads and Waveforms
3.0V/2.5V/1.8V
3.0V/2.5V/1.8V
R1
RTH = 6 kΩ
OUTPUT
OUTPUT
R1
OUTPUT
C = 30 pF
C = 30 pF
R2
C = 5 pF
R2
VTH = 0.8V
(a) Normal Load
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
ALL INPUT PULSES
3.0V/2.5V
1.8V
R1
1022Ω
13500Ω
1.8V
R2
792Ω
10800Ω
GND
10%
≤ 3 ns
90%
90%
10%
≤ 3 ns
Switching Characteristics for VCC = 1.8V
Over the Operating Range[23]
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
Unit
Max
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[24]
CE LOW to Data Valid
55
ns
tDOE
OE LOW to Data Valid
30
ns
tLZOE
[25, 26, 27]
tHZOE[25, 26, 27]
tLZCE[25, 26, 27]
tHZCE[25, 26, 27]
tPU[27]
tPD[27]
tABE[24]
OE Low to Low Z
55
55
5
CE LOW to Power up
ns
25
5
CE HIGH to High Z
ns
ns
5
OE HIGH to High Z
CE LOW to Low Z
ns
ns
ns
25
0
ns
ns
CE HIGH to Power down
55
ns
Byte Enable Access Time
55
ns
Notes
23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
24. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
25. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
26. Test conditions used are Load 3.
27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
waveform.
Document #: 001-00217 Rev. *F
Page 12 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 1.8V
(continued)
Over the Operating Range[23]
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
Unit
Max
Write Cycle
tWC
Write Cycle Time
55
ns
tSCE[24]
CE LOW to Write End
45
ns
tAW
Address Valid to Write End
45
ns
tHA
Address Hold From Write End
0
ns
tSA[24]
Address Setup to Write Start
0
ns
tPWE
Write Pulse Width
40
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold From Write End
0
ns
tHZWE[26, 27]
tLZWE[26, 27]
tWDD[28]
tDDD[28]
R/W LOW to High Z
Busy Timing
R/W HIGH to Low Z
25
0
ns
ns
Write Pulse to Data Delay
80
ns
Write Data Valid to Read Data Valid
80
ns
[29]
tBLA
BUSY LOW from Address Match
45
ns
tBHA
BUSY HIGH from Address Mismatch
45
ns
tBLC
BUSY LOW from CE LOW
45
ns
tBHC
BUSY HIGH from CE HIGH
45
ns
tPS[30]
Port Setup for Priority
tWB
tWH
tBDD[31]
5
ns
R/W HIGH after BUSY (Slave)
0
ns
R/W HIGH after BUSY HIGH (Slave)
35
ns
BUSY HIGH to Data Valid
40
ns
tINS
INT Set Time
45
ns
tINR
INT Reset Time
45
ns
[29]
Interrupt Timing
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
15
ns
tSWRD
SEM Flag Write to Read Time
10
ns
tSPS
SEM Flag Contention Window
10
ns
tSAA
SEM Address Access Time
55
ns
Notes
28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
29. Test conditions used are Load 2.
30. Add 2ns to this parameter if VCC and VDDIOR are <1.8V, and VDDIOL is >2.5V at temperature <0°C.
31. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
Document #: 001-00217 Rev. *F
Page 13 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 2.5V
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
Unit
Max
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[24]
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
[25, 26, 27]
OE Low to Low Z
55
ns
55
5
ns
ns
55
30
2
ns
ns
ns
tHZOE[25, 26, 27]
OE HIGH to High Z
tLZCE[25, 26, 27]
CE LOW to Low Z
tHZCE[25, 26, 27]
CE HIGH to High Z
tPU[27]
CE LOW to Power up
tPD[27]
CE HIGH to Power down
55
ns
tABE[24]
Byte Enable Access Time
55
ns
25
2
ns
ns
25
0
ns
ns
Write Cycle
tWC
Write Cycle Time
55
ns
tSCE[24]
CE LOW to Write End
45
ns
tAW
Address Valid to Write End
45
ns
tHA
Address Hold From Write End
0
ns
tSA[24]
Address Setup to Write Start
0
ns
tPWE
Write Pulse Width
40
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold From Write End
0
ns
tHZWE[26, 27]
tLZWE[26, 27]
tWDD[28]
tDDD[28]
R/W LOW to High Z
R/W HIGH to Low Z
25
0
ns
ns
Write Pulse to Data Delay
80
ns
Write Data Valid to Read Data Valid
80
ns
tBLA
BUSY LOW from Address Match
45
ns
tBHA
BUSY HIGH from Address Mismatch
45
ns
tBLC
BUSY LOW from CE LOW
45
ns
tBHC
BUSY HIGH from CE HIGH
45
ns
tPS[30]
Port Setup for Priority
Busy Timing
[29]
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
35
ns
tBDD[31]
BUSY HIGH to Data Valid
Document #: 001-00217 Rev. *F
40
ns
Page 14 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 2.5V
(continued)
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
Interrupt
Unit
Max
Timing[29]
tINS
INT Set Time
45
ns
tINR
INT Reset Time
45
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
15
ns
tSWRD
SEM Flag Write to Read Time
10
ns
tSPS
SEM Flag Contention Window
10
ns
tSAA
SEM Address Access Time
55
ns
Switching Characteristics for VCC = 3.0V
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
Unit
Max
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[24]
CE LOW to Data Valid
55
ns
tDOE
OE LOW to Data Valid
30
ns
tLZOE
[25, 26, 27]
tHZOE[25, 26, 27]
tLZCE[25, 26, 27]
tHZCE[25, 26, 27]
tPU[27]
tPD[27]
tABE[24]
OE Low to Low Z
55
55
5
CE LOW to Power up
ns
25
1
CE HIGH to High Z
ns
ns
1
OE HIGH to High Z
CE LOW to Low Z
ns
ns
ns
25
0
ns
ns
CE HIGH to Power down
55
ns
Byte Enable Access Time
55
ns
Write Cycle
tWC
Write Cycle Time
55
ns
tSCE[24]
CE LOW to Write End
45
ns
tAW
Address Valid to Write End
45
ns
tHA
Address Hold From Write End
0
ns
tSA[24]
Address Setup to Write Start
0
ns
tPWE
Write Pulse Width
40
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold From Write End
0
ns
Document #: 001-00217 Rev. *F
Page 15 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 3.0V
(continued)
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Min
tHZWE[26, 27]
tLZWE[26, 27]
tWDD[28]
tDDD[28]
Busy
R/W LOW to High Z
R/W HIGH to Low Z
Unit
Max
25
0
ns
ns
Write Pulse to Data Delay
80
ns
Write Data Valid to Read Data Valid
80
ns
Timing[29]
tBLA
BUSY LOW from Address Match
45
ns
tBHA
BUSY HIGH from Address Mismatch
45
ns
tBLC
BUSY LOW from CE LOW
45
ns
tBHC
BUSY HIGH from CE HIGH
45
ns
tPS[30]
Port Setup for Priority
tWB
tWH
tBDD[31]
5
ns
R/W HIGH after BUSY (Slave)
0
ns
R/W HIGH after BUSY HIGH (Slave)
35
ns
BUSY HIGH to Data Valid
40
ns
tINS
INT Set Time
45
ns
tINR
INT Reset Time
45
ns
Interrupt
Timing[29]
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
15
ns
tSWRD
SEM Flag Write to Read Time
10
ns
tSPS
SEM Flag Contention Window
10
ns
tSAA
SEM Address Access Time
Document #: 001-00217 Rev. *F
55
ns
Page 16 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms
Figure 2. Read Cycle No.1 (Either Port Address Access) [32, 33, 34]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle No.2 (Either Port CE/OE Access) [32, 35, 36]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 4. Read Cycle No. 3 (Either Port) [32, 34, 37, 38]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
32. R/W is HIGH for read cycles.
33. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
34. OE = VIL.
35. Address valid before or coincident with CE transition LOW.
36. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
37. R/W must be HIGH during all address transitions.
38. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
Document #: 001-00217 Rev. *F
Page 17 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 5. Write Cycle No.1: R/W Controlled Timing [37, 38, 39, 40, 41, 42]
tWC
ADDRESS
tHZOE [43]
OE
tAW
CE
[41, 42]
tPWE[40]
tSA
tHA
R/W
tHZWE[43]
DATA OUT
tLZWE
NOTE 44
NOTE 44
tSD
tHD
DATA IN
Figure 6. Write Cycle No. 2: CE Controlled Timing [37, 38, 39, 44]
tWC
ADDRESS
tAW
CE
[41, 42]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
39. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
40. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the IO drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tPWE.
41. To access RAM, CE = VIL, SEM = VIH.
42. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
43. Transition is measured ±0 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
44. During this period, the IO pins are in the output state, and input signals must not be applied.
Document #: 001-00217 Rev. *F
Page 18 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 7. Semaphore Read After Write Timing (Either Side) [45, 46]
tSAA
A0–A2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
IO0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 8. Timing Diagram of Semaphore Contention [47, 48]
A0L–A2L
MATCH
R/WL
SEML
tSPS
A0R–A2R
MATCH
R/WR
SEMR
Notes
45. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
46. CE = HIGH for the duration of the above timing (both write and read cycle).
47. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH.
48. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but the side that gets the semaphore cannot be predicted.
Document #: 001-00217 Rev. *F
Page 19 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 9. Timing Diagram of Read with BUSY (M/S = HIGH) [49]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATAOUTL
VALID
tWDD
Figure 10. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
49. CEL = CER = LOW.
Document #: 001-00217 Rev. *F
Page 20 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 11. Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First[50]
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Figure 12. Busy Timing Diagram No.2 (Address Arbitration) [50]
Left Address Valid First
tRC or tWC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSYR
Right Address Valid First
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Note
50. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY iS asserted.
Document #: 001-00217 Rev. *F
Page 21 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 13. Interrupt Timing Diagrams
Left Side Sets INTR
ADDRESSL
tWC
WRITE 1FFF (OR 1/3FFF)
tHA[51]
CEL
R/WL
INTR
tINS [52]
Right Side Clears INTR
tRC
READ 1FFF
(OR 1/3FFF)
ADDRESSR
CER
tINR [52]
R/WR
OER
INTR
Right Side Sets INTL
tWC
ADDRESSR
WRITE 1FFE (OR 1/3FFE)
tHA[51]
CER
R/WR
INTL
[52]
tINS
Left Side Clears INTL
tRC
READ 1FFE
OR 1/3FFE)
ADDRESSL
CEL
tINR[52]
R/WL
OEL
INTL
Notes
51. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
52. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 001-00217 Rev. *F
Page 22 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Ordering Information
Table 7. 16K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
55
CYDM256B16-55BVXC
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Package Type
Commercial
Operating Range
55
CYDM256B16-55BVXI
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Industrial
Table 8. 8K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
55
CYDM128B16-55BVXC
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Package Type
Commercial
Operating Range
55
CYDM128B16-55BVXI
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Industrial
Table 9. 4K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
55
CYDM064B16-55BVXC
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Commercial
55
CYDM064B16-55BVXI
BZ100
100-ball Pb-free 0.5 mm Pitch BGA
Industrial
Package Diagram
Figure 14. 100 VFBGA (6 x 6 x 1.0 mm) BZ100A
"/44/-6)%7
4/06)%7
!#/2.%2
Œ-#
Œ-#!"
!#/2.%2
Œ¼8
!
"
!
"
#
$
%
&
'
(
*
+
¼
¼
!
!
"
#
$
%
&
'
(
*
+
¼
"
¼
#
¼
2%&
#
8
2%&%2%.#%*%$%#-/#
0+'7%)'(44"$.%70+'
3%!4).'0,!.%
Document #: 001-00217 Rev. *F
-!8
2%&
#
51-85209 *B
Page 23 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Document History Page
Document Title: CYDM064B16, CYDM128B16, CYDM256B16 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM
Document Number: 001-00217
REV.
ECN NO.
Orig. of
Change
Submission
Date
Description of Change
**
369423
YDT
New data sheet
*A
381721
YDT
Updated 2.5V/3.0V ICC, ISB1, ISB2, ISB4
Updated VOL ODR to 0.2V
*B
396697
KGH
Updated ISB2 and ISB4 typo to mA.
Updated tINS and tINR for -55 to 31ns.
*C
404777
KGH
Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
VOL
Replaced -35 speed bin with -40
Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
Included note 35
*D
426637
KGH
Removed part numbers CYDM128B08 and CYDM064B08
*E
733676
HKH
Corrected typo for power supply description in page 4 (3.0V instead of 3.3V)
Updated tDDD timing value to be consistent with tWDD
*F
2545957
OGC/AESA
07/31/2008
Removed all details of -40ns parts. Updated data sheet template.
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Document #: 001-00217 Rev. *F
Revised July 31, 2008
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