DAC ® DAC7614 761 4 DAC 761 4 Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● LOW POWER: 20mW ● ATE PIN ELECTRONICS ● UNIPOLAR OR BIPOLAR OPERATION ● SETTLING TIME: 10µs to 0.012% ● PROCESS CONTROL ● CLOSED-LOOP SERVO-CONTROL ● 12-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● USER SELECTABLE RESET TO MIDSCALE OR ZERO-SCALE ● SECOND-SOURCE for DAC8420 ● SMALL 20-LEAD SSOP PACKAGE DESCRIPTION The DAC7614 is a quad, serial input, 12-bit, voltage output digital-to-analog converter (DAC) with guaranteed 12-bit monotonic performance over the –40°C to +85°C temperature range. An asynchronous reset clears all registers to either mid-scale (800H) or zeroscale (000H), selectable via the RESETSEL pin. The device can be powered from a single +5V supply or from dual +5V and –5V supplies. Low power and small size makes the DAC7614 ideal for process control, data acquisition systems, and closed-loop servo-control. The device is available in 16-pin plastic DIP, 16-lead SOIC, or 20-lead SSOP packages, and is guaranteed over the –40°C to +85°C temperature range. VDD GND VREFH DAC Register A DAC A DAC Register B DAC B DAC Register C DAC C DAC Register D DAC D VOUTA SDI Serial-toParallel Shift Register CLK CS DAC Select LOADDACS VOUTB 12 RESET RESETSEL VOUTC VOUTD VREFL VSS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1445C Printed in U.S.A. December, 1998 SPECIFICATIONS At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted. DAC7614E, P, U PARAMETER CONDITIONS MIN TYP DAC7614EB, PB, UB MAX MIN TYP MAX UNITS ACCURACY Linearity Error(1) Linearity Matching(3) Differential Linearity Error VSS = 0V or –5V ±2 ±1 LSB(2) VSS = 0V or –5V ±2 ±1 LSB VSS = 0V or –5V ±1 ±1 LSB ✻ LSB Monotonicity ✻ 12 Zero-Scale Error Zero-Scale Drift 2 Code = FFFH Full-Scale Matching(3) Zero-Scale Error Code = 00AH, VSS = 0V Zero-Scale Drift VSS = 0V Zero-Scale Matching(3) Full-Scale Error Full-Scale Matching(3) ✻ ppm/°C ±2 ✻ ±1 LSB ±4 ✻ LSB ±2 ±1 LSB 5 Zero-Scale Matching(3) Full-Scale Error Bits ±4 Code = 000H ±8 5 ✻ 10 ✻ LSB ✻ ppm/°C LSB VSS = 0V ±4 ±2 Code = FFFH, VSS = 0V ±8 ✻ LSB VSS = 0V ±4 ±2 LSB Power Supply Rejection ✻ 30 ppm/V ANALOG OUTPUT Voltage Output(4) VSS = 0V or –5V Output Current VREFL VREFH ✻ ✻ V –1.25 +1.25 ✻ ✻ mA 100 ✻ pF Short-Circuit Current +5, –15 ✻ mA Short-Circuit Duration Indefinite ✻ Load Capacitance No Oscillation REFERENCE INPUT VREFH Input Range VSS = 0V or –5V VREFL+1.25 +2.5 ✻ ✻ V VREFL Input Range VSS = 0V 0 VREFH–1.25 ✻ ✻ V VREFL Input Range VSS = –5V –2.5 VREFH–1.25 ✻ ✻ V DYNAMIC PERFORMANCE To ±0.012% Settling Time(5) Channel-to-Channel Crosstalk 5 Full-Scale Step ✻ 10 ✻ µs 0.1 ✻ LSB 40 ✻ nV/√Hz On Any Other DAC, RL = 2kΩ Output Noise Voltage Bandwidth: 0Hz to 1MHz DIGITAL INPUT/OUTPUT Logic Family ✻ TTL-Compatible CMOS Logic Levels VIH | IIH | ≤ 10µA 2.4 VDD+0.3 ✻ ✻ V VIL | IIL | ≤ 10µA –0.3 0.8 ✻ ✻ V V Data Format ✻ Straight Binary POWER SUPPLY REQUIREMENTS VDD If VSS ≠ 0V VSS 4.75 5.25 ✻ ✻ –5.25 –4.75 ✻ ✻ V ✻ mA IDD 1.5 ISS –2.1 Power Dissipation ✻ 1.9 ✻ –1.6 ✻ mA VSS = –5V 15 20 ✻ ✻ mW VSS = 0V 7.5 10 ✻ ✻ mW ✻ °C TEMPERATURE RANGE Specified Performance –40 +85 ✻ ✻ Specification same as grade to the left. NOTES: (1) If VSS = 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with VREFH equal to +2.5V and VREFL equal to –2.5V, one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) If VSS = –5V, full-scale step from code 000H to FFF H or vice-versa. If VSS = 0V, full-scale positive step from code 000H to FFFH and negative step from code FFFH to 00AH . The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7614 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to VSS ........................................................................... –0.3V to +11V VDD to GND ........................................................................ –0.3V to +5.5V VREFL to VSS ............................................................... –0.3V to (VDD – VSS) VDD to VREFH .............................................................. –0.3V to (VDD – VSS) VREFH to VREFL ............................................................ –0.3V to (VDD – VSS) Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MAXIMUM LINEARITY ERROR (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) DAC7614P DAC7614PB ±2 ±1 DAC7614U PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) SPECIFICATION TEMPERATURE RANGE ±1 16-Pin DIP 180 –40°C to +85°C " " " " ±2 ±1 16-Lead SOIC 211 –40°C to +85°C " " " " " " DAC7614UB ±1 ±1 16-Lead SOIC 211 –40°C to +85°C " " " " " " ±2 ±1 20-Lead SSOP 334 –40°C to +85°C " " " " " DAC7614E " DAC7614EB ±1 ±1 20-Lead SSOP 334 –40°C to +85°C " " " " " " ORDERING NUMBER(2) TRANSPORT MEDIA DAC7614P DAC7614PB Rails Rails DAC7614U DAC7614U/1K DAC7614UB DAC7614UB/1K Rails Tape and Reel Rails Tape and Reel DAC7614E DAC7614E/1K DAC7614EB DAC7614EB/1K Rails Tape and Reel Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7614EB/1K” will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 DAC7614 PIN CONFIGURATION—P, U Packages Top View PIN CONFIGURATION—E Package Top View PDIP, SOIC VDD 1 16 RESETSEL VOUTD 2 15 VOUTC 3 VREFL 4 DAC7614P, U VDD 1 20 RESETSEL RESET VOUTD 2 19 RESET 14 LOADDACS VOUTC 3 18 LOADDACS 13 NIC VREFL 4 17 NIC 12 CS NIC 5 16 NIC VREFH 5 VOUTB 6 11 CLK NIC 6 15 NIC VOUTA 7 10 SDI VREFH 7 14 CS VSS 8 9 GND VOUTB 8 13 CLK VOUTA 9 12 SDI VSS 10 11 GND DAC7614E PIN DESCRIPTIONS—P, U Packages PIN SSOP LABEL PIN DESCRIPTIONS—E Package DESCRIPTION PIN LABEL DESCRIPTION 1 VDD Positive Analog Supply Voltage, +5V nominal. 1 VDD 2 VOUTD DAC D Voltage Output 2 VOUTD DAC D Voltage Output 3 VOUTC DAC C Voltage Output 3 VOUTC DAC C Voltage Output 4 VREFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. 4 VREFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. 5 VREFH Reference Input Voltage High. Sets maximum output voltage for all DACs. 5 NIC 6 NIC 7 VREFH Reference Input Voltage High. Sets maximum output voltage for all DACs. 8 VOUTB DAC B Voltage Output. 9 VOUTA DAC A Voltage Output. 10 VSS 6 VOUTB DAC B Voltage Output 7 VOUTA DAC A Voltage Output 8 VSS Negative Analog Supply Voltage, 0V or –5V nominal. Positive Analog Supply Voltage, +5V nominal. Not Internally Connected. Not Internally Connected. 9 GND Ground 10 SDI Serial Data Input 11 CLK Serial Data Clock 11 GND 12 CS Chip Select Input 12 SDI Serial Data Input 13 NIC Not Internally Connected. 13 CLK Serial Data Clock 14 LOADDACS The selected DAC register becomes transparent when LOADDACS is LOW. It is in the latched state when LOADDACS is HIGH. 14 CS Chip Select Input 15 NIC Not Internally Connected. 16 NIC Not Internally Connected. 17 NIC Not Internally Connected. 18 LOADDACS The selected DAC register becomes transparent when LOADDACS is LOW. It is in the latched state when LOADDACS is HIGH. 19 RESET Asynchronous Reset Input. Sets all DAC registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. 20 RESETSEL When LOW, a LOW on RESET will cause all DAC registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. 15 16 RESET Asynchronous Reset Input. Sets all DAC registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. RESETSEL When LOW, a LOW on RESET will cause all DAC registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. ® DAC7614 4 Negative Analog Supply Voltage, 0V or –5V nominal. Ground TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B) 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H E00H 0.00 –0.25 600H 800H A00H C00H E00H FFFH LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.25 0.00 –0.25 0.00 –0.25 –0.50 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H 0.25 0.00 –0.25 –0.50 000H A00H C00H E00H FFFH 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC B, –40°C and +85°C) 0.50 0.50 LE (LSB) +85°C 0.00 –0.25 0.25 +85°C 0.00 –0.25 –0.50 –0.50 0.50 0.50 –40°C LE (LSB) 0.25 400H Digital Input Code 0.50 0.25 200H Digital Input Code 0.50 –0.50 000H LE (LSB) 0.25 –0.50 000H FFFH DLE (LSB) DLE (LSB) LE (LSB) –0.50 000H LE (LSB) 0.00 –0.25 –0.50 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) 0.00 –0.25 –0.50 000H 200H 400H 600H 800H 0.25 –40°C 0.00 –0.25 –0.50 000H A00H C00H E00H FFFH 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code ® 5 DAC7614 TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT) At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC D, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) 0.50 +85°C 0.00 –0.25 0.00 –0.25 0.50 0.50 –40°C LE (LSB) LE (LSB) +85°C –0.50 –0.50 0.25 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H C00H E00H 0.25 –40°C 0.00 –0.25 –0.50 000H FFFH 200H 400H 600H A: Output Voltage (V) 1.75 5V 6 LOADDACS 0V 3 B A 1.25 0 0.75 –3 0.25 –6 –0.25 –9 –2 –1 0 1 2 3 4 5 6 7 8 2.75 9 2.25 6 3 1.75 A 0 1.25 B 5V 0.75 –3 LOADDACS 0V 0.25 –6 –0.25 –9 –2 Time (µs) –1 0 1 2 3 Time (µs) ® DAC7614 A00H C00H E00H FFFH NEGATIVE SLEW RATE and SETTLING TIME A: Output Voltage (V) 9 B: Output Voltage, Deviation from +2.5V (LSB) POSITIVE SLEW RATE and SETTLING TIME 2.75 2.25 800H Digital Input Code Digital Input Code 6 4 5 6 7 8 B: Output Voltage, Deviation from Code 00AH (LSB) 0.25 LE (LSB) LE (LSB) 0.50 TYPICAL PERFORMANCE CURVES: VSS = –5V At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B) 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H 0.00 –0.25 600H 800H A00H C00H E00H FFFH LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.50 0.00 –0.25 0.00 –0.25 –0.50 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H 0.25 0.00 –0.25 –0.50 000H A00H C00H E00H FFFH 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC B, –40°C and +85°C) 0.50 0.50 LE (LSB) +85°C 0.00 –0.25 0.25 +85°C 0.00 –0.25 –0.50 –0.50 0.50 0.50 –40°C LE (LSB) 0.25 400H Digital Input Code 0.25 0.25 200H Digital Input Code 0.50 –0.50 000H LE (LSB) 0.25 –0.50 000H A00H C00H E00H FFFH DLE (LSB) DLE (LSB) LE (LSB) –0.50 000H LE (LSB) 0.00 –0.25 –0.50 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR and DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H C00H E00H 0.25 –40°C 0.00 –0.25 –0.50 000H FFFH 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code ® 7 DAC7614 TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT) At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and V REFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC D, –40˚C and +85˚C) 0.50 +85°C 0.00 –0.25 –0.50 0.00 –0.25 0.50 –40°C LE (LSB) LE (LSB) +85˚C –0.50 0.50 0.25 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H C00H E00H 0.25 –40˚C 0.00 –0.25 –0.50 000H FFFH 200H 400H 600H Digital Input Code 5V A: Output Voltage (V) 4 LOADDACS 0V 1 2 A 0 0 B –1 –2 –2 –4 –3 –6 –1 0 1 2 3 4 5 6 7 8 3 6 2 4 1 A 2 B 0 0 5V –1 –2 LOADDACS 0V –2 –4 –3 –6 –2 –1 0 1 2 3 4 5 Time (µs) Time (µs) VREFH CURRENT vs CODE (All DACs Set to Indicated Code) VREFL CURRENT vs CODE (All DACs Set to Indicated Code) 600 0 500 –100 VREL Current (µA) VREH Current (µA) –2 A00H C00H E00H FFFH NEGATIVE SLEW RATE and SETTLING TIME A: Output Voltage (V) 6 B: Output Voltage, Deviation from +2.5V (LSB) POSITIVE SLEW RATE and SETTLING TIME 3 2 800H Digital Input Code 400 300 200 100 6 7 8 –200 –300 –400 –500 0 000H 400H 800H C00H –600 000H FFFH Digital Input Code 800H Digital Input Code ® DAC7614 400H 8 C00H FFFH B: Output Voltage, Deviation from –2.5V (LSB) 0.25 LE (LSB) LE (LSB) 0.50 THEORY OF OPERATION ANALOG OUTPUTS When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, over the –40°C to +85°C temperature range. With VSS = 0V (single-supply operation), the output can swing to ground. Note that the settling time of the output op amp will be longer with voltages very near ground. Also, care must be taken when measuring the zero-scale error when VSS = 0V. If the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes (000H, 001H, 002H, etc.) since the output voltage cannot swing below ground. The DAC7614 is a quad, serial input, 12-bit, voltage output DAC. The architecture is a classic R-2R ladder configuration followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network and output op amp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage output (“full-scale”) are set by external voltage references (VREFL and VREFH, respectively). The digital input is a 16-bit serial word that contains the 12-bit DAC code and a 2-bit address code that selects one of the four DACs (the two remaining bits are unused). The converter can be powered from a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and internal registers to either zero-scale (code 000H) or mid-scale (code 800H). The reset code is selected by the state of the RESETSEL pin (LOW = 000H, HIGH = 800H). See Figures 1 and 2 for the basic operation of the DAC7614. +5V + The behavior of the output amplifier can be critical in some applications. Under short-circuit conditions (DAC output shorted to ground), the output amplifier can sink a great deal more current than it can source. See the Specifications table for more details concerning short-circuit current. DAC7614(1) 1µF to 10µF 0.1µF 0V to +2.5V 0V to +2.5V 1 VDD 2 RESETSEL 16 VOUTD RESET 15 Reset DACs(2) 3 VOUTC LOADDACS 14 Update Selected Register 4 VREFL NIC 13 5 VREFH CS 12 Chip Select 6 VOUTB CLK 11 Clock 7 VOUTA SDI 10 Serial Data In 8 VSS GND 9 +2.500V 0.1µF 0V to +2.5V 0V to +2.5V NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers to code 000H (0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (1.25V). FIGURE 1. Basic Single-Supply Operation of the DAC7614. +5V DAC7614(1) + 1µF to 10µF 0.1µF 1 VDD –2.5V to +2.5V 2 –2.5V to +2.5V –2.500V 16 VOUTD RESET 15 Reset DACs(2) 3 VOUTC LOADDACS 14 Update Selected Register 4 VREFL NIC 13 5 VREFH CS 12 Chip Select 6 VOUTB CLK 11 Clock 7 VOUTA SDI 10 Serial Data In 8 VSS GND 9 0.1µF +2.500V 0.1µF –2.5V to +2.5V –2.5V to +2.5V +5V RESETSEL –5V + 1µF to 10µF 0.1µF NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal register to code 800H (0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–2.5V). FIGURE 2. Basic Dual-Supply Operation of the DAC7614. ® 9 DAC7614 REFERENCE INPUTS SYMBOL DESCRIPTION MIN TYP MAX UNITS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.25V and VDD – 2.25V provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL – 1LSB plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. tDS Data Valid to CLK Rising 25 ns tDH Data Held Valid after CLK Rises 20 ns tCH CLK HIGH 30 ns tCL CLK LOW 50 ns tCSS CS LOW to CLK Rising 55 ns tCSH CLK HIGH to CS Rising 15 ns tLD1 LOADDACS HIGH to CLK Rising 40 ns tLD2 The current into the reference inputs depends on the DAC output voltages and can vary from a few microamps to approximately 0.6 milliamp. Bypassing the reference voltage or voltages with a 0.1µF capacitor placed as close as possible to the DAC7614 package is strongly recommended. tS CLK Rising to LOADDACS LOW 15 ns tLDDW LOADDACS LOW Time 45 ns tRSSH RESETSEL Valid to RESET LOW 25 ns tRSTW RESET LOW Time 70 ns Settling Time 10 µs TABLE I. Timing Specifications (TA = –40°C to +85°C). asynchronous reset input (RESET) is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state. DIGITAL INTERFACE The DAC code and address are provided via a 16-bit serial interface as shown in Figure 3. The first two bits select the DAC register that will be updated when LOADDACS goes LOW (see Table II). The next two bits are not used. The last 12 bits is the DAC code which is provided, most significant bit first. Figure 3 and Table I provide the basic timing for the DAC7614. The interface consists of a serial clock (CLK), serial data (SDI), and a load DAC signal (LOADDACS). In addition, a chip select (CS) input is available to enable serial communication when there are multiple serial devices. An (MSB) SDI A1 A0 X X D11 (LSB) D10 D9 D3 D2 D1 D0 CLK tcss tCSH tLD1 tLD2 CS LOADDAC tLDDW tDS tDH SDI tCL tCH CLK tLDDW LOADDAC tS VOUT tS 1 LSB ERROR BAND 1 LSB ERROR BAND tRSTW RESET tRSSH RESETSEL FIGURE 3. DAC7614 Timing. ® DAC7614 10 STATE OF SELECTED DAC REGISTER A1 A0 LOADDACS RESET SELECTED DAC REGISTER L(1) L L H A Transparent L H L H B Transparent H L L H C Transparent H H L H D Transparent X(2) X H H NONE (All Latched) X X X L ALL Reset(3) Note that CS and CLK are combined with an OR gate and the output controls the serial-to-parallel shift register internal to the DAC7614 (see the block diagram on the front of this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong DAC. NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in their latched state retain the reset value. If both CS and CLK are used, then CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table III for more information. TABLE II. Control Logic Truth Table. Digital Input Coding CS(1) CLK(1) LOADDACS RESET SERIAL SHIFT REGISTER H (2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit ↑ L H H Advanced One Bit H (6) X L(7) H No Change H (6) X H L(8) No Change The DAC7614 input data is in Straight Binary format. The output voltage is given by the following equation: VOUT = VREFL + (VREFH – VREFL) • N 4096 where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOADDACS is LOW, the selected DAC register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each DAC register that has been erroneously selected. (8) RESET LOW causes no change in the contents of the serial shift register. TABLE III. Serial Shift Register Truth Table. ® 11 DAC7614 LAYOUT The power applied to VDD (as well as VSS, if not grounded) should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the DAC7614 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter. As with the GND connection, VDD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1µF to 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high frequency noise (see Figure 4). Because the DAC7614 has a single ground pin, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system (see Figure 4). Digital Circuits +5V +5V Power Supply Ground +5V DAC7614 Ground VDD 100µF + + 1µF to 10µF 0.1µF GND Optional Other Analog Components FIGURE 4. Suggested Power and Ground Connections for a DAC7614 Sharing a +5V Supply with a Digital System. ® DAC7614 12