® DAC7631 DAC ® 763 1 For most current data sheet and other product information, visit www.burr-brown.com Serial Input, 16-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● LOW POWER: 2.5mW ● ATE PIN ELECTRONICS ● UNIPOLAR OR BIPOLAR OPERATION ● SETTLING TIME: 10µs to 0.003% ● PROCESS CONTROL ● CLOSED-LOOP SERVO-CONTROL ● 15-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● USER SELECTABLE RESET TO MID-SCALE OR ZERO-SCALE ● SMALL SSOP-20 PACKAGE DESCRIPTION The DAC7631 is a serial input, 16-bit, voltage output Digital-to-Analog Converter (D/A) with guaranteed 15-bit monotonic performance over the –40°C to +85°C temperature range. An asynchronous reset clears all registers to either mid-scale (8000H) or zero-scale (0000H), selectable via the RESETSEL pin. The device can be powered from a single +5V supply or from dual +5V and –5V supplies. SDO CLK Shift Register VDD VCC Low power and small size makes the DAC7631 ideal for process control, data acquisition systems, and closed-loop servo-control. The device is available in a SSOP-20 package, and is guaranteed over the –40°C to +85°C temperature range. VREFL Sense VSS DAC Register Input Register VREFL VREFH VREFH Sense DAC A VOUT CS VOUT Sense SDI AGND DAC7631 LOAD RSTSEL RST LDAC DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1999 Burr-Brown Corporation SBAS122 PDS-1536A 1 Printed in U.S.A. August, 2000 DAC7631 SPECIFICATIONS (Dual Supply) At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted. DAC7631E PARAMETER CONDITIONS ACCURACY Linearity Error Differential Linearity Error Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration DAC7631EB TYP MAX ±3 ±2 ±4 ±3 ±1 5 ±1 5 10 ±2 10 ±2 10 100 14 At Full Scale VREF = –2.5V, RL = 10kΩ, VSS = –5V MIN VREFH +1.25 VREFL + 1.25 –2.5 +2.5 VREFH – 1.25 8 2 60 40 f = 10kHz 7FFFH to 8000H or 8000H to 7FFFH DIGITAL INPUT VIH VIL IIH IIL UNITS ±2 ±1 ±3 ±2 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB Bits mV ppm/°C mV ppm/°C ppm/V ✻ ✻ ✻ ✻ ✻ ✻ 10 POWER SUPPLY VDD VCC VSS ICC IDD ISS Power 3.6 +4.75 +4.75 –5.25 –0.6 TEMPERATURE RANGE Specified Performance –40 ✻ ✻ V V µA µA ✻ µs nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 IOH = –0.8mA IOL = 1.6mA V mA pF mA ✻ ✻ 0.7 • VDD DIGITAL OUTPUT VOH VOL ✻ ✻ ✻ ✻ ✻ 500 –500 To ±0.003%, 5V Output Step MAX ✻ ✻ 500 –10, +30 Indefinite GND or VCC or VSS TYP 15 VREFL –1.25 No Oscillation REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Digital Feedthrough Output Noise Voltage DAC Glitch MIN 4.5 0.3 +5.0 +5.0 –5.0 0.4 50 –0.5 4 ✻ 0.4 +5.25 +5.25 –4.75 0.5 ✻ ✻ ✻ ✻ 5.5 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mA mW ✻ °C ✻ Specifications same as DAC7631E. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7631 2 SPECIFICATIONS (Single Supply) At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted. DAC7631E PARAMETER ACCURACY Linearity Error(1) Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS At Full Scale VREFL = 0V, VSS = 0V, RL = 10kΩ POWER SUPPLY VDD VCC VSS ICC IDD Power TEMPERATURE RANGE Specified Performance MAX ±3 ±2 ±4 ±3 ±1 5 ±1 5 10 ±2 10 ±2 10 100 MIN VREFH +1.25 VREFL + 1.25 0 +2.5 VREFH – 1.25 8 2 60 40 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±1 ±3 ±2 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB Bits mV ppm/°C mV ppm/°C ppm/V ✻ ✻ ✻ ✻ ✻ ✻ 10 +4.75 +4.75 0 –40 ✻ ✻ V V µA µA ✻ µs nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 3.6 V mA pF mA ✻ ✻ 0.7 • VDD IOH = –0.8mA IOL = 1.6mA ✻ ✻ ✻ ✻ ✻ 250 –250 To ±0.003%, 2.5V Output Step MAX ✻ ✻ 500 ±30 Indefinite GND or VCC TYP 15 0 –1.25 No Oscillation DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL DAC7631EB TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Digital Feedthrough Output Noise Voltage, f = 10kHz DAC Glitch MIN 4.5 0.3 +5.0 +5.0 0 0.4 50 1.8 ✻ 0.4 +5.25 +5.25 0 0.5 ✻ ✻ ✻ 2.5 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mW ✻ °C NOTE: (1) If VSS = 0V specification applies at Code 0040H and above due to possible negative zero-scale error. ✻ Specifications same as DAC7631E. ® 3 DAC7631 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to VSS ........................................................................... –0.3V to +11V VDD to GND ........................................................................ –0.3V to +5.5V VREFL to VSS ............................................................... –0.3V to (VDD – VSS) VDD to VREFH .............................................................. –0.3V to (VDD – VSS) VREFH to VREFL ............................................................ –0.3V to (VDD – VSS) Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM LINEARITY ERROR (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) DAC7631E PACKAGE PACKAGE DRAWING NUMBER SPECIFICATION TEMPERATURE RANGE ±4 ±3 SSOP-20 334 –40°C to +85°C " " " " " " DAC7631EB ±3 ±2 SSOP-20 334 –40°C to +85°C " " " " " " ORDERING NUMBER(1) TRANSPORT MEDIA DAC7631E DAC7631E/1K DAC7631EB DAC7631EB/1K Rails Tape and Reel Rails Tape and Reel NOTE : (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7631E/1K” will get a single 1000-piece Tape and Reel. ® DAC7631 4 PIN CONFIGURATION PIN DESCRIPTIONS Top View PIN SSOP LABEL DESCRIPTION DAC Reference High Input 1 VREFH 2 VREFH Sense DAC Reference Sense High Input VREFH 1 20 VCC 3 VREFL VREFH Sense 2 19 AGND 4 VREFL Sense VREFL 3 18 VSS 5 DGND 6 VDD Logic Power Supply 7 SDO Serial Data Output 8 SDI Serial Data Input DAC Reference Low Input DAC Reference Sense Low Input Digital Ground VREFL Sense 4 17 VOUT Sense DGND 5 16 VOUT VDD 6 15 NC 9 CLK Data Clock SDO 7 14 RSTSEL 10 CS Chip Select, Active LOW. SDI 8 13 RST 11 LDAC 12 LOAD CLK 9 12 LOAD 13 RST CS 10 11 LDAC Reset, Rising Edge. Depending on the state of RSTSEL, the DAC Register is set to either midscale or zero. 14 RSTSEL Reset Select. Determines the action of RST. If HIGH, a RST command will set the DAC register to midscale. If low, a RST command will set the DAC register to zero. DAC7631 15 NC 16 VOUT 17 VOUT Sense 18 VSS 19 AGND 20 VCC DAC Register Load Control, Rising Edge Triggered. DAC Input Register Load Control, Active LOW. No Connection DAC Voltage Output DAC Output Amplifier Inverting Input, Used to Close the Feedback Loop at the Load. Negative Power Supply Analog Ground Positive Power Supply ® 5 DAC7631 TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+85°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) ZERO-SCALE ERROR vs TEMPERATURE (Code 0040H) 2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 1.5 Zero-Scale Error (mV) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –30 –20 –10 0 Digital Input Code POSITIVE FULL-SCALE ERROR vs TEMPERATURE (Code FFFFH) VREFH CURRENT vs CODE 2.0 0.14 1.5 0.12 1.0 VREF Current (mA) Positive Full-Scale Error (mV) 10 20 30 40 50 60 70 80 90 Temperature (°C) 0.5 0 –0.5 –1.0 0.10 0.08 0.06 0.04 0.02 –1.5 –2.0 –40 –30 –20 –10 0 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 10 20 30 40 50 60 70 80 90 Temperature (°C) Digital Input Code ® DAC7631 6 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified. VREFL CURRENT vs CODE POWER SUPPLY CURRENT vs TEMPERATURE 0 1.0 0.8 Quiescent Current (mA) VREF Current (mA) –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 Data = FFFFH No Load 0.6 ICC 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –0.14 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 Digital Input Code Temperature (°C) POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE OUTPUT VOLTAGE vs SETTLING TIME (0V to +2.5V) 90 0.50 +5V LDAC 0 0.45 Large-Signal Settling Time: 0.5V/div 0.40 Output Voltage ICC 0.30 0.25 0.20 0.15 Small-Signal Settling Time: 4LSB/div 0.10 0.05 FFFFH E000H C000H A000H 8000H 6000H 4000H 2000H 1000H 0800H 0400H 0200H 0000H 0 Time (2µs/div) Digital Input Code OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to 2mV) OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE +5V LDAC 0 +5V LDAC 0 Output Voltage (50mV/div) Output Voltage ICC (mA) 0.35 Small-Signal Settling Time: 4LSB/div Large-Signal Settling Time: 0.5V/div Time (2µs/div) 7FFFH to 8000H Time (1µs/div) ® 7 DAC7631 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE BROADBAND NOISE Noise Voltage (50µV/div) Output Voltage (50mV/div) +5V LDAC 0 8000H to 7FFFH BW = 10kHz Code = 8000H Time (10ms/div) Time (1µs/div) OUTPUT VOLTAGE vs RLOAD OUTPUT NOISE VOLTAGE vs FREQUENCY 5 1000 VOUT (V) Noise (nV/√Hz) 4 100 3 Source 2 1 Sink 0 0.01 10 100 10 1000 10000 100000 1000000 ® DAC7631 0.1 1 RLOAD (kΩ) Frequency (Hz) 8 10 100 TYPICAL PERFORMANCE CURVES: VSS = –5V At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+85°C) LE (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code VREFH CURRENT vs CODE 0.30 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0.25 VREF Current (mA) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 0.15 0.10 0.05 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code VREFL CURRENT vs CODE BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE (Code 8000H) 0 Bipolar Zero-Scale Error (mV) 2.0 –0.05 VREF Current (mA) 0.20 –0.10 –0.15 –0.20 –0.25 –0.30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Digital Input Code ® 9 DAC7631 TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified. NEGATIVE FULL-SCALE ERROR vs TEMPERATURE (Code 0000H) 2.0 2.0 1.5 1.5 Negative Full-Scale Error (mV) Positive Full-Scale Error (mV) POSITIVE FULL-SCALE ERROR vs TEMPERATURE (Code FFFFH) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 Temperature (°C) 10 20 30 40 50 60 70 80 90 Temperature (°C) VOUT vs RLOAD POWER SUPPLY CURRENT vs TEMPERATURE 5 1.0 4 Data = FFFFH No Load 0.6 0.4 2 0.2 1 0 –0.2 ISS –0.4 0 –1 Sink –2 –0.6 –3 –0.8 –4 –5 0.001 –1.0 –40 –30 –20 –10 0 Source 3 ICC VOUT (V) Quiescent Current (mA) 0.8 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 1000 RLOAD (kΩ) Temperature (°C) OUTPUT VOLTAGE vs SETTLING TIME (–2.5V to +2.5V) POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE 0.50 0.45 Large-Signal Settling Time: 1V/div ICC 0.40 Output Voltage 0.30 0.25 0.20 0.15 Small-Signal Settling Time: 2LSB/div 0.10 0.05 FFFFH E000H C000H A000H 8000H 6000H 4000H 2000H 1000H 0800H 0400H 0200H 0 0000H ICC (mA) 0.35 Time (2µs/div) Digital Input Code ® DAC7631 10 +5V LDAC 0 TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to –2.5V) +5V LDAC 0 Output Voltage Small-Signal Settling Time: 2LSB/div Large-Signal Settling Time: 1V/div Time (2µs/div) THEORY OF OPERATION The digital input is a 16-bit serial word representing the 16-bit DAC input code, sent MSB first. The DAC7631 can be powered from either a single +5V supply or a dual ±5V supply. The device offers a reset function which immediately sets the output voltage and DAC register to mid-scale code (8000H) or to zero-scale code (0000H). See Figures 2 and 3 for the basic operation of the DAC7631. The DAC7631 is a 16-bit voltage-output Digital-to-Analog Converter (DAC). The architecture is an R-2R ladder configuration with the three MSB’s segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by external voltage references at VREFL and VREFH, respectively. RF VOUT Sense VOUT R 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7631 Architecture. ® 11 DAC7631 +5V +2.5000V 1 VREFH VCC 20 2 VREFH Sense VSS 18 4 VREFL Sense VOUT Sense 17 DAC7631 0V to +2.5V VOUT 16 6 VDD Serial Data Out 1µF AGND 19 3 VREFL 5 DGND + 0.1µF NC 15 7 SDO RSTSEL 14 Serial Data In 8 SDI RST 13 Clock 9 CLK LOAD 12 Load 10 CS LDAC 11 Load DAC Registers Chip Select Reset DAC Registers FIGURE 2. Basic Single-Supply Operation. +5V +5V +2.5000V VCC 20 1 VREFH 2 VREFH Sense 0.1µF + –2.5000V 1µF 3 VREFL 5 DGND 0.1µF + + 1µF 1µF VSS 18 4 VREFL Sense –5V VOUT Sense 17 DAC7631 6 VDD Serial Data Out AGND 19 0.1µF VOUT 16 –2.5V to +2.5V NC 15 7 SDO RSTSEL 14 Reset DAC Registers Serial Data In 8 SDI RST 13 Clock 9 CLK LOAD 12 Load 10 CS LDAC 11 Load DAC Registers Chip Select FIGURE 3. Basic Dual-Supply Operation. ANALOG OUTPUTS When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, guaranteed over the –40°C to +85°C temperature range. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of –2mV, the first specified output starts at code 0040H. load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30µV. The DAC7631 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 4), thus ensuring an accurate output voltage. REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.5V and VCC – 2.5V, provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. Due to the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V fullscale range has a 1LSB value of 38µV. With a load current of 1mA, series wiring and connector resistance of only 40mΩ (RW2) will cause a voltage drop of 40µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copperclad printed circuit board is 1/2 mΩ per square. For a 1mA ® DAC7631 12 DIGITAL INTERFACE The current into the VREFH input and out of VREFL depends on the DAC output voltage, and can vary from a few microamps to approximately 0.3mA in dual supply or 0.15mA in single-supply operation. The reference input appears as a varying load to the reference. If the reference can sink or source the required current, a reference buffer is not required. The DAC7631 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations, and the effect on the linearity and differential linearity. Table I shows the basic control logic for the DAC7631. The interface consists of a serial clock input (CLK), serial data input (SDI), DAC input register load control signal (LOAD), and DAC load control signal (LDAC). In addition, a chip select input (CS) is provided to simplify device selection in systems with multiple devices. An asynchronous reset input (RST), triggered by a rising edge, is provided to force startup conditions, periodic resets, or emergency resets to a known state. The action of RST can be selected using the reset select (RSTSEL) pin. SERIAL DATA INPUT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CS RST RSTSEL LDAC LOAD INPUT REGISTER DAC REGISTER MODE L H H X X H H H ↑ ↑ X X X L H X ↑ H X X L H H X X Write Hold Hold Reset to Zero Reset to Midscale Hold Write Hold Reset to Zero Reset to Midscale Write Input Update Hold Reset to Zero Reset to Midscale TABLE I. DAC7631 Logic Truth Table. +5V +V 1 VREFH +2.5V VCC 20 2 VREFH Sense AGND 19 3 VREFL VSS 18 4 VREFL Sense 5 DGND VOUT Sense 17 DAC7631 6 VDD Serial Data Out 0.1µF + 1µF RW1 RW2 VOUT 16 VOUT NC 15 7 SDO RSTSEL 14 Reset DAC Registers Serial Data In 8 SDI RST 13 Clock 9 CLK LOAD 12 Load 10 CS LDAC 11 Load DAC Registers Chip Select FIGURE 4. Analog Output Closed-loop Configuration. RW1 and RW2 represent wiring resistance. +V +V OPA2234 2200pF +2.5V 100Ω 1 VREFH 1000pF DAC7631 2 VREFH Sense 3 VREFL 4 VREFL Sense 100Ω –2.5V 2200pF 1000pF –V –V FIGURE 5. Dual-supply Buffered References. ® 13 DAC7631 +V OPA2350 2kΩ 2200pF 100Ω 1000pF +0.050V 1 VREFH +V 98kΩ DAC7631 2 VREFH Sense 3 VREFL +2.5V 100Ω 4 VREFL Sense 1000pF 2200pF NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 6. Single-supply Buffered Reference, VREFL = 50mV. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 8. Integral Linearity and Differential Linearity Error Curves for Figure 9. FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 6. +V +V OPA2350 2200pF +1.25V 100Ω 1000pF 1 VREFH DAC7631 2 VREFH Sense +V 3 VREFL 100Ω +2.5V 2200pF 4 1000pF FIGURE 9. Single-supply Buffered Reference, VREFL = +1.25V, VREFH = –1.25V. ® DAC7631 14 VREFL Sense +V +V OPA2350 1 VREFH +2.5V DAC7631 2 VREFH Sense 100Ω 3 VREFL 1000pF 2200pF 4 VREFL Sense FIGURE 10. Single-supply Buffered VREFH. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 13. Linearity and Differential Error Curves for Figure 12. FIGURE 11. Linearity and Differential Error Curves for Figure 10. +5V +V 1 VREFH +2.5V VCC 20 2 VREFH Sense 1µF VSS 18 4 VREFL Sense VOUT Sense 17 DAC7631 6 VCC Serial Data Out + AGND 19 3 VREFL 5 DGND 0.1µF VOUT 16 VOUT NC 15 7 SDO RSTSEL 14 Serial Data In 8 SDI RST 13 Clock 9 CLK LOAD 12 Load 10 CS LDAC 11 Load DAC Registers Chip Select Reset DAC Registers FIGURE 12. Low cost Single-supply Configuration. Data is shifted into the device through the SDI and CLK pins and arrives in a shift register. Once all 16 bits have been transferred, the LOAD pin, which is level-sensitive, should be brought low to latch the data into a buffer register called the DAC input register. To latch the new data into the DAC itself, the LDAC pin, which is edge-sensitive, must be brought high. When this is done, the DAC will assume the new value and the output voltage will change (provided that the new value is different from the old one). Note that settling time is measured from the time that the LDAC pin is brought high, since the device’s output does not begin to change until then. The DAC7631’s double-buffering scheme allows the device to be updated through the serial interface without disturbing the voltage on the output pin. It also allows the user to use separate logic for driving the serial input and triggering ® 15 DAC7631 DAC7631 SCK CLK DIN SDI CS CS DAC7631 CLK SDO DAC7631 CLK SDO SDI CS SDI SDO To Other Serial Devices CS FIGURE 14. Daisy-chaining DAC7631. DIGITAL TIMING DAC updates; i.e., the LDAC pin can be driven with a separate signal, such as a timing clock, which need not be directly related to the serial data timing. This makes it easy to synchronize DAC7631 updates with external events or with other DACs. Figure 15 and Table III provide detailed timing for the digital interface of the DAC7631. DIGITAL INPUT CODING The DAC7631 input data is in Straight Binary format. The output voltage is given by Equation 1: Note that CS and CLK are combined with an OR gate, which controls the serial-to-parallel shift register. These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register(s). If both CS and CLK are used, CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table II for more information. CS(1) CLK(1) LOAD RST SERIAL SHIFT REGISTER H (2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit ↑ L H H Advanced One Bit H (6) X L(7) H No Change H (6) X H ↑(8) No Change VOUT = VREF L + 65, 536 (1) where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. DIGITALLY-PROGRAMMABLE CURRENT SOURCE The DAC7631 offers a unique set of features that allows a wide range of flexibility in designing applications circuits such as programmable current sources. The DAC7631 offers both a differential reference input, as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitallyprogrammable, unidirectional current source. The availability of a differential reference allows programmability for both the full-scale and zero-scale currents. The output current is calculated as: NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOAD is LOW, the DAC register will change. This will corrupt the data in each DAC register that has been erroneously selected. (8) Rising edge of RST causes no change in the contents of the serial shift register. TABLE II. Serial Shift Register Truth Table. V H – VREF L N I OUT = REF • R SENSE 65, 536 SERIAL-DATA OUTPUT The Serial-Data Output (SDO) is the internal shift register’s output. For DAC7631, the SDO is a driven output and does not require an external pull-up. Any number of DAC7631’s can be daisy chained by connecting the SDO pin of one device to the SDI pin of the following device in the chain, as shown in Figure 14. + (VREF L / R SENSE ) ® DAC7631 (VREF H – VREF L) • N 16 (2) (LSB) (MSB) SDI D15 D14 D13 D12 D11 D10 D3 D9 D1 D2 D0 CLK tcss tCSH tLD1 tLD2 CS tLDDD LOAD tLDRW LDAC tDS tDH SDI tSDO tCL tCH CLK SDO tLDDL tLDDH LDAC tS tS ±0.003% ERROR BAND VOUT tRSTL ±1LSB ERROR BAND tRSTH RESET tRSSH tRSSS RESETSEL FIGURE 15. Digital Input and Output Timing. SYMBOL DESCRIPTION MIN tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 tLDRW tLDDL tLDDH tSDO tRSSS tRSSH tRSTL tRSTH tLDDD tS Data Valid to CLK Rising Data Held Valid after CLK Rises CLK HIGH CLK LOW CS LOW to CLK Rising CLK HIGH to CS Rising LOAD HIGH to CLK Rising CLK Rising to LOAD LOW LOAD LOW Time LDAC LOW Time LDAC HIGH Time SDO Propagation Delay RESETSEL Valid to RESET HIGH RESET HIGH to RESETSEL Not Valid RESET LOW Time RESET HIGH Time LOAD LOW to LDAC Rising Time Settling Time 10 20 25 25 15 0 10 30 30 100 150 10 0 100 10 10 40 MAX 45 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs TABLE III. Timing Specifications (TA = –40°C to +85°C). ® 17 DAC7631 Figure 16 shows a DAC7631 in a 4mA to 20mA current output configuration. The output current can be determined by Equation 3: 2.5V – 0.5V N 0.5V • I OUT = + 125Ω 65, 536 125Ω At full-scale, the output current is 16mA, plus the 4mA, for the zero current. At zero scale the output current is the offset current of 4mA (0.5V/125Ω). (3) +V OPA2350 20kΩ 2200pF 100Ω +V 80kΩ 1000pF +2.5V 100Ω 1000pF 2200pF +5V 1 VREFH VCC 20 2 VREFH Sense Serial Data Out Serial Data In Clock Chip Select 7 SDO IOUT VOUT Sense 17 DAC7631 VOUT 16 NC 15 RSTSEL 14 Reset DAC Registers 8 SDI RST 13 9 CLK LOAD 12 Load 10 CS LDAC 11 Load DAC Registers FIGURE 16. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7631). ® DAC7631 1µF VSS 18 4 VREFL Sense 6 VDD + AGND 19 3 VREFL 5 DGND 0.1µF 18 VPROGRAMMED 125Ω PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) DAC7631E ACTIVE SSOP DB 20 68 None CU SNPB Level-3-220C-168 HR DAC7631E/1K ACTIVE SSOP DB 20 1000 None CU SNPB Level-3-220C-168 HR DAC7631EB ACTIVE SSOP DB 20 68 None CU SNPB Level-3-220C-168 HR DAC7631EB/1K ACTIVE SSOP DB 20 1000 None CU SNPB Level-3-220C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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