DAC7551 www.ti.com SLAS441 – MARCH 2005 12-BIT, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.1 nVs Low Power: 200 µA (Max) Power Down: 2 µA (Max) Power-On Reset to Zero Scale SPI-Compatible Serial Interface: Up to 50 MHz Daisy-Chain Capability Asynchronous Hardware Clear Specified Temperature Range: –40°C to 105°C Small, 2-mm x 3-mm, 12-Lead SON Package The 3-wire serial interface operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire™, and DSP interface standards. The parts incorporate a power-on-reset circuit to ensure that the DAC outputs power up to zero volts and remain there until a valid write cycle to the device takes place. The parts contain a power-down feature that reduces the current consumption of the device to under 2 µA. The small size and low-power operation makes the DAC7551 ideally suited for battery-operated portable applications. The power consumption is typically 0.5 mW at 5 V, 0.23 mW at 3 V, and reduces to 1 µW in power-down mode. APPLICATIONS • • • • • The DAC7551 is a single-channel, voltage-output DAC with exceptional linearity and monotonicity. Its proprietary architecture minimizes glitch energy. The low-power DAC7551 operates from a single 2.7-V to 5.5-V supply. The DAC7551 output amplifiers can drive a 2-kΩ, 200-pF load rail-to-rail with 5-µs settling time; the output range is set using an external voltage reference. Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The DAC7551 is available in a 12-lead SON package and is specified over –40°C to 105°C. FUNCTIONAL BLOCK DIAGRAM VDD IOVDD VREFH VFB SCLK SYNC _ Interface Logic Shift Register DAC Register String DAC + VOUT SDIN Power-On Reset SDO CLR Power-Down Logic GND VREFL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Microwire is a trademark of National Semiconductor Corp.. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW FEATURES DAC7551 www.ti.com SLAS441 – MARCH 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC7551 12 SON DRN –40°C TO 105°C D51 (1) ORDERING NUMBER TRANSPORT MEDIA DAC7551IDRNT 250-piece Tape and Reel DAC7551IDRNR 2500-piece Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS PRODUCT PREVIEW over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD to GND –0.3 V to 6 V Digital input voltage to GND –0.3 V to VDD + 0.3 V VOUT to GND –0.3 V to VDD+ 0.3 V Operating temperature range –40°C to 105°C Storage temperature range –65°C to 150°C Junction temperature (TJ Max) (1) 2 150°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC7551 www.ti.com SLAS441 – MARCH 2005 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VREFH = VDD, VREFL = GND, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design ±1 LSB ±0.08 ±0.5 LSB ±12 mV ±12 mV Offset error Zero-scale error All zeroes loaded to DAC register Gain error Full-scale error Zero-scale error drift Gain temperature coefficient PSRR VDD = 5 V Bits ±0.35 ±0.15 %FSR ±0.5 %FSR 7 µV/°C 3 ppm of FSR/°C 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage settling time 2 x VREFL RL = 2 kΩ; 0 pF < CL < 200 pF 5 Slew rate Capacitive load stability 1 RL = ∞ V µs V/µs 470 RL = 2 kΩ Digital-to-analog glitch impulse VREFH pF 1000 0.1 nV-s Digital feedthrough 0.1 nV-s Output noise density (10-kHz offset frequency) 70 nV/rtHz –85 dB 1 Ω VDD = 5 V 50 mA VDD = 3 V 20 Coming out of power-down mode, VDD = 5 V 15 Coming out of power-down mode, VDD = 3 V 15 Total harmonic distortion 1 LSB change around major carry FOUT = 1 kHz, FS = 1 MSPS, BW = 20 kHz DC output impedance Short-circuit current Power-up time PRODUCT PREVIEW Output voltage range µs REFERENCE INPUT VREFH, Input range VREFL, Input range 0 VREFL < VREFH 0 Reference input impedance Reference current VDD GND VDD 100 V V kΩ VREF = VDD = 5 V 130 250 VREF = VDD = 3 V 65 123 µA LOGIC INPUTS (2) Input current VIN_L, Input low voltage VDD = 5 V VIN_H, Input high voltage VDD = 3 V Pin capacitance (1) (2) ±1 µA 0.3 VDD V 3 pF 0.7 VDD V Linearity tested using a reduced code range of 30 to 4065; output unloaded. Specified by design and characterization, not production tested. 3 DAC7551 www.ti.com SLAS441 – MARCH 2005 ELECTRICAL CHARACTERISTICS (Continued) VDD = 2.7 V to 5.5 V, VREFH = VDD, VREFL = GND, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER REQUIREMENTS VDD 2.7 IDD(normal operation) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V DAC active and excluding load current VIH = VDD and VIL = GND 5.5 V 150 200 µA 100 150 0.2 2 0.05 2 IDD (all power-down modes) VDD = 3.6 V to 5.5 V VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V Reference input impedance 100 POWER EFFICIENCY IOUT/IDD PRODUCT PREVIEW 4 ILOAD = 2 mA, VDD = 5 V 93% µA kΩ DAC7551 www.ti.com SLAS441 – MARCH 2005 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified TEST CONDITIONS t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 SCLK falling edge to SDO valid t10 CLR pulse width low (1) (2) (3) MIN VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 4 VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 5 VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V TBD VDD = 3.6 V to 5.5 V TBD VDD = 2.7 V to 3.6 V TBD VDD = 3.6 V to 5.5 V TBD TYP MAX UNITS ns ns ns ns ns ns ns PRODUCT PREVIEW PARAMETER ns ns ns All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram Figure 1. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. t1 SCLK t8 t2 t3 t4 t7 SYNC t5 SDIN D15 t6 D14 D13 D12 D11 D1 D0 Input Word n SDO D0 t9 D15 Undefined CLR D15 Input Word n+1 D14 D0 Input Word n t10 Figure 1. Serial Write Operation 5 DAC7551 www.ti.com SLAS441 – MARCH 2005 PIN DESCRIPTION DRN PACKAGE (TOP VIEW) 1 12 IOVDD VREFH 2 11 SDO VREFL 3 10 SDIN VFB 4 9 SCLK VOUT 5 8 SYNC GND 6 7 CLR VDD Terminal Functions TERMINAL NO. PRODUCT PREVIEW 6 DESCRIPTION NAME 1 VDD Analog voltage supply input 2 VREFH Positive reference voltage input 3 VREFL Negative reference voltage input 4 VFB DAC amplifier sense input. 5 VOUT Analog output voltage from DAC 6 GND Ground 7 CLR Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000H and the output voltage to 0 V. 8 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7551. 9 SCLK Serial clock input 10 SDIN Serial data input 11 SDO Serial data output 12 IOVDD I/O voltage supply input DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE VREFH = 4.096 V VREFL = GND Linearity Error − LSB Linearity Error − LSB 1 VDD = 5 V 0.5 0 −0.5 1 VREFH = 2.5 V VREFL = GND VDD = 2.7 V 0.5 0 Differential Linearity Error − LSB 0.5 0.25 0 −0.25 −1 0.5 0.25 0 −0.25 0 512 1024 1536 2048 2560 3072 3584 4096 −0.5 0 Digital Input Code 512 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 2. Figure 3. ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 1 1 VDD = 5 V, VREFH= 4.096 V, VREFL= GND VDD = 2.7 V, VREFH = 2.5 V, VREFL = GND 0.75 Zero-Scale Error − mV 0.75 0.5 0.5 0.25 0.25 0 −40 1024 −10 20 50 80 TA − Free-Air Temperature − °C Figure 4. 0 −40 −10 20 50 80 TA − Free-Air Temperature − °C Figure 5. 7 PRODUCT PREVIEW −0.5 Zero-Scale Error − mV Differential Linearity Error − LSB −0.5 −1 DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) FULL-SCALE ERROR vs FREE-AIR TEMPERATURE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0 0 VDD = 5 V, VREFH= 4.096 V, VREFL= GND VDD = 2.7 V, VREFH= 2.5 V, VREFL= GND −0.25 Full-Scale Error − mV Full-Scale Error − mV −0.25 −0.5 −0.75 −0.5 −0.75 PRODUCT PREVIEW −1 −40 −1 −40 −10 20 50 80 TA − Free-Air Temperature − °C Figure 6. −10 20 50 80 TA − Free-Air Temperature − °C Figure 7. SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 VDD = 2.7 V, VREFH = 2.5 V, VREFL = GND 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical 0.1 VDD = 5.5 V, VREFH = 4.096 V, VREFL = GND VDD = VREFH = 5.5 V, VREFL = GND 5.40 5.30 0.05 DAC Loaded with 000h 0 0 5 10 ISINK − Sink Current − mA Figure 8. 8 DAC Loaded with FFFh 15 5.20 0 5 10 ISOURCE − Source Current − mA Figure 9. 15 DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 250 2.7 VDD = 5.5 V, VREFH= 4.096 V, VREFL= GND I DD − Supply Current − µ A VO − Output Voltage − V 200 VDD = VREFH = 2.7 V, VREFL = GND 2.6 2.5 150 VDD = 2.7 V, VREFH= 2.5 V, VREFL= GND 100 50 2.4 0 5 10 0 15 0 ISOURCE − Source Current − mA Figure 11. SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 125 DAC Powered, No Load, VREFH= 2.5 V, VREFL= GND I DD − Supply Current − µ A VDD = 5.5 V, VREFH= 4.096 V, VREFL= GND I DD − Supply Current − µ A 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 10. 200 PRODUCT PREVIEW Powered, No Load DAC Loaded with FFFh VDD = 2.7 V, VREFH= 2.5 V, VREFL= GND 150 113 100 88 Powered, No Load 100 −40 −10 20 50 80 TA − Free-Air Temperature − °C Figure 12. 110 75 2.7 3.1 3.4 3.8 4.1 4.5 4.8 5.2 5.5 VDD − Supply Voltage − V Figure 13. 9 DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V 1600 2000 VDD = 5.5 V, VREFH= 4.096 V, VREFL=GND 1200 1500 VDD = 5.5 V, VREFH= 4.096 V, VREFL=GND f − Frequency − Hz I DD − Supply Current − µ A TA = 25C, SCLK Input (All Other Inputs = GND) 800 VDD = 2.7 V, VREFH= 2.5 V VREFL= GND 400 1000 500 PRODUCT PREVIEW 0 0 1 2 3 4 0 5 128 136 VLOGIC − Logic Input Voltage − V 144 152 160 168 Figure 14. HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 1500 VDD = 5 V, VREFH= 4.096 V, VREFL= GND, TA = 25C 2 Total Error − mV f − Frequency − Hz 192 4 VDD = 2.7 V, VREFH= 2.5 V, VREFL= GND 1000 500 0 −2 117 124 131 138 145 152 159 166 173 IDD − Current Consumption − A Figure 16. 10 184 Figure 15. 2000 0 176 IDD − Current Consumption − A −4 0 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 17. DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) TOTAL ERROR - 2.7 V EXITING POWER-DOWN MODE 4 5 VDD = 5 V, VREFH = 4.096 V, VREFL = GND Power-Up Code 4000 VDD = 2.7 V, VREFH= 2.5 V, VREFL= GND, TA = 25C 4 VO − Output Voltage − V 0 −2 −4 3 2 1 0 0 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code PRODUCT PREVIEW Total Error − mV 2 t − Time − 4 s/div Figure 18. Figure 19. LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 VDD = 2.7 V, VREFH = 2.5 V, VREFL = GND Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, VREFH = 4.096 V, VREFL = GND, Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 t − Time − 5 s/div Figure 20. t − Time − 5 s/div Figure 21. 11 DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) WORST-CASE GLITCH VO - VO - (5 mV/Div) (5 mV/Div) MIDSCALE GLITCH Trigger Pulse Trigger Pulse PRODUCT PREVIEW Time - (400 nS/Div) Time - (400 nS/Div) Figure 22. Figure 23. DIGITAL FEEDTHROUGH ERROR TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY VO - (5 mV/Div) THD − Total Harmonic Distortion − dB −40 Trigger Pulse VDD = 5 V, VREFH = 4.096 V, VREFL = GND −1-dB FSR Digital Input, Fs = 1 Msps Measurement Bandwidth = 20 kHz −50 −60 −70 THD −80 2nd Harmonic −90 −100 3rd Harmonic 0 1 2 3 4 5 6 7 8 Output Frequency (Tone) − kHz Time - (400 nS/Div) Figure 24. 12 Figure 25. 9 10 DAC7551 www.ti.com SLAS441 – MARCH 2005 TYPICAL CHARACTERISTICS (continued) 3-Wire Serial Interface The DAC7551 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming DATA BITS FUNCTION DB15 DB14 DB13 (PD1) DB12 (PD0) DB11–DB0 X X 0 0 data X X 0 1 X Powerdown 1 kΩ X X 1 0 X Powerdown 100 kΩ X X 1 1 X Powerdown Hi-Z Normal mode PRODUCT PREVIEW CONTROL 13 DAC7551 www.ti.com SLAS441 – MARCH 2005 THEORY OF OPERATION D/A SECTION DAC External Reference Input The architecture of the DAC7551 consists of a string DAC followed by an output buffer amplifier. Figure 26 shows a generalized block diagram of the DAC architecture. There is a single reference input pin for the DAC. The reference input is unbuffered. The user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of any reference amplifier. VREFH VFB _ Ref + Resistor String Ref − DAC Register VOUT + Power-On Reset VREFL Figure 26. Typical DAC Architecture PRODUCT PREVIEW The input coding to the DAC7551 is unsigned binary, which gives the ideal output voltage as: VOUT = 2 x VREFL + (VREFH – VREFL) x D/4096 Where D = decimal equivalent of the binary code that is loaded to the DAC register which can range from 0 to 4095. To Output Amplifier VREFH R R R On power up, the internal register is cleared and the DAC channel is updated with zero-scale voltage. The DAC output remains in this state until valid data is written. This is particularly useful in applications where it is important to know the state of the DAC output while the device is powering up. In order not to turn on ESD protection devices, VDD should be applied before any other pin is brought high. Power Down The DAC7551 has a flexible power-down capability. During a power-down condition, the user has flexibility to select the output impedance of the DAC. During power-down operation, the DAC can have either 1-kΩ, 100-kΩ, or Hi-Z output impedance to ground. R VREFL Figure 27. Typical Resistor String RESISTOR STRING The resistor string section is shown in Figure 27. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is specified monotonic. OUTPUT BUFFER AMPLIFIERS The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a half-scale settling time of 3 µs with the output unloaded. 14 It is recommended to use a buffered reference in the external circuit (e.g., REF3140). The input impedance is typically 100 kΩ. Asynchronous Clear The DAC7551 output is asynchronously set to zero-scale voltage immediately after the CLR pin is brought low. The CLR signal resets all internal registers and therefore behaves like the Power-On Reset. The DAC7551 updates at the first rising edge of the SYNC signal that occurs after the CLR pin is brought back to high. SERIAL INTERFACE The DAC7551 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. In order to initialize the serial interface for the next update, the DAC7551 requires a falling SCLK edge after the rising SYNC. 16-Bit Word and Input Shift Register The input shift register is 16 bits wide. DAC data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK, as shown in the Figure 1 timing diagram. The 16-bit word, illustrated in Table 1, consists of four control bits followed by 12 bits of DAC data. The data format is straight binary DAC7551 www.ti.com SLAS441 – MARCH 2005 The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. The SPI interface is enabled after SYNC becomes low and the data is continuously shifted into the shift register at each falling edge of SCLK. When SYNC is brought high the last 16 bits stored in the shift register get latched into the DAC register, and the DAC updates. Daisy-Chain Operation Serial Data Output (SDO) pin is provided to daisy-chain multiple DAC7551 devices in a system. As long as SYNC is high the SDO pin is in a high-impedance state. When SYNC is brought low the output of the internal shift register is tied to the SDO pin. As long as SYNC is low, at each falling edge of SCLK, SDO duplicates SDIN signal with a 16-cycle delay. To support multiple devices in a daisy chain, SCLK and SYNC signals are shared across all devices, and SDO of one DAC7551 should be tied to the SDIN of the next DAC7551. For n devices in such a daisy chain, 16n SCLK cycles are required to shift the entire input data stream. After 16n SCLK falling edges are received following a falling SYNC, the data stream becomes complete, and SYNC can be brought high to update n devices simultaneously. SDO operation is specified at a maximum SCLK speed of 10 MHz. INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7551 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. GLITCH ENERGY The DAC7551 uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches are so low, they are usually buried within the wide-band noise and cannot be easily detected. The DAC7551 glitch is typically well under 0.1 nV-s. Such low glitch energy provides more than 10X improvement over industry alternatives. APPLICATION INFORMATION Waveform Generation Due to its exceptional linearity and low glitch, the DAC7551 is well suited for waveform generation (from DC to 10 kHz). The DAC7551 large-signal settling time is 5 µs, supporting an update rate of 200 KSPS. However, the update rates can exceed 1 MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, REF3140 (4.096 V) or REF02 (5.0 V) are recommended for reference voltage generation. Generating ±5-V, ±10-V, and ±12-V Outputs For Precision Industrial Control Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. Loop Accuracy: In a control loop, the ADC has to be accurate. Offset, gain, and the integral linearity errors of the DAC are not factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step determines the minimum incremental change the loop can generate. A DNL error less than –1 LSB (non-monotonicity) can create loop instability. A DNL error greater than +1 LSB implies unnecessarily large voltage steps and missed voltage targets. With high DNL errors, the loop loses its stability, resolution, and accuracy. Offering 12-bit ensured monotonicity and ± 0.08 LSB typical DNL error, 755X DACs are great choices for precision control loops. Loop Speed: Many factors determine control loop speed. Typically, the ADC's conversion time, and the MCU's computation time are the two major factors that dominate the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop 15 PRODUCT PREVIEW with all zeroes corresponding to 0-V output and all ones corresponding to full-scale output (VREF – 1 LSB). Data is loaded MSB first (Bit 15) where the first two bits (DB15 and DB14) are don't care bits. Bit 13 and bit 12 (DB13 and DB12) determine either normal mode operation or power-down mode (see Table 1). DAC7551 www.ti.com SLAS441 – MARCH 2005 down only during the start-up. Once the loop reaches its steady-state operation, these errors do not affect loop speed any further. Depending on the ringing characteristics of the loop's transfer function, DAC glitches can also slow the loop down. With its 1 MSPS (small-signal) maximum data update rate, DAC7551 can support high-speed control loops. Ultralow glitch energy of the DAC7551 significantly improves loop stability and loop settling time. Generating Industrial Voltage Ranges: For control loop applications, DAC gain and offset errors are not important parameters. This could be exploited to lower trim and calibration costs in a high-voltage control circuit design. Using a quad operational amplifier (OPA4130), and a voltage reference (REF3140), the DAC7551 can generate the wide voltage swings required by the control loop. PRODUCT PREVIEW REF3140 R2 VREF DAC7551 _ Vdac + VOUT OPA4130 Figure 28. Low-cost, Wide-swing Voltage Generator for Control Loop Applications The output voltage of the configuration is given by: 16 (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a single DAC7551 could be used to set the required offset voltages. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated. One DAC7551 can provide the Vtail voltages, while four additional DAC7551 devices can provide Vdac voltages to generate four high-voltage outputs. A single SPI interface is sufficient to control all five DAC7551 devices in a daisy-chain configuration. For ±5-V operation: R1 = 10 kΩ, R2 = 15 kΩ, Vtail = 3.33 V, VREF = 4.096 V For ±12-V operation: R1 = 10 kΩ, R2 = 49 kΩ, Vtail = 2.45 V, VREF = 4.096 V R1 VREFH For ±10-V operation: R1 = 10 kΩ, R2 = 39 kΩ, Vtail = 2.56 V, VREF = 4.096 V Vtail DAC7551 V out V REF R2 1 Din V tail R2 4096 R1 R1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC7551IDRNR PREVIEW SON DRN 12 250 TBD Call TI Call TI DAC7551IDRNT PREVIEW SON DRN 12 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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