a 12-Bit Serial Input Multiplying D/A Converter DAC8043A FUNCTIONAL BLOCK DIAGRAM FEATURES Compact SO-8 and TSSOP Packages True 12-Bit Accuracy +5 V Operation @ <10 A Fast 3-Wire Serial Input Fast 1 s Settling Time 2.4 MHz 4-Quadrant Multiply BW Pin-for-Pin Upgrade for DAC8043 Standard and Rotated Pinout DAC8043A VDD VREF LD DAC REG 12 GND CLK SRI 12-BIT SHIFT REGISTER 0.5 GENERAL DESCRIPTION The circuit consists of a 12-bit serial-in/parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the D/A converter. IOUT DAC 12 APPLICATIONS Ideal for PLC Applications in Industrial Control Programmable Amplifiers and Attenuators Digitally Controlled Calibration and Filters Motion Control Systems 0.4 0.3 TA = +258C, +858C, –408C VDD = +5V VREF = –10V 0.2 INL – LSB The DAC8043A is an improved high accuracy 12-bit multiplying digital-to-analog converter in space-saving 8-lead packages. Featuring serial input, double buffering and excellent analog performance, the DAC8043A is ideal for applications where PC board space is at a premium. Improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. RFB 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 Figure 1. Integral Nonlinearity Error vs. Code Consuming only 10 µA from a single +5 V power supply, the DAC8043A is the ideal low power, small size, high performance solution to many application problems. The DAC8043A is specified over the extended industrial (–40°C to +85°C) temperature range. DAC8043A is available in plastic DIP, and the low profile 1.75 mm height SO-8 surface mount packages. The DAC8043AFRU is available for ultracompact applications in a thin 1.1 mm TSSOP-8 package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 DAC8043A–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ VDD = +5 V, VREF = +10 V, –40ⴗC < TA < +85ⴗC, unless otherwise noted.) Parameter Symbol Condition E Grade F Grade Units STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error1 N INL DNL GFSE 12 ± 0.5 All Grades Monotonic to 12 Bits ± 0.5 TA = +25°C, Data = FFFH ± 1.0 ± 2.0 TA = –40°C, +85°C, Data = FFFH IOUT Pin Measured ±5 Data = 000H, IOUT Pin Measured ±5 TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured ± 25 Data = 000H 0.03 TA = –40°C, +85°C, Data = 000H 0.15 12 ± 1.0 ± 1.0 ± 2.0 ± 2.0 ±5 ±5 ± 25 0.03 0.15 Bits LSB max LSB max LSB max LSB max ppm/°C max nA max nA max LSB max LSB max Gain Tempco2 Output Leakage Current TCGFS ILKG Zero-Scale Error3 IZSE REFERENCE INPUT Input Resistance Input Capacitance2 RREF CREF Absolute Tempco < 50 ppm/°C 7/15 5 7/15 5 kΩ min/max pF typ ANALOG OUTPUT Output Capacitance2 COUT Data = 000H Data = FFFH 25 30 25 30 pF typ pF typ DIGITAL INPUTS Digital Input Low Digital Input High Input Leakage Current Input Capacitance2 VIL VIH IIL CIL VLOGIC = 0 V to +5 V VLOGIC = 0 V 0.8 2.4 0.001/± 1 10 0.8 2.4 0.001/± 1 10 V max V min µA typ/max pF max INTERFACE TIMING 2, 4 Data Setup Data Hold Clock Width High Clock Width Low Load Pulsewidth LSB CLK to LD DAC tDS tDH tCH tCL tLD tASB 10 5 25 25 25 0 10 5 25 25 25 0 ns min ns min ns min ns min ns min ns min AC CHARACTERISTICS 1, 2 Output Current Settling Time DAC Glitch Feedthrough (VOUT/VREF) Total Harmonic Distortion Output Noise Density5 Multiplying Bandwidth tS Q FT THD en BW To ± 0.01% of Full Scale, Ext Op Amp OP42 Data = 000H to FFFH to 000H, VREF = 0 V VREF = 20 V p-p, Data = 000 H, f = 10 kHz VREF = 6 V rms, Data = FFFH, f = 1 kHz 10 Hz to 100 kHz Between R FB and IOUT –3 dB, VOUT/VREF, VREF = 100 mV rms, Data = FFFH 1 20 1 –85 17 2.4 1 20 1 –85 17 2.4 µs max nVs max mV p-p dB typ nV/√Hz max MHz typ SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity VDD RANGE IDD PDISS PSS VLOGIC = 0 V or VDD VLOGIC = 0 V or VDD ∆VDD = ± 5% 4.5/5.5 10 50 0.002 4.5/5.5 10 50 0.002 V min/max µA max µW max %/% max NOTES 1 Using internal feedback resistor R FB, see Figure 19 test circuit with V REF = +10 V. 2 These parameters are guaranteed by design and not subject to production testing. 3 Calculated from worst case R REF: IZSE(LSB) = (R REF × ILKG × 4096)/VREF. 4 All input control signals are specified with t R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 5 Calculation from e n = √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth. Specifications subject to change without notice. –2– REV. 0 DAC8043A PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS* VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V RFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VIOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA Thermal Resistance θJA 8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . 103°C/W 8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . 158°C/W TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . 240°C/W Maximum Junction Temperature (TJ max) . . . . . . . . +150°C Operating Temperature Range . . . . . . . . . . – 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C #(*) Name Function 1(7) VREF 2 (8) RFB 3 (1) IOUT 4 (2) GND 5 (3) LD 6 (4) SRI *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7 (5) CLK 8 (6) VDD *Note Pin numbers in parenthesis represent the rotated pinout of the DAC8043A1ES and DAC8043A1FS models. ORDERING GUIDE Model INL (LSB) Temp Package Description Package Option DAC8043AEP DAC8043AES DAC8043A1ES DAC8043AFP DAC8043AFS DAC8043A1FS DAC8043AFRU ± 0.5 ± 0.5 ± 0.5 ± 1.0 ± 1.0 ± 1.0 ± 1.0 8-Lead P-DIP 8-Lead SOIC 8-Lead SOIC 8-Lead P-DIP 8-Lead SOIC 8-Lead SOIC* TSSOP-8 N-8 SO-8 SO-8 N-8 SO-8 SO-8 RU-8 –40/+85°C –40/+85°C –40/+85°C –40/+85°C –40/+85°C –40/+85°C –40/+85°C DAC Reference Input Pin. Establishes DAC fullscale voltage. Constant input resistance versus code. Internal Matching Feedback Resistor. Connect to external op amp output. DAC Current Output, full-scale output 1 LSB less than reference input voltage –VREF. Analog and Digital Ground. Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low. See truth table for operation. 12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored. Clock Input, positive-edge clocks data into shift register. Positive Power Supply Input. Specified range of operation +5 V ± 10%. DAC8043AE/F PIN CONFIGURATIONS VREF 1 8 1 8 4 5 TSSOP-8 DAC8043A FRU NOTES The DAC8043A contains 346 transistors. The die size measures 70.3 mil × 57.1 mil, 4014 sq mil. *The DAC8043A1ES and DAC8043A1FS have a rotated pinout. TSSOP-8 Package Branding: Line 1: yww (data code: year, work week). Line 2: 8043A. VDD 7 CLK RFB 2 1 8 TOP VIEW IOUT 3 (Not to Scale) 6 SRI 4 5 GND 4 5 LD PDIP-8 DAC8043A EP/FP SO-8 DAC8043A ES/FS DAC8043A1E AND DAC8043A1F PIN CONFIGURATION (Rotated Pinout) IOUT 1 8 RFB GND 2 7 VREF TOP VIEW LD 3 (Not to Scale) 6 VDD SRI 4 5 CLK SO-8 DAC8043A1ES DAC8043A1FS CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE DAC8043A D11 SRI D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK t LD1 t ASB LD DATA LOADED MSB(D11) FIRST DAC REGISTER LOAD Dxx SRI t DS t DH t CL CLK t CH t LD LD tS FS 61 LSB ERROR BAND VOUT ZS Figure 2. Timing Diagram Table I. Control-Logic Truth Table CLK LD Serial Shift Register Function DAC Register Function u L L H L u Shift-Register-Data Advanced One Bit No Effect No Effect Latched Updated with Current Shift Register Contents Latched All Zeros NOTES u positive logic transition. The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the switches in the R-2R DAC ladder. Typical Performance Characteristics 35 30 50 SS = 200 UNITS TA = +258C VDD = +5V VREF = +10V SS = 200 UNITS TA = –408C TO +858C VDD = +5V VREF = +10V 40 FREQUENCY FREQUENCY 25 20 15 30 20 10 10 5 0 –1.0 –0.5 0.0 0.5 TOTAL UNADJUSTED ERROR – LSB 0 1.0 Figure 3. Total Unadjusted Error Histogram 0 1 FULL SCALE TEMPCO – ppm/8C 2 Figure 4. Full-Scale Output Tempco Histogram –4– REV. 0 DAC8043A 0.5 100 0.4 80 PSRR – dB SUPPLY CURRENT IDD – mA D VDD = +5V 610% TA = +258C VDD = +5V 0.3 0.2 60 40 0.1 0 0 0.5 1 1.5 2.5 3.5 2 3 LOGIC INPUT VOLTAGE – Volts 4 4.5 20 1k 5 Figure 5. Supply Current vs. Logic Input Voltage 100k FREQUENCY – Hz 10k 1M 10M Figure 8. Power Supply Rejection vs. Frequency 10 0.5 0.4 VDD = +5V VLOGIC = 0V OR VDD VDD = +5V VREF = +10V SUPERIMPOSED: TA = –408C, +258C, +858C 0.3 1 DNL – LSB IDD – mA 0.2 0.1 0.1 0 –0.1 –0.2 0.01 –0.3 –0.4 0.001 –55 –35 –15 5 25 45 65 TEMPERATURE – 8C 85 105 –0.5 125 512 1536 2048 2560 CODE – Decimal 1024 3072 3584 4096 Figure 9. Linearity Error vs. Digital Code Figure 6. Supply Current vs. Temperature 4 3500 3000 0 VDD = +5V VREF = +10V TA = +258C 2 2500 VDD = +5V VREF = +10V TA = +258C INL – LSB I DD – mA CODE = F55H 2000 1500 0 CODE = 800H 1000 –2 CODE = FFFH 500 0 1k 10k 100k 1M FREQUENCY – Hz 10M –4 –2000 100M Figure 7. Supply Current vs. Clock Frequency REV. 0 –1000 0 1000 OPAMP OFFSET VOS – mV 2000 Figure 10. Linearity Error vs. External Op Amp VOS –5– DAC8043A VDD = +5V TA = +258C 0.5 VDD = +5V VREF = +10V fCLK = 2.5MHz CODE: 7FFH TO 800H 0.25 INL – LSB VOUT (10mV/DIV) LD (5V/DIV) 0 –0.25 –0.5 20mV 5 0 10 | VREF| – Volts TIME – 200ns/DIV Figure 11. Midscale Transition Performance Figure 14. Linearity Error vs. Reference Voltage 1.2 NOMINAL CHANGE IN VOLTAGE – mV SAMPLE SIZE = 50 5V VDD = +5V VREF = +10V TA = +258C CLK (5V/DIV) VOUT (5V/DIV) 1.0 0.8 CODE = FFFH 0.6 0.4 CODE = 000H 0.2 5V 0 0 TIME – 1ms/DIV Figure 12. Large Signal Settling Time 600 72 THD – dB 60 ATTENUATION – dB 48 84 –75 0.018 –80 0.010 –85 0.0056 –90 0.0032 THD – % VREF = 4V p-p OUTPUT OP AMP: OP42 24 36 0.032 –70 12 DATA BITS "ON" (ALL OTHER DATA BITS "OFF") 200 300 400 500 HOURS OF OPERATION AT +1508C Figure 15. Long-Term Drift Accelerated by Burn-In 0 ALL BITS ON (MSB) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB) B0 100 96 100 1k 10k 100k FREQUENCY – Hz 1M 108 10M –95 10 Figure 13. Reference Multiplying Bandwidth vs. Frequency and Code 100 1k FREQUENCY – Hz 10k 0.0018 100k Figure 16. THD vs. Frequency –6– REV. 0 DAC8043A PARAMETER DEFINITIONS code. This constant current results in a constant input resistance at VREF equal to R. The VREF input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the Absolute Maximum Ratings. INTEGRAL NONLINEARITY (INL) This is the single most important DAC specification. ADI measures INL as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed as a percent of full-scale range or in terms of LSBs. Refer to Analog Devices Data Reference Manual for additional digital-to-analog converter definitions. 10kV 10kV 10kV VREF 20kV 20kV 20kV 20kV 20kV S1 S2 S3 S12 * INTERFACE LOGIC INFORMATION The DAC8043A has been designed for ease of operation. The timing diagram, Figure 2, illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Once the 12-bit input register is full, the data is transferred to the DAC register by taking LD momentarily low. GND 10kV * BIT 2 BIT 3 BIT 12 (LSB) DIGITAL INPUTS (SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH") *THESE SWITCHES PERMANENTLY "ON" The DAC8043A’s digital inputs, SRI, LD, and CLK, are TTL compatible. The input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (VIN) passes through the transition region. See the Supply Current vs. Logic Input Voltage graph located in the typical performance characteristics curves. Maintaining the digital input voltage levels as close as possible to the supplies, VDD and GND, minimizes supply current consumption. The DAC8043A’s digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 17 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. Figure 18. Simplified DAC Circuit The twelve output current steering NMOS FET switches are in series with each R-2R resistor. To further ensure accuracy across the full temperature range, permanently “ON” MOS switches were included in series with the feedback resistor and the R-2R ladder’s terminating resistor. Figure 18 shows the location of the series switches. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn “ON” these series switches. DYNAMIC PERFORMANCE OUTPUT IMPEDANCE The DAC8043A’s output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT terminal, may be between 10 kΩ (the feedback resistor alone when all digital inputs are LOW) and 7.5 kΩ (the feedback resistor in parallel with approximate 30 kΩ of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. VDD 5kV APPLICATIONS INFORMATION GND In most applications, linearity depends upon the potential of the IOUT and GND pins being at the same voltage potential. The DAC is connected to an external precision op amp inverting input. The external amplifiers noninverting input should be tied directly to ground without the usual bias current compensating resistor. (See Figures 19 and 20.) The selected amplifier should have a low input bias current and low drift over temperature. The amplifiers input offset voltage should be nulled to less than 200 microvolts (less than 10% of 1 LSB). All grounded pins should tie to a single common ground point to avoid ground loops. The VDD power supply should have a low noise level with adequate bypassing. It is best to operate the DAC8043A from the analog power supply and grounds. Figure 17. Digital Input Protection GENERAL CIRCUIT INFORMATION The DAC8043A is a 12-bit multiplying D/A converter with a very low temperature coefficient. It contains an R-2R resistor ladder network, data input and control logic, and two data registers. The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. The analog portion of the DAC8043A contains an inverted R-2R ladder network consisting of silicon-chrome, highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs of NMOS current-steering switches, see Figure 18. These switches steer binarily weighted currents into either IOUT or GND; this yields a constant current in each ladder leg, regardless of digital input REV. 0 RFEEDBACK BIT 1 (MSB) DIGITAL SECTION LD, CLK, SRI IOUT –7– DAC8043A The most straightforward application of the DAC8043A is in the 2-quadrant multiplying configuration shown in Figure 19. If the reference input signal is replaced with a fixed dc voltage reference, the DAC output will provide a proportional dc voltage output according to the transfer equation: VOUT = –D/4096 × VREF VOUT2 = (D/2048 – 1) × –VREF where D is the decimal data loaded into the DAC register and VREF is the externally applied reference voltage source. where D is the decimal data loaded into the DAC register and VREF is the externally applied reference voltage source. Precision resistors will be necessary to avoid ratio errors. Otherwise trimming will be required to achieve full accuracy specifications available from the DAC8043A device. See the various Analog Devices Digital Potentiometer products for automated trimming solutions (e.g., the AD5204 for low voltage applications or the AD7376 for high voltage applications). VDD VREF RFB R 2R 610VP VAC RFB 10pF 2R IOUT OP77 VOUT C3499–8–1/99 The negative full-scale voltage will be VREF when the DAC is loaded with all zeros. The positive full-scale output will be –(VREF – 1 LSB) when the DAC is loaded with all ones. Thus the digital coding is offset binary. The voltage output transfer equation for various input data and reference (or signal) values follows: UNIPOLAR 2-QUADRANT MULTIPLYING GND DIGITAL INPUTS OMITTED FOR CLARITY VDD VREF Figure 19. Unipolar (2-Quadrant) Operation BIPOLAR 4-QUADRANT MULTIPLYING 2R RFB 2R VAC 20kV 610VP Figure 20 shows a suggested circuit to achieve 4-quadrant multiplying operation. The summing amplifier multiplies VOUT1 by 2, and offsets the output with the reference voltage so that a midscale digital input code of 2048 places VOUT2 at zero volts. 20kV RFB R 10pF IOUT 10kV OP213 VOUT1 OP213 GND DIGITAL INPUTS OMITTED FOR CLARITY VOUT2 (0V TO –VREF) Figure 20. Bipolar (4-Quadrant) Operation OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC SEATING PLANE 4 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 5 1 0.015 (0.381) 0.008 (0.204) 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. PIN 1 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 8 8-Lead TSSOP (RU-8) 0.122 (3.10) 0.114 (2.90) 8 1 5 0.256 (6.50) 0.246 (6.25) 4 0.177 (4.50) 0.169 (4.30) 1 0.1574 (4.00) 0.1497 (3.80) 4 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) SEATING 0.0075 (0.19) PLANE 0.0433 (1.10) MAX 88 08 0.0079 (0.20) 0.0035 (0.090) –8– 0.028 (0.70) 0.020 (0.50) REV. 0