Dual, Current-Output, Serial-Input, 16-/14-Bit DAC AD5545/AD5555 FEATURES 16-bit resolution AD5545 14-bit resolution AD5555 ±1 LSB DNL monotonic ±2 LSB INL AD5545 2 mA full-scale current ±20%, with VREF = 10 V 0.5 µs settling time 2Q multiplying reference-input 4 MHz BW Zero or midscale power-up preset Zero or midscale dynamic reset 3-wire interface Compact TSSOP-16 package FUNCTIONAL BLOCK DIAGRAM VREFA VREFB 16 OR 14 VDD RFBA D0..DX INPUT REGISTER SDI DAC A REGISTER R R IOUTA DAC A AGNDA RFBB CS INPUT REGISTER EN CLK DAC B REGISTER R R IOUTB DAC B AGNDB DAC A B ADDR DECODE POWERON RESET DGND RS MSB AD5545/ AD5555 LDAC 02918-0- 001 Figure 1. APPLICATIONS Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs Programmable attentuator PRODUCT OVERVIEW The AD5545/AD5555 are 16-bit/14-bit, current-output, digitalto-analog converters designed to operate from a single 5 V supply with bipolar output up to ±15 V capability. An external reference is needed to establish the full-scale output-current. An internal feedback resistor (RFB) enhances the resistance and temperature tracking when combined with an external op amp to complete the I-to-V conversion. A serial data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). Additional LDAC function allows simultaneous update operation. The internal reset logic allows power-on preset and dynamic reset at either zero or midscale, depending on the state of the MSB pin. The AD5545/AD5555 are packaged in the compact TSSOP-16 package and can be operated from –40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD5545/AD5555 TABLE OF CONTENTS AD5545/AD5555—Electrical Characteristics .............................. 3 Applications..................................................................................... 13 Absolute Maximum Ratings............................................................ 5 Stability ........................................................................................ 13 Pin Configuration And Functional Descriptions......................... 6 Positive Voltage Output ............................................................. 13 Typical Performance Characteristics ............................................. 9 Bipolar Output............................................................................ 13 Circuit Operation ........................................................................... 11 Programmable Current Source ................................................ 13 D/A Converter Section .............................................................. 11 DAC with Programmable Input Reference Range................ 14 Serial Data Interface................................................................... 11 Outline Dimensions ....................................................................... 16 Power-Up Sequence ................................................................... 12 ESD Caution................................................................................ 16 Layout and Power Supply Bypassing ....................................... 12 Ordering Guide .......................................................................... 16 Grounding ................................................................................... 12 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD5545/AD5555 AD5545/AD5555—ELECTRICAL CHARACTERISTICS Table 1. VDD = 5 V ± 10%, IOUT = Virtual GND, GND = 0 V, VREF = 10 V, TA = Full Operating Tempearture Range, unless otherwise noted. Parameter STATIC PERFORMANCE1 Resolution Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity Output Leakage Current Output Leakage Current Full-Scale Gain Error Full-Scale Temperature Coefficient2 REFERENCE INPUT VREF Range Input Resistance Input Capacitance2 ANALOG OUTPUT Symbol Conditions 5 V ± 10% Units N N INL INL DNL IOUT IOUT GFSE TCVFS AD5545, 1 LSB = VREF/216 = 153 µV when VREF = 10 V AD5555, 1 LSB = VREF/214 = 610 µV when VREF = 10 V AD5545 AD5555 Monotonic Data = 0x0000, TA = 25°C Data = 0x0000, TA = TA Max Data = Full Scale 16 14 ±2 ±1 ±1 10 20 ±1/±4 1 Bits Bits LSB max LSB max LSB max nA max nA max mV typ/max ppm/°C typ –12/+12 5 5 V min/V max kΩ typ3 pF typ 2 200 mA typ pF typ VREF RREF CREF Output Current Output Capacitance2 LOGIC INPUTS AND OUTPUT IOUT COUT Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance2 INTERFACE TIMING2, 4 Clock Input Frequency Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Data Setup Data Hold LDAC Setup Hold VIL VIH IIL CIL 0.8 2.4 10 10 V max V min µA max pF max fCLK tCH tCL tCSS tCSH tDS tDH tLDS 50 10 10 0 10 5 10 5 MHz ns min ns min ns min ns min ns min ns min ns min tLDH 10 ns min tLDAC 10 ns min 4.5/5.5 10 0.055 0.006 V min/V max µA max mW max %/% max LDAC Width SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity VDD Range IDD PDISS PSS Data = Full Scale Code Dependent Logic Inputs = 0 V Logic Inputs = 0 V ∆VDD = ±5% 1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an O42 I-to-V converter amplifier. 4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Rev. 0 | Page 3 of 16 AD5545/AD5555 Parameter AC CHARACTERISTICS Output Voltage Setting Time Reference Multiplying BW DAC Glitch Impulse Feedthrough Error Symbol tS BW Q VOUT/VREF Digital Feedthrough Total Harmonic Distortion Analog Crosstalk Q THD Output Spot Noise Voltage eN CTA Conditions To ±0.1% Full Scale, Data = Zero Scale to Full Scale to Zero Scale VREF = 5 V p-p, Data = Full Scale VREF = 0 V, Data = Zero Scale to Midscale to Zero Scale Data = Zero Scale, VREF = 100 mV rms, f = 1 kHz, Same Channel CS = Logic High and fCLK = 1 MHz VREF = 5 V p-p, Data = Full Scale, f = 1 kHz to 10 kHz VREFB = 0 V, Measure VOUTB with VREFA = 5 V p-p Sine Wave, Data = Full Scale, f = 1 kHz to 10 kHz f = 1 kHz, BW = 1 Hz Rev. 0 | Page 4 of 16 5 V ± 10% Units 0.5 µs typ 4 MHz typ 7 nV-s typ –65 dB 7 –85 nV-s typ dB typ –95 dB typ 12 nV/√Hz AD5545/AD5555 ABSOLUTE MAXIMUM RATINGS Table 2. AD5545/AD5555 Absolute Maximum Ratings Parameter VDD to GND VREF to GND Logic Inputs to GND V(IOUT) to GND Input Current to Any Pin except Supplies Package Power Dissipation Thermal Resistance θJA 16-Lead TSSOP Maximum Junction Temperature (TJ max) Operating Temperature Range Storage Temperature Range Lead Temperature RU-16 (Vapor Phase, 60 sec) RU-16 (Infrared, 15 sec) Rating –0.3 V, +8 V –18 V, +18 V –0.3 V, +8 V –0.3 V, VDD + 0.3 V ±50 mA (TJ max – TA)/ θJA 150°C/W 150°C –40°C to +85°C –65°C to +150°C 215°C 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 16 AD5545/AD5555 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS RFBA 1 16 CLK VREFA 2 15 LDAC IOUTA 3 AGNDA 4 AGNDB 5 IOUTB 6 14 MSB AD5545/ AD5555 TOP VIEW (Not to Scale) VREFB 7 13 VDD 12 DGND 11 CS 10 RS RFBB 8 9 SDI 02918- 0- 002 Figure 2. 16-Lead TSSOP Table 3. Pin Function Descriptions—16-Lead TSSOP Pin No. 1 2 Mnemonic RFBA VREFA 3 4 5 6 7 IOUTA AGNDA AGNDB IOUTB VREFB 8 9 10 RFBB SDI RS 11 CS 12 13 14 DGND VDD MSB 15 LDAC 16 CLK Function Establish voltage output for DAC A by connecting to external amplifier output. DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin. DAC A Current Output. DAC A Analog Ground. DAC B Analog Ground. DAC B Current Output. DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin. Establish voltage output for DAC B by connecting to external amplifier output. Serial Data Input. Input data loads directly into the shift register. RESET Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when MSB = 1. Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. This does not affect LDAC operation. Digital Ground Pin. Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%. MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system poweron. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied permanently to ground or VDD. Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 4 and Table 5 for operation. Clock Input. Positive edge clocks data into shift register. Rev. 0 | Page 6 of 16 AD5545/AD5555 SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 INPUT REG LD CLK tDS CS tDH tCH tCL tCSS tCSH LDAC tLDH tLDS tLDAC 02918- 0- 003 Figure 3. AD5545 18-Bit Data Word Timing Diagram SDI A1 A0 D13 D12 D11 D10 D09 D08 D1 D0 INPUT REG LD CLK tDS CS tDH tCH tCL tCSS tCSH LDAC tLDH tLDS tLDAC 02918- 0- 004 Figure 4. AD5555 16-Bit Data Word Timing Diagram Table 4. AD5545 Control Logic Truth Table CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register H L L X L ↑+ H H H H H H X X X Latched Latched Latched Latched Latched Latched L ↑+ H L H H H H X X No Effect No Effect Shift Register Data Advanced One Bit No Effect No Effect Latched Latched H H H H H X X X X X L H ↑+ H H H H H L L X X X 0 H No Effect No Effect No Effect No Effect No Effect Latched Selected DAC Updated with Current SR Current Latched Latched Latched Latched Data = 0x0000 Latched Data = 0x8000 NOTES 1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care. 2. At power-on, both the input register and the DAC register are loaded with all 0s. Rev. 0 | Page 7 of 16 Transparent Latched Latched Latched Data = 0x0000 Latched Data = 0x8000 AD5545/AD5555 Table 5. AD5555 Control Logic Truth Table CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register H L L X L ↑+ H H H H H H X X X Latched Latched Latched Latched Latched Latched L ↑+ H L H H H H X X No Effect No Effect Shift Register Data Advanced One Bit No Effect No Effect Latched Latched H H H H H X X X X X L H ↑+ H H H H H L L X X X 0 H No Effect No Effect No Effect No Effect No Effect Latched Selected DAC Updated with Current SR Current Latched Latched Latched Latched Data = 0x0000 Latched Data = 0x2000 Transparent Latched Latched Latched Data = 0x0000 Latched Data = 0x2000 NOTES 1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care. 2. At power-on, both the input register and the DAC register are loaded with all 0s. Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format Bit Position Data Word MSB B17 A1 B16 A0 B15 D15 B14 D14 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format Bit Position Data Word MSB B15 A1 B14 A0 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 8. Address Decode A1 0 0 1 1 A0 0 1 0 1 DAC Decoded None DAC A DAC B DAC A and DAC B Rev. 0 | Page 8 of 16 AD5545/AD5555 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 8192 –1.0 16384 24576 32768 40960 49152 57344 65536 CODE (Decimal) 0 0248 4096 6144 8192 10240 12288 14336 16384 CODE (Decimal) 02918- 0- 009 02918- 0- 012 Figure 5. AD5545 Integral Nonlinearity Error Figure 8. AD5555 Differential Nonlinearity Error 1.0 1.5 VREF = 2.5V TA = 25°C 0.8 1.0 LINEARITY ERROR (LSB) 0.6 DNL (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 0.5 INL 0 DNL –0.5 –1.0 GE –0.8 –1.0 0 8192 –1.5 16384 24576 32768 40960 49152 57344 65536 CODE (Decimal) 2 4 02918- 0- 010 Figure 6. AD5545 Differential Nonlinearity Error 10 02918- 0- 013 Figure 9. Linearity Errors vs. VDD 5 1.0 VDD = 5V TA = 25°C 0.8 SUPPLY CURRENT IDD (LSB) 0.6 0.4 INL (LSB) 6 8 SUPPLY VOLTAGE VDD (V) 0.2 0 –0.2 –0.4 –0.6 4 3 2 1 –0.8 –1.0 0 2048 4096 0 6144 8192 10240 12288 14336 16384 CODE (Decimal) 02918- 0- 011 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LOGIC INPUT VOLTAGE VIH (V) 4.5 Figure 10. Supply Current vs. Logic Input Voltage Figure 7. AD5555 Integral Nonlinearity Error Rev. 0 | Page 9 of 16 5.0 02918- 0- 014 AD5545/AD5555 3.0 SUPPLY CURRENT (mA) 2.5 CS 2.0 0x5555 1.5 0x8000 1.0 0xFFFF 0x0000 0.5 0 10k 100k VOUT 1M 10M CLOCK FREQUENCY (Hz) 100M 02918- 0- 018 02918- 0- 015 Figure 14. Settling Time Figure 11. Supply Current vs. Clock Frequency 90 VDD = 5V ± 10% VREF = 10V 80 70 CS (5V/DIV) PSSR (-dB) 60 VDD = 5V VREF = 10V CODES 0x8000 ↔ 0x7FFF 50 40 30 VOUT (50mV/DIV) 20 10 0 10 100 1k 10k FREQUENCY (Hz) 100k 0 1M /DIV 12.000dB MARKER 4 41 677.200Hz MAG (A/R) –2.939db –12dB –24dB –36dB –48dB –60dB –72dB –84dB –96dB –108dB 0x0000 10 100 START 10.000Hz 1k 10k 1.5 2.0 2.5 3.0 TIME (µs) 3.5 4.0 4.5 5.0 Figure 15. Midscale Transition and Digital Feedthrough Figure 12. Power Supply Rejection Ration vs. Frequency REF LEVEL 0.000dB 1.0 02918- 0- 019 02918- 0- 016 0xFFFF 0x8000 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0.5 100k 1M 10M STOP 50 000 000.000Hz 02918- 0- 017 Figure 13. Reference Multiplying Bandwidth Rev. 0 | Page 10 of 16 AD5545/AD5555 CIRCUIT OPERATION The DAC architecture uses a current-steering R-2R ladder design. Figure 16 shows the typical equivalent DAC. The DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFB pin is connected to the output of the external amplifier. The IOUT terminal is connected to the inverting input of the external amplifier. These DACs are designed to operate with both negative or positive reference voltages. The VDD power pin is used only by the logic to drive the DAC switches ON and OFF. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users attempt to measure the RFB value, power must be applied to VDD to achieve continuity. The VREF input voltage and the digital data (D) loaded into the corresponding DAC register, according to Equation 1 and Equation 2, determine the DAC output voltage. VOUT = –VREF × D / 65,536 (1) VOUT = –VREF × D /16,384 (2) Note that the output full-scale polarity is the opposite of the VREF polarity for dc reference voltages. VDD R VREF 2R R 2R 2R 2.500V R RFB R 5kΩ S2 S1 IOUT GND DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED 02918- 0- 005 Figure 16. Equivalent R-2R DAC Circuit These DACs are also designed to accommodate ac reference input signals. The AD5545/AD5555 will accommodate input reference voltages in the range of –12 V to +12 V. The reference voltage inputs exhibit a constant nominal input-resistance value of 5 kΩ, ±30%. The DAC output (IOUT) is code dependent, producing various output resistances and capacitances. When choosing an external amplifier, the user should take into account the variation in impedance generated by the AD5545/AD5555 on the amplifiers inverting input node. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise. VOUT ADR03 GND VDD R VREFA D/A CONVERTER SECTION 5V VIN The AD5545/AD5555 contain a 16-/14-bit, current-output, digital-to-analog converter, a serial-input register, and a DAC register. Both parts require a minimum of a 3-wire serial data interface with additional LDAC for dual channel simultaneous update. 2R R 2R 2R R RFBA R 5kΩ S2 +3V S1 IOUTA VCC VOUT AD8628 VEE AD5545/AD5555 –3V LOAD AGNDA DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED 02918- 0- 006 Figure 17. Recommended System Connections SERIAL DATA INTERFACE The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK) serial data interface for single channel update operation. With Table 4 as an example (AD5545), users can tie LDAC low and RS high, then pull CS low for an 18-bit duration. New serial data is then clocked into the serial-input register in an 18-bit dataword format with the MSB bit loaded first. Table 5 defines the truth table for the AD5555. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK. For the AD5545, only the last 18-bits clocked into the serial register will be interrogated when the CS pin is strobed high, transferring the serial register data to the DAC register and updating the output. If the applied microcontroller outputs serial data in different lengths than the AD5545, such as 8-bit bytes, three right justified data bytes can be written to the AD5545. The AD5545 will ignore the six MSB and recognize the 18 LSB as valid data. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register and updates the output; during the CS strobe, the CLK should not be toggled. If users want to program each channel separately but update them simultaneously, they need to program LDAC and RS high initially, then pull CS low for an 18-bit duration and program DAC A with the proper address and data bits. CS is then pulled high to latch data to the DAC A register. At this time, the output is not updated. To load DAC B data, pull CS low for an 18-bit duration and program DAC B with the proper address and data, then pull CS high to latch data to the DAC B register. Finally, pull LDAC low and then high to update both the DAC A and DAC B outputs simultaneously. Rev. 0 | Page 11 of 16 AD5545/AD5555 Table 8 shows that each DAC A and DAC B can be individually loaded with a new data value. In addition, a common new data value can be loaded into both DACs simultaneously by setting Bit A1 = A0 = high. This command enables the parallel combination of both DACs, with IOUTA and IOUTB tied together, to act as one DAC with significant improved noise performance. LAYOUT AND POWER SUPPLY BYPASSING ESD Protection Circuits Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at VDD to minimize any transient disturbance and to filter any low frequency ripple (see Figure 19). Users should not apply switching regulators for VDD due to the power supply rejection ratio degradation over frequency. All logic input pins contain back-biased ESD protection Zeners connected to digital ground (DGND) and VDD as shown in Figure 18. VDD DIGITAL INPUTS 5kΩ It is a good practice to employ compact, minimum lead length layout design. The input leads should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. DGND AD5545/ AD5555 02918- 0- 007 VDD C2 Figure 18. Equivalent ESD Protection Circuits POWER-UP SEQUENCE It is recommended to power-up VDD and ground prior to any reference voltages. The ideal power-up sequence is AGNDX, DGND, VDD, VREFX, and digital inputs. A noncompliance powerup sequence can elevate reference current, but the device will resume normal operation once VDD is powered. + C1 10µF VDD 0.1µF AGNDX DGND 02918- 0- 008 Figure 19. Power Supply Bypassing and Grounding Connection GROUNDING The DGND and AGNDX pins of the AD5545/AD5555 refer to the digital and analog ground references. To minimize the digital ground bounce, the DGND terminal should be joined remotely at a single point to the analog ground plane (see Figure 19). Rev. 0 | Page 12 of 16 AD5545/AD5555 circuit, the second amplifier, U4, provides a gain of +2, which increases the output span magnitude to 5 V. Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created because the input data (D) is incremented from code zero (VOUT = –2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT = +2.5 V). APPLICATIONS STABILITY VDD U1 VDD VREF C1 RFB VREF IOUT VO AD8628 GND AD5545/AD5555 U2 02918- 0- 020 VOUT = (D / 32,768 – 1) × VREF ( AD5545) (3) VOUT = (D /16,384 – 1) × VREF ( AD5555) (4) Figure 20. Operational Compensation Capacitor for Gain Peaking Prevention In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP, and if there is excessive parasitic capacitance at the inverting node. An optional compensation capacitor, C1, can be added for stability as shown in Figure 20. C1 should be found empirically, but 20 pF is generally more than adequate for the compensation. For the AD5545, the external resistance tolerance becomes the dominant error that users should be aware of. R1 10kΩ±0.01% 10kΩ±0.01% C2 ADR03 U4 ADR03 5V 1/2 V+ AD8620 V– GND +5V U3 –2.5V U1 VDD VREF R3 U1 VDD RFB VOUT VIN VREF GND GND C1 RFB IOUT GND 1/2 AD8628 VO C1 IOUT AD5545/AD5555 U2 VO 1/2 V+ AD8620 V– 1/2 AD8620 U2 –5V –2.5 < VO < +2.5 02918- 0- 022 Figure 22. Four-Quadrant Multiplying Application Circuit PROGRAMMABLE CURRENT SOURCE Figure 23 shows a versatile V-to-I conversion circuit using improved Howland Current Pump. In addition to the precision current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit can be used in a 4 mA to 20 mA current transmitter with up to a 500 Ω of load. In Figure 23, it shows that if the resistor network is matched, the load current is ( R 2 + R3 ) –5V AD5545/AD5555 +5V 5kΩ±0.01% U3 VOUT VIN +5V U4 +5V POSITIVE VOLTAGE OUTPUT To achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistors’ tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and –2.5 V, respectively (see Figure 21). R2 IL = 0 < VO < +2.5 R1 R3 × VREF × D (5) 02918- 0- 021 Figure 21. Positive Voltage Output Configuration BIPOLAR OUTPUT The AD5545/AD5555 is inherently a 2-quadrant multiplying D/A converter. It can easily set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage. R3, in theory, can be made small to achieve the current needed within the U3 output current driving capability. This circuit is versatile such that the AD8510 can deliver ±20 mA in both directions, and the voltage compliance approaches 15 V, which is mainly limited by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished by using an additional external amplifier, U4, configured as a summing amplifier (see Figure 22). In this Rev. 0 | Page 13 of 16 ZO = R1′R3( R1 + R2 ) R1(R2′ + R3′) – R1′( R2 + R3) (6) AD5545/AD5555 If the resistors are perfectly matched, ZO is infinite, which is desirable, and the resistors behave as an ideal current source. On the other hand, if they are not matched, ZO can be either positive or negative. The latter can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically but typically falls in the range of a few pF. RWB and RWA are digital potentiometer 128-step programmable resistances and are given by U1 VDD RFB VREF DC RAB 128 (8) RWA ≈ 128 − DC RAB 128 (9) DC RWB ≈ RWA 128 − DC VDD VREF RWB ≈ IOUT AD8628 GND AD5545/AD5555 where DC = Digital Potentiometer Digital Code in Decimal (0 ≤ DC ≤ 127). R1' R2' 150kΩ 15kΩ By putting Equations 7 through 10 together, the following results: C1 10pF U2 VDD R3' 50Ω U3 DC 1 + 128 − D C VREF AB = VREF × DC D 1 − NA × 128 − DC 2 V+ AD8510 V– R3 50Ω VSS R1 150kΩ VL R2 15kΩ LOAD IL 02918- 0- 023 Figure 23. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities DAC WITH PROGRAMMABLE INPUT REFERENCE RANGE Since high voltage references can be costly, users may consider using one of the DACs, a digital potentiometer, and a low voltage reference to form a single-channel DAC with a programmable input reference range. This approach optimizes the programmable range as well as facilitates future system upgrades with just software changes. Figure 24 shows this implementation. VREFAB is in the feedback network, therefore, R D R VREF AB = VREF × 1 + WB – – VREF_AB × NA × WB (7) RWA RWA 2 where: VREFAB = Reference Voltage of VREFA and VREFB (10) (11) Table 9 shows a few examples of VREFAB of the 14-bit AD5555. Table 9. VREFAB vs. DB and DC of the AD5555 DC 0 32 32 64 64 96 96 DA X 0 8192 0 8192 0 8192 VREFAB VREF 1.33 VREF 1.6 VREF 2 VREF 4 VREF 4 VREF –8 VREF The output of DAC B is, therefore, VOB = −VREF AB DB 2N (12) where DB is the DAC B digital code in decimal. The accuracy of VREFAB will be affected by the matching of the input and feedback resistors and, therefore, a digital potentiometer is used for U4 because of its inherent resistance matching. The AD7376 is a 30 V or ±15 V, 128-step digital potentiometer. If 15 V or ±7.5 V is adequate for the application, a 256-step AD5260 digital potentiometer can be used instead. VREF = External Reference Voltage DA = DAC A Digital Code in Decimal N = Number of Bits of DAC Rev. 0 | Page 14 of 16 AD5545/AD5555 +5V C1 +15V VDD RFBA IOUTA VREFA U1A AGNDA V+ A OP4177 V– U2A +15V –15V 2 AD7376 U4 W B C2 2.2p U3 VIN 3 AD5555 5 TEMP TRIM 6 VOUT GND 4 VREF OP4177 VREF_AB U2C ADR03 C3 RFBB VREFB POT IOUTB U1B AGNDB OP4177 V OB U2B 02918- 0- 024 Figure 24. DAC with Programmable Input Reference Range Rev. 0 | Page 15 of 16 AD5545/AD5555 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE AD5545/AD5555 Products AD5545BRU* AD5545BRU–REEL7 AD5555CRU AD5555CRU–REEL7 INL LSB ±2 ±2 ±1 ±1 DNL LSB ±1 ±1 ±1 ±1 RES (Bits) 16 16 14 14 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C *The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C02918-0-7/03(0) Rev. 0 | Page 16 of 16 Package Description TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 Package Outline RU–16 RU–16 RU–16 RU–16 Qty 96 1000 96 1000