16 Megabit High Speed CMOS SRAM DPS1MX16MKn3 SLCC Stack DESCRIPTION: The DPS1MX16MKn3 High Speed SRAM ‘’STACK’’ modules are a revolutionary new memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC). Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages. The module packs 16-Megabits of low-power CMOS static RAM in an area as small as 0.549 in2, while maintaining a total height as low as 0.269 inches. The DPS1MX16MKn3 STACK modules contain four individual 512K x 8 SRAMs, each packaged in a hermetically sealed SLCC, making the modules suitable for commercial, industrial and military applications. Straight Leaded Stack By using SLCCs, the ‘’Stack’’ family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. FEATURES: • Organizations Available: 1Meg x 16 or 2 Meg x 8 • Access Times: 20*, 25, 30, 35, 45ns • Fully Static Operation • • • • • - No clock or refresh required Single +5V Power Supply, ±10% Tolerance TTL Compatible Common Data Inputs and Outputs Low Data Retention Voltage: 2.0V min. Packages Available: SLCC Stack Straight Leaded Stack ‘’J’’ Leaded Stack Gullwing Leaded Stack ‘’J’’ Leaded Stack Gullwing Leaded Stack * Commercial and Industrial Grade only. FUNCTIONAL BLOCK DIAGRAM PIN NAMES A0 - A18 I/O0 - I/O15 CE0 - CE3 WE OE0, OE1 VDD VSS N.C. 30A129-04 REV. E This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. This Material Copyrighted By Its Respective Manufacturer Address Inputs Data Input/Output Low Chip Enables Write Enable Output Enables Power (+5V) Ground No Connect 1 DPS1MX16MKn3 Dense-Pac Microsystems, Inc. TRUTH TABLE PIN-OUT DIAGRAM Mode CE WE OE Not Selected DOUT Disable Read Write H L L L X H H L X H L X H = HIGH Supply I/O Pin Current High-Z Standby High-Z Active DOUT Active DIN Active L = LOW X = Don’t Care ABSOLUTE MAXIMUM RATINGS Symbol TSTC TBIAS VDD VI/O 3 Parameter Value Storage Temperature -65 to +150 Temperature Under Bias -55 to +125 Supply Voltage 1 -0.5 to +7.0 Input/Output Voltage 1 -0.5 to VDD+0.5 RECOMMENDED OPERATING RANGE CAPACITANCE 4: TA = 25°C, F = 1.0MHz Symbol CADR CCE CWE COE CI/O Parameter Address Input Chip Enable Write Enable Output Enable Data Input/Output Max. 40 16 40 25 25 Unit Condition pF VIN2 = 0V Symbol Characteristic VDD Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage M/B Operating TA I Temperature C Min. 4.5 2.2 -0.52 -55 -40 0 Unit °C °C °C V 3 Typ. 5.0 Max. Unit 5.5 V VDD+0.3 V 0.8 V +25 +125 o +25 +85 C +25 +70 DC OUTPUT CHARACTERISTICS Symbol Parameter VOH HIGH Voltage VOL LOW Voltage Conditions Min. Max. Unit IOH= -4.0mA 2.4 V IOL=8.0mA 0.4 V DC OPERATING CHARACTERISTICS: Over operating ranges Symbol IIN IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Characteristics Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3.0V) Data Retention Supply Current (2.0V) Output Low Voltage Output High Voltage Test Conditions VIN = 0V to VDD VI/O = 0V to VDD, CE or OE = VIH, or WE = VIL Cycle=min., Duty=100% X8 IOUT = 0mA X16 VIN ≥ VDD -0.2V or VIN ≤ VSS +0.2V CE = VIH C I M/B Typ. (†) Min. Max. Min. Max. Min. Max. - -20 +20 -20 +20 -20 +20 µA - -20 +20 -20 +20 -20 +20 µA 36 0 480 mA 185 290 350 460 360 480 Unit 4 40 40 60 mA 80 240 240 240 mA VDR = 3.0V, CE ≥ VDR -0.2V 0.6 2.0 4.0 8.0 mA VDR = 2.0V, CE ≥ VDR -0.2V 0.4 1.2 3.2 7.2 mA - 0.4 0.4 0.4 V V IOUT = 8.0mA IOUT = -4.0mA 2.4 2.4 2.4 † Typical measurements made at +25oC, Cycle = min., VDD = 5.0V. 2 This Material Copyrighted By Its Respective Manufacturer 30A129-04 REV. E DPS1MX16MKn3 Dense-Pac Microsystems, Inc. AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels Figure 1. Output Load 0V to 3.0V 5ns +5V 1.5V 480Ω DOUT OUTPUT LOAD Load 1 2 CL 100pF 5pF CL* Parameters Measured except tLZ, tHZ, tOHZ, tOLZ, and tWHZ tLZ, tHZ, tOHZ, tOLZ, and tWHZ 255Ω Data Retention AC Characteristics 8 Symbol VDR VCDR tR Parameter VDD for Data Retention Chip Disable to Data Retention Time Operation Recovery Time Test Conditions CE ≥ VDR -0.2V Min. 2.0 Typ. - Max. - Unit V See Data Retention Waveform 0 - - ns See Data Retention Waveform 5 - - ms AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol 1 2 3 4 5 6 7 8 9 tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH Parameter Read Cycle Time Address Access Time CE to Output Valid Output Enable to Output Valid CE to Output in LOW-Z 4, 5 Output Enable to Output in LOW-Z 4, 5 CE to Output in HIGH-Z 4, 5 Output Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change 20ns* Min. Max. 20 25ns Min. 25 20 20 10 3 0 0 4 Max. Max. 30 25 25 12 3 0 8 8 30ns Min. 10 10 Max. 35 30 30 15 3 0 0 5 35ns Min. 15 15 Max. Unit 45 35 35 20 3 0 0 5 45ns Min. ns ns ns ns ns ns ns ns ns 45 45 25 3 0 20 20 0 5 25 25 0 5 AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges No. Symbol 10 11 12 13 14 15 16 17 18 19 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW Parameter Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-Up Time ** Write Pulse Width Write Recovery Time Write Enable to Output in HIGH-Z 4, 5 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 20ns* Min. 20 13 13 0 13 0 0 9 0 3 Max. 8 25ns Min. 25 15 15 0 15 0 0 10 0 3 Max. 10 30ns Min. 30 20 20 0 20 0 0 12 0 3 Max. 12 35ns Min. 35 25 25 0 25 0 0 15 0 3 Max. 15 45ns Min. 45 35 35 0 35 0 0 20 0 3 Max. 20 Unit ns ns ns ns ns ns ns ns ns ns * Available in Commercial and Industrial Grade Only. ** Valid for both Read and Write Cycles. 30A129-04 REV. E This Material Copyrighted By Its Respective Manufacturer 3 DPS1MX16MKn3 Dense-Pac Microsystems, Inc. DATA RETENTION WAVEFORM: CE Controlled. VDD 4.5V 2.3V VDR1 CE 0V CE ≥ VDD -0.2V READ CYCLE ADDRESS CE OE DATA I/O WRITE CYCLE 1: CE Controlled. ADDRESS CE WE DATA IN DATA OUT 4 This Material Copyrighted By Its Respective Manufacturer 30A129-04 REV. E Dense-Pac Microsystems, Inc. DPS1MX16MKn3 WRITE CYCLE 2: WE Controlled. OE is HIGH. 8 ADDRESS CE WE DATA IN DATA OUT WRITE CYCLE 3: WE Controlled. OE is LOW. 8 ADDRESS CE WE DATA IN DATA OUT 30A129-04 REV. E This Material Copyrighted By Its Respective Manufacturer 5 DPS1MX16MKn3 Dense-Pac Microsystems, Inc. (52 - PIN LEADLESS STACK) MECHANICAL DRAWING (52 - PIN STRAIGHT LEADED STACK) MECHANICAL DRAWING 6 This Material Copyrighted By Its Respective Manufacturer 30A129-04 REV. E Dense-Pac Microsystems, Inc. DPS1MX16MKn3 (52 - PIN ‘’J’’ LEADED STACK) MECHANICAL DRAWING (52 - PIN GULLWING LEADED STACK) MECHANICAL DRAWING 30A129-04 REV. E This Material Copyrighted By Its Respective Manufacturer 7 DPS1MX16MKn3 Dense-Pac Microsystems, Inc. ORDERING INFORMATION NOTES: 1. All voltages are with respect to VSS. 2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). 3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. This parameter is guaranteed and not 100% tested. 5. Transition is measured at the point of ±500mV from steady state voltage. 6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. The outputs are in a high impedance state when WE is LOW. 8. CE and WE can initiate and terminate WRITE Cycle. WAVEFORM KEY Data Valid Transition from HIGH to LOW Transition from LOW to HIGH Data Undefined or Don’t Care Dense-Pac Microsystems, Inc. 7321 Lincoln Way u Garden Grove, California 92841-1428 (714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com 8 This Material Copyrighted By Its Respective Manufacturer 30A129-04 REV. E