P4C163/163L P4C163/P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS FEATURES Single 5V±10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C163L Military) Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC – 28-Pin CERPACK Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 25/35ns (Commercial) – 25/35/45ns (Military) Low Power Operation (Commercial/Military) – 690/800 mW Active – 25 – 193/220 mW Standby (TTL Input) – 5.5 mW Standby (CMOS Input) P4C163L Output Enable and Dual Chip Enable Control Functions DESCRIPTION The P4C163 and P4C163L are 73,728-bit ultra high-speed static RAMs organized as 8K x 9. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is 10 µA from a 2.0V supply. Access times as fast as 25 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption in both active and standby modes. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS COLUMN I/O I/O 9 COLUMN SELECT CE 1 CE 2 WE A8 A 12 3 26 A3 A3 A4 4 A2 WE CE 2 4 25 A4 A5 6 24 5 24 A12 A 11 A 12 A 11 A5 6 23 A10 A6 7 23 A 10 A7 A8 8 22 9 21 OE A9 I/O 1 10 20 I/O 2 11 19 I/O 3 12 13 A6 7 22 OE A7 8 21 A9 A8 9 20 I/O1 10 19 CE1 I/O 9 I/O2 I/O3 11 18 I/O 8 12 17 I/O 7 I/O4 13 16 I/O 6 GND 14 15 I/O 5 DIP (P5, C5), SOJ (J5) CERPACK (F4) SIMILAR TOP VIEW OE WE V CC 27 3 5 2 27 28 26 1 25 14 15 16 18 17 CE 2 CE 1 I/O9 I/O8 I/O7 INPUT DATA CONTROL 28 2 I/O6 I/O 1 1 I/O4 A7 A0 A1 GND I/O5 73,728-BIT MEMORY ARRAY ROW SELECT VCC A2 A0 A1 A0 The P4C163 and P4C163L are available in 28-pin 300 mil DIP and SOJ and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. LCC (L5) TOP VIEW Means Quality, Service and Speed 1Q97 109 P4C163/163L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature GND VCC Military –55 to +125°C 0V 5.0V ± 10% Grade(2) Ambient Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C163 Test Conditions P4C163L Min Max Min Max Unit VIH Input High Voltage 2.2 VCC+0.5 2.2 VCC+0.5 V VIL Input Low Voltage –0.5(3) 0.8 –0.5(3) 0.8 V VHC CMOS Input High Voltage VCC–0.2 VCC+0.5 (3) VLC CMOS Input Low Voltage –0.5 VCD Input Clamp Diode Voltage VCC = Min., IIN = –18 mA VOL Output Low Voltage (TTL Load) VOLC 0.2 VCC–0.2 VCC+0.5 (3) –0.5 V 0.2 V –1.2 –1.2 V IOL = +8 mA, VCC = Min. 0.4 0.4 V Output Low Voltage (CMOS Load) IOLC = +100 µA, VCC = Min. 0.2 0.2 V VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. VOHC Output High Voltage (CMOS Load) IOHC = –100 µA, VCC = Min. ILI Input Leakage Current VCC = Max. VIN = GND to VCC Mil. Com’l. –10 –5 +10 +5 –5 N/A +5 N/A µA ILO Output Leakage Current VCC = Max., CE = VIH, VOUT= GND to VCC Mil. Com’l. –10 –5 +10 +5 –5 N/A +5 N/A µA 2.4 2.4 V VCC–0.2 VCC–0.2 V CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN Parameter Input Capacitance Symbol Conditions Typ. Unit VIN = 0V 5 COUT pF Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Parameter Output Capacitance Conditions Typ. Unit VOUT = 0V 7 pF 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 110 P4C163/163L POWER DISSIPATION CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C163 Test Conditions P4C163L Min Max Min Max Unit ICC Dynamic Operating Current – 25 VCC = Max., f = Max., Outputs Open Mil. Com’l. — — 145 125 — — 145 N/A mA ICC Dynamic Operating Current – 35, 45 VCC = Max., f = Max., Outputs Open Mil. Com’l. — — 120 95 — — 120 N/A mA ISB Standby Power Supply CE1 ≥ VIH or Current (TTL Input Levels) CE2 ≤ VIL, VCC = Max., f = Max., Outputs Open Mil. Com’l. — — 40 35 — — 40 N/A mA ISB1 Standby Power Supply Current (CMOS Input Levels) Mil. Com’l. — — 20 18 — — 1 N/A mA CE1 ≥ VHC or CE2 ≤ VLC, VCC = Max., f = 0, Outputs Open, VIN ≤ VLC or VIN ≥ VHC n/a = Not Applicable DATA RETENTION CHARACTERISTICS (P4C163L, Military Temperature Only) Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Min Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 CE1 ≥ VCC – 0.2V or CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V V 10 15 200 tRC§ ns DATA RETENTION MODE 4.5V VDR ≥ 2V CE 1 CE 2 4.5V tR VDR VHC VHC VLC VLC 111 µA ns DATA RETENTION WAVEFORM t CDR 300 0 *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. VCC Unit P4C163/163L AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol -25 Parameter -35 -45 Min Max Min Max Min Max 25 35 tRC Read Cycle Time tAA Address Access Time 25 35 45 ns tAC Chip Enable Access Time 25 35 45 ns tOH Output Hold from Address Change 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 ns tHZ Chip Disable to Output in High Z 10 15 20 ns tOE Output Enable Low to Data Valid 13 18 20 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 3 45 Unit 3 12 0 3 15 ns 20 0 20 ns 0 20 ns ns 25 ns OE CONTROLLED)(5) READ CYCLE NO. 1 (OE t RC (9) ADDRESS t AA OE t OE CE 1 t OLZ t OH (8) CE 2 t AC t OHZ(8) t LZ (8) t HZ(8) DATA OUT Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured ± 200mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 112 P4C163/163L READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) t RC (9) ADDRESS t AA t OH PREVIOUS DATA VALID DATA OUT DATA VALID CE1, CE2 CONTROLLED)(5,7,10) READ CYCLE NO. 3 (CE tRC CE 1 CE 2 (8,10) t AC (10) t HZ (8,10) t LZ DATA VALID DATA OUT (10) I CC VCC SUPPLY CURRENT HIGH IMPEDANCE t PD(10) t PU I SB Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. 113 P4C163/163L AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -25 Symbol Parameter -35 -45 Min Max Min Max Min Max Unit tWC Write Cycle Time 25 35 45 ns tCW Chip Enable Time to End of Write 18 25 33 ns tAW Address Valid to End of Write 18 25 33 ns tAS Address Set-up Time 0 0 0 ns tWP Write Pulse Width 18 20 25 ns tAH Address Hold Time 0 0 0 ns tDW Data Valid to End of Write 13 15 20 ns tDH Data Hold Time 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 10 3 14 5 18 5 WE CONTROLLED)(11) WRITE CYCLE NO. 1 (WE t WC (14) ADDRESS t CW CE 1 CE 2 t AW t WR t AH t WP WE t AS t DW DATA IN DATA VALID t OW(8,13) (8) t WZ DATA OUT t DH (12) DATA UNDEFINED HIGH IMPEDANCE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a low impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. 114 ns ns P4C163/163L CE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE t WC (14) ADDRESS t AS t CW CE 1 t AH t WR t AW CE 2 t WP WE t DW DATA IN t DH DATA VALID (12) DATA OUT(11) HIGH IMPEDANCE AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE Mode GND to 3.0V CE1 CE2 OE WE I/O Power Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V Standby X L X X High Z Standby Output Timing Reference Level 1.5V DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L High Z Active Output Load See Figures 1 and 2 +5V R TH = 166.5 Ω 480Ω D OUT DOUT 255Ω VTH = 1.73 V 30pF* (5pF* for t 30pF* (5pF* for t HZ , t LZ , t OHZ , tOLZ, tWZ and t OW ) HZ ,t ,t LZ , OHZ, t OLZ , t WZ and t OW ) 1527 09 1527 10 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C163/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 115 P4C163/163L PACKAGE SUFFIX Package Suffix P J C L F TEMPERATURE RANGE SUFFIX Temperature Range Suffix Description Plastic DIP, 300 mil wide standard Plastic SOJ, 300 mil wide standard Sidebrazed DIP, 300 mil wide Leadless Chip Carrier (ceramic) CERPACK C Description Commercial Temperature Range, 0°C to +70°C. Military Temperature Range, –55°C to +125°C. Mil. Temp. with MIL-STD-883D Class B compliance M MB ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 163 l — ss p t Temperature Range Package Code Speed (Access/Cycle Time) Low Power Designation L = Low Power; Blank = None Device Number Static RAM Prefix I = Ultra-low standby power designator L, if available. ss = Speed (access/cycle time in ns), e.g., 25, 35, 45. p = Package code, i.e., P, J, C, L. t = Temperature range, i.e., C, M, MB. 1527 11 The P4C163L is also available to SMD-5962-88683 SELECTION GUIDE The P4C163/L is available in the following temperature, speed and package options. The P4C163L is only available over the military temperature range. Temp. Range Speed Plastic DIP Plastic SOJ 25 –25PC –25JC 35 –35PC –35JC 45 N/A N/A Mil Temp. Side Brazed LCC CERPACK –25CM –25LM –25FM –35CM –35LM –35FM –45CM –45LM –45FM Military Proc’d* Side Brazed LCC CERPACK –25CMB –25LMB –25FMB –35CMB –35LMB –35FMB –45CMB –45LMB –45FMB Com’l Package * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available 116