DS1100 5-Tap Economy Timing Element (Delay Line) www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § § All-Silicon Timing Circuit Five Taps Equally Spaced 5V Operation Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy Improved Replacement for DS1000 Low-Power CMOS TTL/CMOS-Compatible Vapor-Phase, IR, and Wave Solderable Custom Delays Available Fast-Turn Prototypes Delays Specified Over Both Commercial and Industrial Temperature Ranges IN 1 8 VCC TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1100M DIP (300mil) DS1100Z SO (150mil) DS1100U µSOP PIN DESCRIPTION TAP 1 to TAP 5 VCC GND IN - TAP Output Number - +5V - Ground - Input DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry-standard DIP and SO packaging. The DS1100 5-tap silicon delay line reproduces the inputlogic state at the output after a fixed delay as specified by the extension of the part number after the dash. The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to meet special needs. 1 of 6 091202 DS1100 Figure 1. LOGIC DIAGRAM Table 1. DS1100 PART NUMBER DELAY TABLE (All Values in ns) PART DS1100-XXX -20 -25 -30 -35 -40 -45 -50 -60 -75 -100 -125 -150 -175 -200 -250 -300 -500 TAP 1 4 5 6 7 8 9 10 12 15 20 25 30 35 40 50 60 100 TAP 2 8 10 12 14 16 18 20 24 30 40 50 60 70 80 100 120 200 NOMINAL DELAYS TAP 3 12 15 18 21 24 27 30 36 45 60 75 90 105 120 150 180 300 Figure 2. TIMING DIAGRAM: SILICON DELAY LINE 2 of 6 TAP 4 16 20 24 28 32 36 40 48 60 80 100 120 140 160 200 240 400 TAP 5 20 25 30 35 40 45 50 60 75 100 125 150 175 200 250 300 500 DS1100 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Short-Circuit Output Current -0.5V to +6.0V -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020A Specification 50mA for 1s *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.) PARAMETER Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input-Leakage Current Active Current High-Level Output Current Low-Level Output Current SYM VCC TEST CONDITION MIN 4.75 TYP 5.00 MAX 5.25 VCC + 0.3 UNITS V NOTES 5 V 5 5 VIH 2.2 VIL -0.3 0.8 V -1.0 1.0 µA 50 mA -1 mA II 0.0V £ VI £ VCC ICC VCC = Max; Freq = 1MHz IOH VCC = Min; VOH = 4 IOL VCC = Min; VOL = 0.5 30 12 6, 8 mA AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.) PARAMETER Input Pulse Width Input-to-Tap Delay Tolerance (Delays £ 40ns) Input-to-Tap Delay Tolerance (Delays > 40ns) Power-Up Time Input Period SYM TEST CONDITION tWI tPLH, tPHL tPLH, tPHL +25°C 5V 0°C to +70°C -40°C to +85°C +25°C 5V 0°C to +70°C -40°C to +85°C tPU Period MIN 20% of Tap 5 tPLH -2 -3 -4 -5 -8 -13 TYP Table 1 Table 1 Table 1 Table 1 Table 1 Table 1 MAX UNITS NOTES ns 9 ns ns ns % % % µs ns 1, 3, 4, 7 1, 2, 3, 4, 7 1, 2, 3, 4, 7 1, 3, 4, 7 1, 2, 3, 4, 7 1, 2, 3, 4, 7 +2 +3 +4 +5 +8 +13 200 2(tWI) CAPACITANCE PARAMETER Input Capacitance 9 (TA = +25°C) SYMBOL CIN MIN TYP 5 3 of 6 MAX 10 UNITS pF NOTES DS1100 NOTES: 1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and trailing edge. 2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature range, and a supply-voltage range of 4.75V to 5.25V. 3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2. 4) Intermediate delay values are available on a custom basis. For further information, call (972) 371-4348. 5) All voltages are referenced to ground. 6) Measured with outputs open. 7) See Test Conditions section at the end of this data sheet. 8) Frequencies higher than 1MHz result in higher ICC values. 9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e., decoupling, layout). Figure 3. TEST CIRCUIT 4 of 6 DS1100 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100. The input waveform is produced by a precision-pulse generator under software control. Time delays are measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS INPUT : Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Time: Pulse Width: Period: +25°C ±3°C 5.0V ±0.1V High = 3.0V ±0.1V Low = 0.0V ±0.1V 50W max 3.0ns max (measured between 0.6V and 2.4V) 500ns (1µs for -500 version) 1µs (2µs for -500 version) OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 5 of 6 DS1100 ORDERING INFORMATION DS1100 TOTAL TIME DELAY (ns): 20, 25, 30, 35, 40, 45, 50, 60, 75, 100, 125, 150, 175, 200, 250, 300, 500 PACKAGE TYPE: M = DIP Z = SO (150MIL) U = µSOP EXAMPLE: The DS1100Z-250 is a 250ns delay (input-to-tap 5) DS1100 in the SO package. 6 of 6