MAXIM MXD1000SE__

19-1310; Rev 0; 10/97
5-Tap Silicon Delay Line
________________________Applications
____________________________Features
♦ Improved Second Source to DS1000
♦ Available in Space-Saving 8-Pin µMAX Package
♦ 20mA Supply Current (vs. Dallas’ 35mA)
♦ Low Cost
♦ Delay Tolerance of ±2ns or ±5%, whichever is
Greater
♦ TTL/CMOS-Compatible Logic
♦ Leading- and Trailing-Edge Accuracy
♦ Custom Delays Available
______________Ordering Information
Clock Synchronization
PART
MXD1000C/D__
Digital Systems
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
Dice*
MXD1000PA__
MXD1000PD__
MXD1000SA__
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 Plastic DIP
14 Plastic DIP
8 SO
MXD1000SE__
MXD1000UA__
-40°C to +85°C
-40°C to +85°C
16 Narrow SO
8 µMAX
*Dice are tested at TA = +25°C.
Note: To complete the ordering information, fill in the blank
with the part number extension from the Part Number and Delay
Times table (located at the end of this data sheet) to indicate
the desired delay per output.
Functional Diagram appears at end of data sheet.
__________________________________________________________Pin Configurations
TOP VIEW
IN 1
TAP2 2
8
VCC
7
TAP1
MXD1000
3
6
TAP3
GND 4
5
TAP5
TAP4
DIP/SO/µMAX
IN 1
14 VCC
IN 1
16 VCC
N.C.
2
13 N.C.
N.C. 2
15 N.C.
N.C.
3
12 TAP1
N.C. 3
11 N.C.
TAP2 4
TAP2 4
MXD1000
N.C. 5
10 TAP3
14 N.C.
MXD1000
13 TAP1
N.C. 5
12 N.C.
TAP4 6
9
N.C.
TAP4 6
11 TAP3
GND 7
8
TAP5
N.C. 7
10 N.C.
GND 8
9
TAP5
DIP
SO
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MXD1000
_______________General Description
The MXD1000 silicon delay line offers five equally
spaced taps with delays ranging from 4ns to 500ns and
a nominal accuracy of ±2ns or ±5%, whichever is
greater. Relative to hybrid solutions, this device offers
enhanced performance and higher reliability, and
reduces overall cost. Each tap can drive up to ten 74LS
loads.
The MXD1000 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin µMAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1000 and other delay line products.
MXD1000
5-Tap Silicon Delay Line
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.5V to +6V
All Other Pins..............................................-0.5V to (VCC + 0.5V)
Short-Circuit Output Current (1sec) ....................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) .......727mW
14-Pin Plastic DIP (derate 10.0mW/°C above +70°C) ...800mW
8-Pin SO (derate 5.9mW/°C above +70°C)....................471mW
16-Pin Narrow SO (derate 8.7mW/°C above +70°C) .....696mW
8-Pin µMAX (derate 4.1mW/°C above +70°C) ...............330mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V ±5%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
MIN
TYP
MAX
UNITS
Supply Voltage
PARAMETER
VCC
(Note 3)
4.75
5.00
5.25
V
Input Voltage High
VIH
(Note 3)
2.2
Input Voltage Low
VIL
(Note 3)
IL
0V ≤ VIN ≤ VCC
Input Leakage Current
SYMBOL
CONDITIONS
V
0.8
-1
Active Current
ICC
VCC = 5.25V, period = minimum (Notes 4, 5)
Output Current High
IOH
VCC = 4.75V, VOH = 4.0V
Output Current Low
IOL
VCC = 4.75V, VOL = 0.5V
Input Capacitance
CIN
TA = +25°C (Note 6)
20
V
1
µA
75
mA
-1
mA
12
mA
5
10
pF
TIMING CHARACTERISTICS
(VCC = +5.0V ±5%, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
Input Pulse Width
tWI
Input-to-Tap Delay
(leading edge)
tPLH
(Notes 1, 8–12)
See Part Number and
Delay Times table
ns
Input-to-Tap Delay
(trailing edge)
tPHL
(Notes 1, 8–12)
See Part Number and
Delay Times table
ns
Power-Up Time
tPU
Period
(Note 7)
MIN
40% of TAP5
tPLH
ns
100
(Note 7)
4(tWI)
ms
ns
Contact factory for ordering information.
Specifications to -40°C are guaranteed by design, not production tested.
All voltages referenced to GND.
Measured with output open.
ICC is a function of frequency and TAP5 delay. Only an MXD1000_ _25 operating with a 40ns period and VCC = +5.25V will have
an ICC = 75mA. For example, an MXD1000_ _100 will never exceed 30mA. See Supply Current vs. Input Frequency in Typical
Operating Characteristics.
Note 6: Guaranteed by design.
Note 7: Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling,
etc.). The device will remain functional with pulse widths down to 20% of TAP5 delay, and input periods as short as 2(tWI).
Note 8: Typical initial tolerances are ± with respect to the nominal value at +25°C and VCC = 5V.
Note 9: Typical temperature tolerance is ± with respect to the initial delay value over a temperature range of -40°C to +85°C.
Note 10: The delay will also vary with supply voltage, typically by less than 4% over the supply range of VCC = +4.75V to +5.25V.
Note 11: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other
taps will also slow down; i.e., TAP3 can never be faster than TAP2.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
2
_______________________________________________________________________________________
5-Tap Silicon Delay Line
MXD1000_ _75
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
ACTIVE CURRENT
vs. FREQUENCY
16
MXD1000_ _50
MXD1000_ _75
12
MXD1000_ _200
tPLH
0.5
tPLH
0
tPHL
-0.5
-1.0
-1.5
MXD1000_ _500
8
RELATIVE TO NOMINAL (+25°C)
-2.0
0.001
0.01
0.1
1
10
100
-40
-20
0
20
40
60
80
100
FREQUENCY (MHz)
TEMPERATURE (°C)
MXD1000_ _100 TO MXD1000_ _200
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1000_ _250 TO MXD1000_ _500
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
1.5
1.0
tPHL
0.5
tPHL
0
tPLH
-0.5
tPLH
-1.0
-1.5
2.0
1.5
% CHANGE IN DELAY (TAP2)
MXD1000 TOC2
2.0
% CHANGE IN DELAY (TAP2)
tPHL
1.0
MXD1000 TOC03
10
1.5
% CHANGE IN DELAY (TAP2)
ACTIVE CURRENT (mA)
18
MXD1000 TOC01
50% DUTY CYCLE
14
2.0
MXD1000-04
20
1.0
0.5
tPLH
tPHL
0
tPHL
-0.5
tPLH
-1.0
-1.5
RELATIVE TO NOMINAL (+25°C)
-2.0
RELATIVE TO NOMINAL (+25°C)
-2.0
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
MXD1000
__________________________________________Typical Operating Characteristics
(VCC = +5V, TA = +25°C, unless otherwise noted.)
MXD1000
5-Tap Silicon Delay Line
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
8-PIN
DIP/SO/µMAX
14-PIN DIP
16-PIN SO
1
1
1
IN
2
4
4
TAP2
40% of specified maximum delay
3
6
6
TAP4
80% of specified maximum delay
4
7
8
GND
Device Ground
5
8
9
TAP5
100% of maximum specified delay
6
10
11
TAP3
60% of specified maximum delay
7
12
13
TAP1
20% of specified maximum delay
8
14
16
VCC
Power-Supply Input
—
2, 3, 5, 9, 11,
13
2, 3, 5, 7, 10,
12, 14, 15
N.C.
No Connection. Not internally connected.
Signal Input
Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________Definitions of Terms
Period: The time elapsed between the first pulse’s
leading edge and the following pulse’s leading edge.
Pulse Width (t WI): The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
Input Rise Time (tRISE): The time elapsed between
the 20% and 80% points on the input pulse’s leading
edge.
Input Fall Time (tFALL): The time elapsed between
the 80% and 20% points on the input pulse’s trailing
edge.
Time Delay, Rising (tPLH): The time elapsed between
the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.
Time Delay, Falling (tPHL): The time elapsed between
the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.
4
____________________Test Conditions
Ambient Temperature:
Supply Voltage (VCC):
Input Pulse:
+25°C ±3°C
+5V ±0.1V
High = 3.0V ±0.1V
Source Impedance:
Low = 0.0V ±0.1V
50Ω max
Rise and Fall Times:
Pulse Width:
3.0ns max
500ns max (1ns for -500)
Period:
1µs (2ns for -500)
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
_______________________________________________________________________________________
5-Tap Silicon Delay Line
VIH
IN
VIL
(+5V)
0.1µF
PERIOD
TIME
MEASUREMENT
UNIT
tFALL
tRISE
2.4V
1.5V
2.4V
1.5V
1.5V
0.6V
0.6V
MXD1000
VCC
IN
20%
TAP1
20%
TAP2
20%
TAP3
20%
TAP4
20%
TAP5
50Ω
tWI
MXD1000
tPHL
tPLH
1.5V
1.5V
OUT
74FO4
Figure 2. Test Circuit
Figure 1. Timing Diagram
__________Applications Information
Supply and Temperature
Effects on Delay
Variations in supply voltage may affect the MXD1000’s
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temperature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.
Capacitance and Loading
Effects on Delay
The output load can affect the tap delays. Larger
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.
Board Layout Considerations/Decoupling
The device should be driven with a source that can
deliver the required current for proper operation. A
0.1µF ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capacitance.
_______________________________________________________________________________________
5
MXD1000
5-Tap Silicon Delay Line
_________________________________________________Part Number and Delay Times
Part
Number
Extension
(MXD1000__)
TAP1
TAP2
Tolerance
(ns)
Nom.
Delay
(ns)
Init.
20
(Note 1)
4
25
(Note 1)
TAP3
Tolerance
(ns)
Temp.
Nom.
Delay
(ns)
Init.
2
1
8
5
2
1
30
(Note 1)
6
2
35
7
40
8
45
50
60
TAP4
Tolerance
(ns)
Temp.
Nom.
Delay
(ns)
Init.
2
1
12
10
2
1
1
12
2
2
1
14
2
1
16
9
2
1
10
2
1
12
2
TAP5
Tolerance
(ns)
Temp.
Nom.
Delay
(ns)
Init.
2
1
16
15
2
1
1
18
2
2
1
21
2
1
24
18
2
1
20
2
1
1
24
2
Temp.
Init.
Temp.
2
1
20
2
1
20
2
1
25
2
1
1
24
2
1
30
2
1
2
1
28
2
1
35
2
1.1
2
1
32
2
1
40
2
1.2
27
2
1
36
2
1.1
45
2.3
1.4
30
2
1
40
2
1.2
50
2.5
1.5
1
36
2
1.1
48
2.4
1.5
60
3
1.8
75
15
2
1
30
2
1
45
2.3
1.4
60
3
1.8
75
3.8
2.3
100
20
2
1
40
2
1.2
60
3
1.8
80
4
2.4
100
5
3
125
25
2
1
50
2.5
1.5
75
3.8
2.3
100
5
3
125
6.3
3.8
150
30
2
1
60
3
1.8
90
4.5
2.7
120
6
3.6
150
7.5
4.5
175
35
2
1.1
70
3.5
2.1
105
5.3
3.2
140
7
4.2
175
8.8
5.3
200
40
2
1.2
80
4
2.4
120
6
3.6
160
8
4.8
200
10
6
250
50
2.5
1.5
100
5
3
150
7.5
4.5
200
10
6
250
12.5
7.5
500
100
5
3
200
10
6
300
15
9
400
20
12
500
25
15
Note 1: Contact factory for ordering information.
6
Tolerance
(ns)
Nom.
Delay
(ns)
_______________________________________________________________________________________
5-Tap Silicon Delay Line
TAP1
IN
20%
TAP2
20%
TAP3
20%
TAP4
20%
TAP5
20%
MXD1000
___________________Chip Information
TRANSISTOR COUNT: 824
_______________________________________________________________________________________
7
MXD1000
_________________________________________________________Functional Diagram
________________________________________________________Package Information
8LUMAXD.EPS
MXD1000
5-Tap Silicon Delay Line
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.