XX-XXXX; Rev 1; 11/03 3V 10-Tap Silicon Delay Line The DS1110L 10-tap delay line is a 3V version of the DS1110. It has 10 equally spaced taps providing delays from 10ns to 500ns. The DS1110L series delay lines provide a nominal accuracy of ±5% or ±2ns, whichever is greater, at 3.3V and +25°C. The DS1110L is characterized to operate from 2.7V to 3.6V. The DS1110L produces both leading- and trailing-edge delays with equal precision. The device is offered in a standard 14-pin TSSOP. Features ♦ All-Silicon Delay Line ♦ 3V Version of the DS1110 ♦ 10 Taps Equally Spaced ♦ Delays Are Stable and Precise ♦ Leading- and Trailing-Edge Accuracy ♦ Delay Tolerance ±5% or ±2ns, Whichever Is Greater, at 3.3V and +25°C ♦ Economical ♦ Low-Profile 14-Pin TSSOP Applications Communications Equipment ♦ Low-Power CMOS ♦ TTL/CMOS Compatible ♦ Vapor Phase and IR Solderable Medical Devices ♦ Fast-Turn Prototypes Automated Test Equipment ♦ Delays Specified Over Commercial and Industrial Temperature Ranges PC Peripheral Devices ♦ Custom Delays Available Pin Configuration TOP VIEW IN 1 Ordering Information PART TEMP RANGE PINPACKAGE TOTAL DELAY (ns) * DS1110LE-100 -40°C to +85°C 14 TSSOP (173mil) 100 14 VCC DS1110LE-125 -40°C to +85°C 14 TSSOP (173mil) 125 N.C. 2 13 TAP1 DS1110LE-150 -40°C to +85°C 14 TSSOP (173mil) 150 TAP2 3 12 TAP3 DS1110LE-175 -40°C to +85°C 14 TSSOP (173mil) 175 11 TAP5 DS1110LE-200 -40°C to +85°C 14 TSSOP (173mil) 200 10 TAP7 DS1110LE-250 -40°C to +85°C 14 TSSOP (173mil) 250 TAP8 6 9 TAP9 DS1110LE-300 -40°C to +85°C 14 TSSOP (173mil) 300 GND 7 8 TAP10 DS1110LE-350 -40°C to +85°C 14 TSSOP (173mil) 350 DS1110LE-400 -40°C to +85°C 14 TSSOP (173mil) 400 DS1110LE-450 -40°C to +85°C 14 TSSOP (173mil) 450 DS1110LE-500 -40°C to +85°C 14 TSSOP (173mil) 500 TAP4 4 TAP6 5 DS1110L TSSOP (173mil) *Custom delays are available. _____________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1110L General Description DS1110L 3V 10-Tap Silicon Delay Line ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C, VCC = 2.7V to 3.6V.) PARAMETER SYMBOL Supply Voltage VCC CONDITIONS (Note 1) MIN TYP 2.7 3.3 MAX UNITS 3.6 V VCC + 0.3 V High-Level Input Voltage VIH (Note 1) 2.2 Low-Level Input Voltage VIL (Note 1) -0.3 +0.8 V 0V ≤ VI ≤ VCC -1.0 +1.0 µA 150 mA Input Leakage Current II Active Current ICC VCC = max, period = min (Note 2) High-Level Output Current IOH VCC = min, VOH = 2.3V Low-Level Output Current IOL VCC = min, VOL = 0.5V 40 -1.0 12 mA mA AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C, VCC = 2.7V to 3.6V.) PARAMETER SYMBOL Input Pulse Width tWI Input to Tap Delay (Delays ≤ 40ns) tPLH tPHL Input to Tap Delay (Delays > 40ns) tPLH tPHL Power-Up Time Input Period 2 CONDITIONS (Note 6) MIN MAX 10% of tap 10 -2 Table 1 +2 0°C to +70°C (Notes 4–7) -3 Table 1 +3 -40°C to +85°C (Notes 4–7) -4 Table 1 +4 +25°C, 3.3V (Notes 3, 5, 6, 7, 9) -5 Table 1 +5 0°C to +70°C (Notes 4–7) -8 Table 1 +8 -40°C to +85°C (Notes 4–7) -13 Table 1 +13 100 (Note 8) ______________________________________________________________________ 2 (tWI) UNITS ns +25°C, 3.3V (Notes 3, 5, 6, 7, 9) tPU Period TYP ns % ms ns 3V 10-Tap Silicon Delay Line DS1110L CAPACITANCE (TA = +25°C.) PARAMETER Input Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: CONDITIONS SYMBOL MIN TYP MAX UNITS 5 10 pF CIN All voltages are referenced to ground. Measured with outputs open. Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and trailing edges. Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to 3.6V range. Intermediate delay values are available on a custom basis. See Test Conditions section. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.). For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater. Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) DELAY CHANGE (%) vs. VCC DS1110L-500 DELAY CHANGE (%) vs. VCC DS1110L-250 DS1110L toc02 0.05 0.2 0 CHANGE IN DELAY (%) CHANGE IN DELAY (%) 0.3 DS1110L toc01 0.10 -0.05 -0.10 RAISING EDGE FALLING EDGE -0.15 -0.20 0.1 0 -0.1 RAISING EDGE FALLING EDGE -0.2 -0.25 -0.3 -0.30 -0.35 -0.4 2.7 3.0 3.6 3.3 3.0 3.3 3.6 VCC (V) CHANGE IN DELAY (%) vs. TEMPERATURE DS1110L-500 CHANGE IN DELAY (%) vs. TEMPERATURE DS1110L-250 5 4 2 1 0 RISING EDGE FALLING EDGE -1 -2 3 CHANGE IN DELAY (%) 3 -3 DS1110L toc04 4 DS1110L toc03 6 CHANGE IN DELAY (%) 2.7 VCC (V) 2 1 0 RISING EDGE FALLING EDGE -1 -2 -4 -5 -3 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _____________________________________________________________________ 3 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) OUTPUT CURRENT HIGH vs. OUTPUT VOLTAGE HIGH OUTPUT CURRENT LOW vs. OUTPUT VOLTAGE LOW -6.00E-03 -8.00E-03 -1.00E-02 -1.20E-02 -1.40E-02 DS1110L toc06 -4.00E-03 1.60E-02 OUTPUT CURRENT LOW (A) VCC = 2.7V -1.60E-02 1.40E-02 1.20E-02 1.00E-02 8.00E-03 6.00E-03 4.00E-03 VCC = 2.7V 2.00E-03 -1.80E-02 0.00E+00 2.0 2.1 2.2 2.3 2.4 2.5 2.7 2.6 0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT VOLTAGE HIGH (V) OUTPUT VOLTAGE LOW (V) ACTIVE CURRENT vs. INPUT FREQUENCY DS1110L-250 ACTIVE CURRENT vs. INPUT FREQUENCY DS1110L-500 25 DS1110L toc07 50 45 40 20 CURRENT (mA) 35 30 25 20 DS1110L toc08 OUTPUT CURRENT HIGH (A) 1.80E-02 DS1110L toc05 0.00E+0 -2.00E-03 CURRENT (mA) DS1110L 3V 10-Tap Silicon Delay Line 15 10 15 VCC = 3.6V 15pF LOAD ON EACH TAP 10 5 VCC = 3.6V 15pF LOAD ON EACH TAP 5 0 0 0.1 1 10 100 0.1 10 1.0 FREQUENCY (MHz) FREQUENCY (MHz) Pin Description 4 PIN NAME FUNCTION 1 IN 2 N.C. No Connection 7 GND Ground 13, 3, 12, 4, 11, 5, 10, 6, 9, 8 Tap 1–Tap 10 14 VCC Input Tap Output Number 2.7V to 3.6V ______________________________________________________________________ 3V 10-Tap Silicon Delay Line Table 1. Part Number by Delay (tPHL, tPLH) The DS1110L 10-tap delay line is a 3V version of the DS1110. It has 10 equally spaced taps providing delays from 10ns to 500ns. The device is offered in a standard 14-pin TSSOP. The DS1110L series delay lines provide a nominal accuracy of ±5% or ±2ns, whichever is greater, at 3.3V and +25°C. The DS1110L is characterized to operate from 2.7V to 3.6V. The DS1110L reproduces the input-logic state at the tap 10 output after a fixed delay as specified by the dash-number suffix of the part number (Table 1). The DS1110L produces both leading- and trailing-edge delays with equal precision. Each tap is capable of driving up to 10 74LS-type loads. Dallas Semiconductor can customize standard products to meet specific needs. Figure 1 is the DS1110_L logic diagram and Figure 2 shows the timing diagram for the silicon delay line. TAP1 PART TOTAL DELAY (ns) DELAY/TAP (ns) DS1110LE-100 100 10 DS1110LE-125 125 12.5 DS1110LE-150 150 15 DS1110LE-175 175 17.5 DS1110LE-200 200 20 DS1110LE-250 250 25 DS1110LE-300 300 30 DS1110LE-350 350 35 DS1110LE-400 400 40 DS1110LE-450 450 45 DS1110LE-500 500 50 TAP2 TAP9 TAP10 IN 10% 10% 10% 10% Figure 1. Logic Diagram PERIOD tFALL tRISE VIH 2.4V 2.4V 1.5V 1.5V 1.5V 0.6V 0.6V IN VIL tWI tWI tPLH tPLH 1.5V 1.5V OUT Figure 2. Timing Diagram: Silicon Delay Line _____________________________________________________________________ 5 DS1110L Detailed Description DS1110L 3V 10-Tap Silicon Delay Line Terminology Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. Test Setup Description Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1110L. A precision pulse generator under software control produces the input waveform. Time delays are measured by a time interval counter (20ps resolution) connected PULSE GENERATOR START Z0 = 50Ω TIME INTERVAL COUNTER STOP VHF SWITCH CONTROL UNIT DEVICE UNDER TEST Figure 3. Test Circuit 6 ______________________________________________________________________ 3V 10-Tap Silicon Delay Line Chip Information TRANSISTOR COUNT: 6813 Output Each output is loaded with the equivalent of one 450Ω resistor in parallel with a 15pF capacitor. Delay is measured at the 1.5V level on the rising and falling edge. Package Information For the latest package outline information, go to www.maxim-ic. com/packages. Table 2. Test Conditions INPUT CONDITION Ambient Temperature +25°C ±3°C Supply Voltage (VCC) 3.3V ±0.1V Input Pulse High = 3.0V ±0.1V Low = 0.0V ±0.1V Source Impedance 50Ω max Rise and Fall Time 2ns max Pulse Width 500ns (1µs for - 500ns) Period 1µs (2µs for - 500ns) Note: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. DS1110L between the input and each tap. Each tap is selected and connected to the counter by a VHF switch-control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE-488 bus.