Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DSP56002 24-BIT DIGITAL SIGNAL PROCESSOR USER’S MANUAL Motorola, Inc. Semiconductor Products Sector DSP Division 6501 William Cannon Drive, West Austin, Texas 78735-8598 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc... Paragraph Number Title Page Number SECTION 1 INTRODUCTION TO THE DSP56002 1.1 1.2 1.3 1.4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56K CENTRAL PROCESSING UNIT OVERVIEW. . . . . . . . . . . . . . . . MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-4 1-4 1-5 SECTION 2 DSP56002 PIN DESCRIPTIONS 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 Port A Address and Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1.1 Address (A0–A15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 2.2.1.2 Data Bus (D0–D23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 2.2.2 Port A Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.2.1 Program Memory Select (PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 2.2.2.2 Data Memory Select (DS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.3 X/Y Select (X/Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.4 Read Enable (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.5 Write Enable (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.6 Bus Needed (BN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.7 Bus Request (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2.2.8 Bus Grant (BG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.2.2.9 Bus Strobe (BS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.2.2.10 Bus Wait (WT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.2.3 Interrupt and Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.3.1 Mode Select A/External Interrupt Request A (MODA/IRQA)/STOP Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 2.2.3.2 Mode Select B/External Interrupt Request B (MODB/IRQB) . . . . . . .2-7 2.2.3.3 Mode Select C/Non-Maskable Interrupt Request (MODC/NMI) . . . .2-7 MOTOROLA TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number Title Page Number 2.2.3.4 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 2.2.4 Power and Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4.1 Power (Vcc), Ground (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 2.2.4.2 External Clock/Crystal Input (EXTAL) . . . . . . . . . . . . . . . . . . . . . . . .2-8 2.2.4.3 Crystal Output (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 2.2.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5.1 Host Data Bus (H0–H7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 2.2.5.2 Host Address (HA0–HA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.5.3 Host Read/Write (HR/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.5.4 Host Enable (HEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.5.5 Host Request (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.5.6 Host Acknowledge (HACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.6 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.6.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.6.2 Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.6.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.7 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7.1 Serial Clock Zero (SC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.7.2 Serial Control One (SC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.7.3 Serial Control Two (SC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.7.4 SSI Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.7.5 SSI Receive Data (SRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.7.6 SSI Transmit Data (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.3 ON-CHIP EMULATION (OnCE) PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.1 Debug Serial Input/Chip Status 0 (DSI/OS0) . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.2 Debug Serial Clock/Chip Status 1 (DSCK/OS1). . . . . . . . . . . . . . . . . . . 2-12 2.3.3 Debug Serial Output (DSO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.4 Debug Request Input (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4 PLL PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.5 TIMER/EVENT COUNTER MODULE PIN. . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 SECTION 3 MEMORY MODULES AND OPERATING MODES 3.1 MEMORY MODULES AND OPERATING MODES . . . . . . . . . . . . . . . . . . . 3.2 DSP56002 DATA AND PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 X Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com 3-3 3-3 3-3 3-4 MOTOROLA Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number 3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.5 3.6 Title Page Number Y Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56002 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . . . . Chip Operating Mode (Bits 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . Data ROM Enable (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Y Memory Disable Bit (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Operating Mode (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Delay (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved OMR Bits (Bits 7–23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56002 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Chip Mode (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap From EPROM (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Expanded Mode (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development Mode (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap From Host (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap From SCI (Mode 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved (Mode 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56002 INTERRUPT PRIORITY REGISTER. . . . . . . . . . . . . . . . . . . . . DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR . . 3-4 3-4 3-6 3-6 3-6 3-7 3-7 3-7 3-7 3-7 3-8 3-8 3-11 3-11 3-11 3-11 3-12 3-12 3-12 3-13 SECTION 4 PORT A 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT A INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT A TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT A WAIT STATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS CONTROL REGISTER (BCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS STROBE AND WAIT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS ARBITRATION AND SHARED MEMORY. . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Using Only BR and BG With Internal Control. . . . . . . . . Bus Arbitration Using BN, BR, and BG With External Control . . . . . . . . Bus Arbitration Using BR and BG, and WT and BS With No Overhead. Signaling Using Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com 4-3 4-3 4-9 4-13 4-13 4-15 4-16 4-18 4-18 4-20 4-22 v Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number Title SECTION 5 PORT B Page Number 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 GENERAL PURPOSE I/O CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.1 Programming General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.2 Port B General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 HOST INTERFACE (HI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1 Host Interface – DSP CPU Viewpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2 Programming Model – DSP CPU Viewpoint. . . . . . . . . . . . . . . . . . . . . . 5-12 5.3.2.1 Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 5.3.2.1.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . . . . . . . . . .5-14 5.3.2.1.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . . . . . . . . . .5-14 5.3.2.1.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 . . . . . . . . . .5-14 5.3.2.1.4 HCR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 5.3.2.1.5 HCR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 5.3.2.1.6 HCR Reserved Control (Bits 5, 6, and 7) . . . . . . . . . . . . . . . . . . .5-15 5.3.2.2 Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 5.3.2.2.1 HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . . . . . . . . . .5-15 5.3.2.2.2 HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . . . . . . . . . .5-15 5.3.2.2.3 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . . . . . . . . . .5-16 5.3.2.2.4 HSR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16 5.3.2.2.5 HSR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16 5.3.2.2.6 HSR Reserved Status (Bits 5 and 6) . . . . . . . . . . . . . . . . . . . . . .5-17 5.3.2.2.7 HSR DMA Status (DMA) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.3.2.3 Host Receive Data Register (HRX) . . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.3.2.4 Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.3.2.5 Register Contents After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17 5.3.2.6 Host Interface DSP CPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .5-18 5.3.2.7 Host Port Usage Considerations – DSP Side . . . . . . . . . . . . . . . . . .5-18 5.3.3 Host Interface – Host Processor Viewpoint . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.3.1 Programming Model – Host Processor Viewpoint . . . . . . . . . . . . . . .5-20 5.3.3.2 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20 5.3.3.2.1 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . . . . . . . . .5-22 5.3.3.2.2 ICR Transmit Request Enable (TREQ) Bit 1 . . . . . . . . . . . . . . . .5-22 5.3.3.2.3 ICR Reserved Bit (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.6 ICR Host Mode Control (HM1 and HM0 bits) Bits 5 and 6 . . . . . .5-23 5.3.3.2.7 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24 5.3.3.3 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . .5-26 vi TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number Title Page Number 5.3.3.3.1 CVR Host Vector (HV) Bits 0–5 . . . . . . . . . . . . . . . . . . . . . . . . . .5-26 5.3.3.3.2 CVR Reserved Bit (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.3.3 CVR Host Command Bit (HC) Bit 7 . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.4 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.4.1 ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . . . . . . . . .5-27 5.3.3.4.2 ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . . . . . . . . . .5-28 5.3.3.4.3 ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.4 ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.5 ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.6 ISR Reserved Bit (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.7 ISR DMA Status (DMA) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.4.8 ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.5 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.6 Receive Byte Registers (RXH, RXM, RXL) . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.7 Transmit Byte Registers (TXH, TXM, TXL) . . . . . . . . . . . . . . . . . . . .5-30 5.3.3.8 Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 5.3.4 Host Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.3.4.1 Host Data Bus(H0-H7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 5.3.4.2 Host Address (HA0–HA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 5.3.4.3 Host Read/Write (HR/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.4 Host Enable (HEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.5 Host Request (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.6 Host Acknowledge (HACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.5 Servicing the Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.3.5.1 HI Host Processor Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .5-34 5.3.5.2 HI Interrupts Host Request (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . .5-34 5.3.5.3 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35 5.3.5.4 Servicing Non-DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-36 5.3.5.5 Servicing DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-37 5.3.6 HI Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.3.6.1 HI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-38 5.3.6.2 Polling/Interrupt Controlled Data Transfer . . . . . . . . . . . . . . . . . . . . .5-38 5.3.6.2.1 Host to DSP - Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40 5.3.6.2.2 Host to DSP – Command Vector . . . . . . . . . . . . . . . . . . . . . . . . .5-43 5.3.6.2.3 Host to DSP - Bootstrap Loading Using the HI . . . . . . . . . . . . . .5-50 5.3.6.2.4 DSP to Host Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-51 5.3.6.3 DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-54 5.3.6.3.1 Host To DSP Internal Processing . . . . . . . . . . . . . . . . . . . . . . . .5-56 5.3.6.3.2 Host to DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-57 5.3.6.3.3 DSP to Host Internal Processing . . . . . . . . . . . . . . . . . . . . . . . . .5-59 5.3.6.3.4 DSP to Host DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-60 5.3.6.4 Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-62 5.3.6.5 Host Port Usage Considerations – Host Side . . . . . . . . . . . . . . . . . .5-65 MOTOROLA TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number Title SECTION 6 PORT C Page Number 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 GENERAL-PURPOSE I/O (PORT C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 Programming General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.2.2 Port C General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1 SCI I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 6.3.1.2 Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 6.3.1.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 6.3.2 SCI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.3.2.1 SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 6.3.2.1.1 SCR Word Select (WDS0, WDS1, WDS2) Bits 0, 1, and 2 . . . . .6-14 6.3.2.1.2 SCR SCI Shift Direction (SSFTD) Bit 3 . . . . . . . . . . . . . . . . . . . .6-18 6.3.2.1.3 SCR Send Break (SBK) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 6.3.2.1.4 SCR Wakeup Mode Select (WAKE) Bit 5 . . . . . . . . . . . . . . . . . .6-18 6.3.2.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6 . . . . . . . . . . . . . . . .6-18 6.3.2.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7 . . . . . . . . . . . . . . . .6-19 6.3.2.1.7 SCR Receiver Enable (RE) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . .6-19 6.3.2.1.8 SCR Transmitter Enable (TE) Bit 9 . . . . . . . . . . . . . . . . . . . . . . .6-19 6.3.2.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10 . . . . . . . . . . . . . . . .6-20 6.3.2.1.10 SCR SCI Receive Interrupt Enable (RIE) Bit 11 . . . . . . . . . . . . .6-21 6.3.2.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12 . . . . . . . . . . . . .6-21 6.3.2.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13 . . . . . . . . . . . . . . . . .6-21 6.3.2.1.13 SCR SCI Timer Interrupt Rate (STIR) Bit 14 . . . . . . . . . . . . . . . .6-21 6.3.2.1.14 SCR SCI Clock Polarity (SCKP) Bit 15 . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.1 SSR Transmitter Empty (TRNE) Bit 0 . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1 . . . . . . . . . . . .6-22 6.3.2.2.3 SSR Receive Data Register Full (RDRF) Bit 2 . . . . . . . . . . . . . .6-23 6.3.2.2.4 SSR Idle Line Flag (IDLE) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 6.3.2.2.5 SSR Overrun Error Flag (OR) Bit 4 . . . . . . . . . . . . . . . . . . . . . . .6-23 6.3.2.2.6 SSR Parity Error (PE) Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 6.3.2.2.7 SSR Framing Error Flag (FE) Bit 6 . . . . . . . . . . . . . . . . . . . . . . .6-24 6.3.2.2.8 SSR Received Bit 8 Address (R8) Bit 7 . . . . . . . . . . . . . . . . . . . .6-24 6.3.2.3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . .6-24 6.3.2.3.1 SCCR Clock Divider (CD11–CD0) Bits 11–0 . . . . . . . . . . . . . . . .6-25 6.3.2.3.2 SCCR Clock Out Divider (COD) Bit 12 . . . . . . . . . . . . . . . . . . . .6-26 6.3.2.3.3 SCCR SCI Clock Prescaler (SCP) Bit 13 . . . . . . . . . . . . . . . . . . .6-26 viii TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 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Paragraph Number Title Page Number 6.3.2.3.4 SCCR Receive Clock Mode Source Bit (RCM) Bit 14 . . . . . . . . .6-26 6.3.2.3.5 SCCR Transmit Clock Source Bit (TCM) Bit 15 . . . . . . . . . . . . . .6-26 6.3.2.4 SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 6.3.2.4.1 SCI Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 6.3.2.4.2 SCI Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 6.3.2.5 Preamble, Break, and Data Transmission Priority . . . . . . . . . . . . . .6-30 6.3.3 Register Contents After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.3.4 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.3.5 SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6.3.6 Synchronous Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6.3.7 Asynchronous Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.3.7.1 Asynchronous Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45 6.3.7.2 Asynchronous Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 6.3.8 Multidrop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.3.8.1 Transmitting Data and Address Characters . . . . . . . . . . . . . . . . . . .6-57 6.3.8.2 Wired-OR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 6.3.8.3 Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 6.3.8.4 Address Mode Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61 6.3.8.5 Multidrop Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61 6.3.9 SCI Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 6.3.10 Bootstrap Loading Through the SCI (Operating Mode 6) . . . . . . . . . . . . 6-71 6.3.11 Example Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 6.4 SYNCHRONOUS SERIAL INTERFACE (SSI) . . . . . . . . . . . . . . . . . . . . . . 6-76 6.4.1 SSI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78 6.4.1.1 Serial Transmit Data Pin (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-78 6.4.1.2 Serial Receive Data Pin (SRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-80 6.4.1.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-80 6.4.1.4 Serial Control Pin (SC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 6.4.1.5 Serial Control Pin (SC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 6.4.1.6 Serial Control Pin (SC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83 6.4.2 SSI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 6.4.2.1 SSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 6.4.2.1.1 CRA Prescale Modulus Select (PM7–PM0) Bits 0–7 . . . . . . . . . .6-87 6.4.2.1.2 CRA Frame Rate Divider Control (DC4–DC0) Bits 8–12 . . . . . . .6-87 6.4.2.1.3 CRA Word Length Control (WL0, WL1) Bits 13 and 14 . . . . . . . .6-87 6.4.2.1.4 CRA Prescaler Range (PSR) Bit 15 . . . . . . . . . . . . . . . . . . . . . . .6-88 6.4.2.2 SSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-88 6.4.2.2.1 CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . . . . . . . . . . . .6-88 6.4.2.2.2 CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . . . . . . . . . . . .6-88 6.4.2.2.3 CRB Serial Control 0 Direction (SCD0) Bit 2 . . . . . . . . . . . . . . . .6-89 6.4.2.2.4 CRB Serial Control 1 Direction (SCD1) Bit 3 . . . . . . . . . . . . . . . .6-89 6.4.2.2.5 CRB Serial Control 2 Direction (SCD2) Bit 4 . . . . . . . . . . . . . . . .6-89 MOTOROLA TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com ix Freescale Semiconductor, Inc. Table of Contents (Continued) Freescale Semiconductor, Inc... Paragraph Number Title Page Number 6.4.2.2.6 CRB Clock Source Direction (SCKD) Bit 5 . . . . . . . . . . . . . . . . .6-89 6.4.2.2.7 CRB Shift Direction (SHFD) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . .6-91 6.4.2.2.8 CRB Frame Sync Length (FSL0 and FSL1) Bits 7 and 8 . . . . . .6-91 6.4.2.2.9 CRB Sync/Async (SYN) Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-91 6.4.2.2.10 CRB Gated Clock Control (GCK) Bit 10 . . . . . . . . . . . . . . . . . . . .6-91 6.4.2.2.11 CRB SSI Mode Select (MOD) Bit 11 . . . . . . . . . . . . . . . . . . . . . .6-92 6.4.2.2.12 CRB SSI Transmit Enable (TE) Bit 12 . . . . . . . . . . . . . . . . . . . . .6-92 6.4.2.2.13 CRB SSI Receive Enable (RE) Bit 13 . . . . . . . . . . . . . . . . . . . . .6-92 6.4.2.2.14 CRB SSI Transmit Interrupt Enable (TIE) Bit 14 . . . . . . . . . . . . .6-93 6.4.2.2.15 CRB SSI Receive Interrupt Enable (RIE) Bit 15 . . . . . . . . . . . . .6-93 6.4.2.3 SSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-94 6.4.2.3.1 SSISR Serial Input Flag 0 (IF0) Bit 0 . . . . . . . . . . . . . . . . . . . . . .6-94 6.4.2.3.2 SSISR Serial Input Flag 1 (IF1) Bit 1 . . . . . . . . . . . . . . . . . . . . . .6-94 6.4.2.3.3 SSISR Transmit Frame Sync Flag (TFS) Bit 2 . . . . . . . . . . . . . .6-94 6.4.2.3.4 SSISR Receive Frame Sync Flag (RFS) Bit 3 . . . . . . . . . . . . . . .6-95 6.4.2.3.5 SSISR Transmitter Underrun Error Flag (TUE) Bit 4 . . . . . . . . . .6-96 6.4.2.3.6 SSISR Receiver Overrun Error Flag (ROE) Bit 5 . . . . . . . . . . . . .6-96 6.4.2.3.7 SSISR SSI Transmit Data Register Empty (TDE) Bit 6 . . . . . . . .6-97 6.4.2.3.8 SSISR SSI Receive Data Register Full (RDF) Bit 7 . . . . . . . . . . .6-97 6.4.2.3.9 SSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-97 6.4.2.3.10 SSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . . . . . . . .6-97 6.4.2.3.11 SSI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-97 6.4.2.3.12 SSI Transmit Data Register (TX) . . . . . . . . . . . . . . . . . . . . . . . . .6-100 6.4.2.3.13 Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-100 6.4.3 Operational Modes and Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 6-100 6.4.4 Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100 6.4.5 SSI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 6.4.6 SSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109 6.4.7 Operating Modes – Normal, Network, and On-Demand. . . . . . . . . . . . . 6-112 6.4.7.1 Data/Operation Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-112 6.4.7.1.1 Normal/Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . .6-112 6.4.7.1.2 Continuous/Gated Clock Selection . . . . . . . . . . . . . . . . . . . . . . .6-113 6.4.7.1.3 Synchronous/Asynchronous Operating Modes . . . . . . . . . . . . . .6-113 6.4.7.1.4 Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-123 6.4.7.1.5 Shift Direction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-127 6.4.7.2 Normal Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-127 6.4.7.2.1 Normal Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-130 6.4.7.2.2 Normal Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-133 6.4.7.3 Network Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-135 6.4.7.3.1 Network Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-140 6.4.7.3.2 Network Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-144 6.4.7.4 On-Demand Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-145 x TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table of Contents (Continued) Paragraph Number Title Page Number Freescale Semiconductor, Inc... 6.4.7.4.1 On-Demand Mode – Continuous Clock . . . . . . . . . . . . . . . . . . . .6-148 6.4.7.4.2 On-Demand Mode – Gated Clock . . . . . . . . . . . . . . . . . . . . . . . .6-148 6.4.8 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-153 6.4.9 Example Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-157 SECTION 7 DSP56002 TIMER AND EVENT COUNTER 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 TIMER/EVENT COUNTER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . 7.3 TIMER COUNT REGISTER (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 TIMER CONTROL/STATUS REGISTER (TCSR) . . . . . . . . . . . . . . . . . . . . 7.4.1 Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Timer Interrupt Enable (TIE) Bit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Inverter (INV) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4 Timer Control (TC0-TC2) Bits 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 General Purpose I/O (GPIO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6 Timer Status (TS) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.7 Direction (DIR) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.8 Data Input (DI) Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.9 Data Output (DO) Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.10 TCSR Reserved bits (Bits 11-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 TIMER/EVENT COUNTER MODES OF OPERATION . . . . . . . . . . . . . . . . 7.5.1 Timer Mode 0 (Standard Timer Mode, Internal Clock, No Timer Output) . . . . . . . . . . . 7.5.2 Timer Mode 1 (Standard Timer Mode, Internal Clock, Output Pulse Enabled) . . . . . . . 7.5.3 Timer Mode 2 (Standard Timer Mode, Internal Clock, Output Toggle Enabled) . . . . . . 7.5.4 Timer Mode 4 (Pulse Width Measurement Mode) . . . . . . . . . . . . . . . . . 7.5.5 Timer Mode 5 (Period Measurement Mode). . . . . . . . . . . . . . . . . . . . . . 7.5.6 Timer Mode 6 (Standard Time Counter Mode, External Clock) . . . . . . . 7.5.7 Timer Mode 7 (Standard Timer Mode, External Clock) . . . . . . . . . . . . . 7.6 TIMER/EVENT COUNTER BEHAVIOR DURING WAIT and STOP . . . . . . 7.7 OPERATING CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 SOFTWARE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 General Purpose I/O Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 General Purpose I/O Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com 7-3 7-3 7-4 7-5 7-5 7-5 7-5 7-6 7-6 7-7 7-7 7-7 7-7 7-7 7-7 7-7 7-8 7-10 7-11 7-12 7-13 7-15 7-16 7-17 7-18 7-18 7-19 xi Freescale Semiconductor, Inc. Table of Contents (Continued) Paragraph Number Freescale Semiconductor, Inc... 7.8.3 7.8.4 7.8.5 Title Page Number Timer Mode 0, Input Clock, GPIO Output, and No Timer Output . . . . . . 7-20 Pulse Width Measurement Mode (Timer Mode 4) . . . . . . . . . . . . . . . . . 7-21 Period Measurement Mode (Timer Mode 5). . . . . . . . . . . . . . . . . . . . . . 7-22 APPENDIX A BOOTSTRAP AND ROM CODE A.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 APPENDIX B PROGRAMMING SHEETS B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 xii PERIPHERAL ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERRUPT VECTOR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CENTRAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GP I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TABLE OF CONTENTS For More Information On This Product, Go to: www.freescale.com B-3 B-4 B-5 B-10 B-14 B-16 B-21 B-24 B-27 MOTOROLA Freescale Semiconductor, Inc. LIST of FIGURES Freescale Semiconductor, Inc... Figure Number Title Page Number SECTION 1 1-1 1-2 DSP56002 Technical Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 DSP56002 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2-1 DSP56002 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-1 3-2 3-3 3-4 DSP56002 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Bootstrap Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56002 Interrupt Priority Register (IPR) . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 2 SECTION 3 SECTION 4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 Port A Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External X and Y Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Bootstrap ROM with X and Y RAM . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Bus Operation with No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Bus Operation with Two Wait States . . . . . . . . . . . . . . . . . . . . . . . . . Mixed-Speed Expanded System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Strobe/Wait Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Request/Bus Grant Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Using Only BR and BG with Internal Control . . . . . . . . . . . . Two DSPs with External Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Using BN, BR, and BG with External Control . . . . . . . . . . . . Bus Arbitration Using BR and BG, and WT and BS with No Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Two DSPs with External Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . 4-17 Signaling Using Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 5-3 5-4 5-5 5-6 SECTION 5 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port B Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B I/O Pin Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructions to Write/Read Parallel Data with Port B . . . . . . . . . . . . . . . . . . . MOTOROLA Revision 2.1 LIST of FIGURES For More Information On This Product, DSP56004 DESIGN SPECIFICATION Go to: www.freescale.com 3-5 3-6 3-9 3-13 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-12 4-14 4-15 4-17 4-19 4-19 4-20 4-21 4-22 4-23 5-3 5-4 5-5 5-6 5-7 5-8 xiii xiii Freescale Semiconductor, Inc. List of Figures (Continued) Freescale Semiconductor, Inc... Figure Number 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21a 5-21b 5-21c 5-21d 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 xiv Title Page Number I/O Port B Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface Programming Model – DSP Viewpoint . . . . . . . . . . . . . . . . . Host Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSR–HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Processor Programming Model – Host Side . . . . . . . . . . . . . . . . . . . . . HI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Processor Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Register Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Transfer Logic and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Initialization–DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Configuration–Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Initialization–Host Side, Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Initialization–Host Side, Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . HI Initialization–Host Side, DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Mode and INIT Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits Used for Host-to-DSP Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer from Host to DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Data from Host–Main Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Data from Host Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . . HI Exception Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Using the HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Code Fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits Used for DSP to Host Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer from DSP to Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Program - Transmit 24-Bit Data to Host . . . . . . . . . . . . . . . . . . . . . . . . Transmit to HI Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HI Hardware–DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Transfer and Host Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Bits with TREQ and RREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host-to-DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP to Host DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC11 to DSP56002 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68000 to DSP56002 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-DSP Network Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIST of FIGURES For More Information On This Product, Go to: www.freescale.com 5-9 5-12 5-13 5-16 5-19 5-21 5-22 5-26 5-33 5-34 5-36 5-37 5-38 5-39 5-40 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-54 5-55 5-56 5-57 5-58 5-61 5-62 5-63 5-64 MOTOROLA Freescale Semiconductor, Inc. List of Figures (Continued) Freescale Semiconductor, Inc... Figure Number 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 Title SECTION 6 Page Number Port C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C I/O Pin Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write/Read Parallel Data with Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Programming Model – Control and Status Registers . . . . . . . . . . . . . . . SCI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Formats (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Packing and Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI General Initialization Detail – Step 2 (Sheet 1 of 2) . . . . . . . . . . . . . . . . SCI Exception Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Synchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Synchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous SCI Receiver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Character Reception with Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous SCI Transmitter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous SCI Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Marks and Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Asynchronous Transmit/Receive Example (Sheet 1 of 3) . . . . . . . . . . . 11-Bit Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data and Address Characters . . . . . . . . . . . . . . . . . . . . . . . . . Wired-OR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mode Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multidrop Transmit Receive Example (Sheet 1 of 4) . . . . . . . . . . . . . . . . . . . SCI Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Timer Example (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56002 Bootstrap Example - Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Code Fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA LIST of FIGURES For More Information On This Product, Go to: www.freescale.com 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-13 6-14 6-16 6-25 6-27 6-29 6-33 6-34 6-38 6-40 6-42 6-43 6-44 6-45 6-46 6-47 6-49 6-50 6-51 6-52 6-53 6-56 6-58 6-59 6-60 6-62 6-64 6-69 6-70 6-72 6-73 6-74 xv Freescale Semiconductor, Inc. List of Figures (Continued) Freescale Semiconductor, Inc... Figure Number 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 6-51 6-52 6-53 6-54 6-55 6-56 6-57 6-58 6-59 6-60 6-61 6-62 6-63 6-64 6-65 6-66 6-67 6-68 6-69 6-70 6-71 6-72 6-73 6-74 6-75 6-76 6-77 6-78 6-79 xvi Title Page Number Master-Slave System Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multimaster System Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . SSI Frame Sync Generator Functional Block Diagram . . . . . . . . . . . . . . . . . SSI Programming Model — Control and Status Registers . . . . . . . . . . . . . . SSI Programming Model (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control, Direction Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Initialization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI CRA Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI CRB Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Exception Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . . . . . . . . . . . Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) . . . . . . . . . CRB GCK Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Clock Timing Diagram (8-Bit Example) . . . . . . . . . . . . . . . . . . . Internally Generated Clock Timing (8-Bit Example) . . . . . . . . . . . . . . . . . . . Externally Generated Gated Clock Timing (8-Bit Example) . . . . . . . . . . . . . Synchronous Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRB SYN Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated Clock — Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated Clock — Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Clock — Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . Continuous Clock — Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . CRB FSL0 and FSL1 Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode Initialization for FLS1=0 and FSL0=0 . . . . . . . . . . . . . . . . . . . Normal Mode Initialization for FSL1=1 and FSL0=0 . . . . . . . . . . . . . . . . . . . CRB SHFD Bit Operation (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode Transmit Example (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . Normal Mode Receive Example (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . Network Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TDM Network Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Mode Transmit Example Program (Sheet 1 of 2) . . . . . . . . . . . . . . Network Mode Receive Example Program (Sheet 1 of 2) . . . . . . . . . . . . . . LIST of FIGURES For More Information On This Product, Go to: www.freescale.com 6-75 6-75 6-80 6-81 6-84 6-85 6-90 6-98 6-99 6-104 6-105 6-106 6-107 6-110 6-111 6-114 6-115 6-115 6-116 6-117 6-118 6-119 6-120 6-121 6-122 6-122 6-122 6-122 6-124 6-125 6-126 6-128 6-130 6-132 6-134 6-136 6-137 6-139 6-141 6-143 MOTOROLA Freescale Semiconductor, Inc. List of Figures (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 6-80 6-81 6-82 6-83 6-84 6-85 6-86 6-87 6-88 6-89 6-90 6-91 6-92 6-93 6-94 6-95 6-96 6-97 On Demand Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Demand Data-Driven Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Demand Mode Example — Hardware Configuration . . . . . . . . . . . . . . . On-Demand Mode Transmit Example Program (Sheet 1 of 2) . . . . . . . . . . . On-Demand Mode Receive Example Program . . . . . . . . . . . . . . . . . . . . . . . Output Flag Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Flag Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Flag Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Cascaded Multi-DSP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI TDM Parallel DSP Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI TDM Connected Parallel Processing Array . . . . . . . . . . . . . . . . . . . . . . SSI TDM Serial/Parallel Processing Array . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Parallel Processing — Nearest Neighbor Array . . . . . . . . . . . . . . . . . . . SSI TDM Bus DSP Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI TDM Master-Slave DSP Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 Timer/Event Counter Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . Timer/Event Counter Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Timer Mode (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer/Event Counter Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=0) . . . . . Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=1) . . . . . Standard Timer Mode, Internal Clock, Output Toggle Enable . . . . . . . . . . . Pulse Width Measurement Mode (INV=0) . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Measurement Mode (INV=1) . . . . . . . . . . . . . . . . . . . . . . . . . . Period Measurement Mode (INV=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Period Measurement Mode (INV=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Time Counter Mode, External Clock (INV=0) . . . . . . . . . . . . . . . . Standard Timer Mode, External Clock (INV=1) . . . . . . . . . . . . . . . . . . . . . . . Standard Timer Mode, External Clock (INV=0) . . . . . . . . . . . . . . . . . . . . . . . Standard Timer Mode, External Clock (INV=1) . . . . . . . . . . . . . . . . . . . . . . . A-1 DSP56002 Bootstrap Program (Sheet 1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . A-4 B-1 B-2 B-3 B-4 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register (IPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 7 6-146 6-147 6-148 6-149 6-150 6-150 6-152 6-154 6-155 6-156 6-157 6-157 6-159 6-160 6-161 6-162 6-163 6-164 7-3 7-4 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 AAPPENDIX A BAPPENDIX B MOTOROLA LIST of FIGURES For More Information On This Product, Go to: www.freescale.com B-3 B-10 B-10 B-11 xvii Freescale Semiconductor, Inc. List of Figures (Continued) Freescale Semiconductor, Inc... Figure Number B-5 B-6 B-7 B-8 B-9 B-10 B-11 B-12 B-13 B-14 B-15 B-16 B-17 B-18 B-19 B-20 B-21 B-22 B-23 B-24 B-25 B-26 B-27 B-28 B-29 B-30 B-31 B-32 B-33 B-34 B-35 xviii Title Page Number Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Control Register (PBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Direction Register (PBDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register (PBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Control Register (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Direction Register (PCDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register (PCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Control Register (PBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Receive Data Register (HRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Control Register (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Control Register (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control and Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIST of FIGURES For More Information On This Product, Go to: www.freescale.com B-12 B-13 B-14 B-14 B-14 B-15 B-15 B-15 B-16 B-16 B-17 B-17 B-17 B-18 B-18 B-19 B-19 B-20 B-20 B-21 B-21 B-22 B-22 B-23 B-23 B-24 B-24 B-25 B-26 B-27 B-27 MOTOROLA Freescale Semiconductor, Inc. List of Figures (Continued) Title Page Number Freescale Semiconductor, Inc... Figure Number MOTOROLA LIST of FIGURES For More Information On This Product, Go to: www.freescale.com xix Freescale Semiconductor, Inc. List of Tables (Continued) Freescale Semiconductor, Inc... Table Number Title Page Number SECTION 1SECTION 1 SECTION 2SECTION 2 2-1 Program and Data Memory Select Encoding . . . . . . . . . . . . . . . . . . . . . . . .2-4 3-1 3-2 3-3 3-4 3-5 Memory Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 DSP56002 Operating Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 Organization of EPROM Data Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 Exception Priorities Within an IPL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 4-1 4-2 4-3 Program and Data Memory Select Encoding . . . . . . . . . . . . . . . . . . . . . . . .4-7 Wait State Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13 BR and BG During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17 5-1 5-2 5-3 5-4 5-5 5-6 Host Registers after Reset–DSP CPU Side . . . . . . . . . . . . . . . . . . . . . . . . .5-18 HREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24 HREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-25 Host Registers after Reset (Host Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 Port B Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 SECTION 3SECTION 3 SECTION 4SECTION 4 SECTION 5SECTION 5 SECTION 6SECTION 6 6-1 Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 6-2 SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-32 6-3a Asynchronous SCI Bit Rates for a 40-MHz Crystal. . . . . . . . . . . . . . . . . . . .6-36 6-3b Frequencies for Exact Asynchronous SCI Bit Rates. . . . . . . . . . . . . . . . . . .6-36 6-4a Synchronous SCI Bit Rates for a 32.768-MHz Crystal . . . . . . . . . . . . . . . . .6-37 6-4b Frequencies for Exact Synchronous SCI Bit Rates . . . . . . . . . . . . . . . . . . .6-37 6-5 Definition of SC0, SC1, SC2, and SCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 6-6 SSI Clock Sources, Inputs, and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 6-7 SSI Operation: Flag 0 and Rx Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 6-8 SSI Operation: Flag 1 and Rx Frame Sync. . . . . . . . . . . . . . . . . . . . . . . . . .6-83 6-9 SSI Operation: Tx and Rx Frame Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83 6-10 Number of Bits/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 6-11 Frame Sync Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-91 6-12 Mode and Pin Definition Table – Continuous Clock . . . . . . . . . . . . . . . . . . .6-101 6-13 Mode and Pin Definition Table – Gated Clock . . . . . . . . . . . . . . . . . . . . . . .6-102 6-14 SSI Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-103 6-15a SSI Bit Rates for a 40-MHz Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-15b SSI Bit Rates for a 39.936-MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-16 Crystal Frequencies Required for Codecs . . . . . . . . . . . . . . . . . . . . . . . . . .6-108 6-17 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-112 7-1 SECTION 7SECTION 7 Timer/Event Counter Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 APPENDIX A A-1 MOTOROLA LIST of TABLES For More Information On This Product, Go to: www.freescale.com xix Freescale Semiconductor, Inc. List of Tables (Continued) Table Number Title Page Number APPENDIX B B-1 Interrupts Starting Addresses and Sources . . . . . . . . . . . . . . . . . . . . . . . . .B-4 Instruction Set Summary — Sheet 1 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5 Freescale Semiconductor, Inc... B-1 B-2 xx LIST of TABLES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 User’s Manual Trouble Report DSP Applications Fax Number — (512) 891-4665 Dr. BuB Bulletin Board —891-DSP3 (8 data bits, no parity, 1 stop) Freescale Semiconductor, Inc... We welcome your comments and suggestions. They help us provide you with better product documentation. Please send your suggestions/corrections to the Fax number or Email address above or mail this completed form to: Motorola Inc. 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Attn: DSP Applications/Documentation Mail Drop: OE314 1. Did you find errors in the manual? Please give page number and a description of each error. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56002 User’s Manual Trouble Report Freescale Semiconductor, Inc... 2. Did you find the manual clear and easy to use? Please comment on specific sections that you feel need improvement. 3. What sections of this manual do you consider most important/least important? For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by DSP56002UMAD/AD DSP56002 Addendum to 24-bit Digital Signal Processor User’s Manual This document, containing changes, additional features, further explanations, and clarifications, is a supplement to the original document: Freescale Semiconductor, Inc... DSP56002UM/AD Rev. 1 User’s Manual DSP56002 24-bit Digital Signal Processor Change the following: Page 1-4, Section 1.2 - Insert after first group of bullets “PLL based clocking with wide input frequency range, wide range frequency multiplication (1 to 4096) and power saving clock divider (2i, i=0,...,15) to reduce clock noise” Page 1-4, Section 1.2 - Replace “24 General Purpose I/O Pins” with “25 General Purpose I/O pins” Page 1-6 - Replace with the following Figure 1-2. Page 2-14, Section 2.5 - Insert “Reset disables the TIO pin and causes it to be three-stated.” Page 3-11, Section 3.4.3, third sentence - Replace “Mode 0” with “Mode 2”. Page 5-19, Figure 5-11 - Replace “X:FFE” in two places with “X:$FFE8” on top and “X:FFE9” on bottom. Page 6-28, Program listing - Move: “MOVE (R0)+ ;and increment the packing pointer” to after the JCS instruction. Replace “RTI” with “RTI X:” Replace “FLAG with “FLAG MOVE MOVE A,(R3)+” A,X:(R3)+” Page 6-68, Section 6.3.9, third sentence - Replace “Bits CD11–CD0, SCP, and STIR in the SCCR work together to determine the time base.” with “Bits CD11–CD0 and SCP in the SCCR and the STIR bit in the SCR work together to determine the time base.” Page 6-127, Section 6.4.7.2, second paragraph - Replace “MC15500” with “MC145500”. Page 6-130, Figure 6-72 - Replace “MC1550x” with “MC14550x”. Page 6-155, Figure 6-88 - Replace “MC15500” with “MC145500”. Page B-11, Figure B-4 - Add programming description for IPR bits 16 and 17 (see Figure B-4 below). Page B-25, Figure B-32 - Change CRB bits 2-4 description (see Figure B-32 below). Page B-27, Figure B-34 - Change arrows pointing to Timer Enable bits 1 and 0 as shown in Figure B-34 below. MOTOROLA INC., 1995 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 1 6 3 24-bit Sync. Serial Host Timer / Serial Comm. Interface Event (SSI) (SCI) (HI) Counter or I/O or I/O or I/O Address Generation Unit 24-bit 56000 DSP Core Internal Data Bus Switch OnCETM Port PLL Interrupt Control Clock Program Address Generator Program Control Unit Gen. 7 Program Decode Controller 4 16-bit Bus 24-bit Bus 15 Program Memory 512 × 24 RAM 64 × 24 ROM (boot) X Data Memory 256 × 24 RAM 256 × 24 ROM (A-law / µ-law) Y Data Memory 256 × 24 RAM 256 × 24 ROM (sine) PAB XAB YAB External Address Bus Switch GDB PDB XDB YDB External Data Bus Switch Data ALU 24 × 24 + 56 → 56-bit MAC Two 56-bit Accumulators Bus Control Address 16 Data 24 Control 10 3 IRQ Figure 1-2 DSP56002 Block Diagram 2 DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com 3 4 DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com $0 TIL1 TIL0 SCL1 SCL0 SSL1 SSL0 HPL1 HPL0 8 7 6 5 3 IPL — 0 1 2 IPL — 0 1 2 2 1 0 * = Reserved, Program as zero IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 4 Enabled No Yes Yes Yes *0 *0 *0 *0 9 Figure B-4 Interrupt Priority Register (IPR) *0 *0 *0 *0 *0 *0 IBL0 0 1 0 1 Host IPL IBL1 0 0 1 1 IRQB Mode Enabled No Yes Yes Yes HPL1 HPL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 IBL2 Trigger 0 Level 1 Neg. Edge 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Enabled IPL No — Yes 0 Yes 1 Yes 2 Interrupt Priority Register (IPR) X:$FFFF Read/Write Reset = $000000 TIL1 TIL0 0 0 0 1 1 0 1 1 TIMER IPL SCL1 SCL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCI IPL IAL0 0 1 0 1 IAL1 0 0 1 1 SSL1 SSL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 IAL2 Trigger 0 Level 1 Neg. Edge IRQA Mode SSI IPL CENTRAL PROCESSOR Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SSI Serial Control Direction Bits 0 = Input 1 = Output Clock Source Direction 0 = External Clock 1 = Internal Clock Shift Direction 0 = MSB First 1 = LSB First Frame Sync Length 0 0 = Rx and Tx Same Length 1 = Rx and Tx Different Length Frame Sync Length 1 0 = Rx is Word Length 1 = Rx is Bit Length Sync/Async Control 0 = Asynchronous 1 = Synchronous Gated Clock Control 0 = Continuous Clock 1 = Gated Clock SSI Mode Select 0 = Normal 1 = Network Transmit Enable 0 = Disable 1 = Enable Output Flag x If SYN = 1 and SCD1=1 OFx SCx Pin Receive Enable 0 = Disable 1 = Enable Transmit Interrupt Enable 0 = Disable 1 = Enable Receive Interrupt Enable 0 = Disable 1 = Enable SSI Control Register B (CRB) X:$FFED Read/Write Reset = $000000 23 *0 •• • 15 14 13 12 11 10 RIE TIE RE 9 8 7 6 5 4 3 2 1 0 TE MOD GCK SYN FSL1 FSL0 SHFDSCKDSCD2 SCD1SCD0 OF1 OF0 * = Reserved, Program as zero Figure B-32 SSI Control Register B (CRB) 6 DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Sheet 1 of 1 Freescale Semiconductor, Inc... TIMER Timer Control Bits 3-5 (TC0 - TC2) TC2 TC1 TC0 TIO 0 0 0 GPIO 0 0 1 Output 0 1 0 Output 0 1 1 X 1 0 0 Input 1 0 1 Input 1 1 0 Input 1 1 1 Input Clock Internal Internal Internal X Internal Internal External External Mode Timer Timer Pulse Timer Toggle Undefined Input Width Input Period Standard Time Counter Event Counter Timer Status Bit 7 0 = TCSR read, or timer interrupt serviced 1 = Counter decremented to 0 Direction Bit 8 0 = TIO pin is input 1 = TIO pin is output Data Output Bit 10 0 =Zero written to TIO pin 1 = One written to TIO pin Timer Control and Status Register (TCSR) X:$FFDE (Read/Write) Reset = $000200 Timer Interrupt Enable Bit 1 0 = Interrupts Disabled 1 = Interrupts Enabled Inverter Bit 2 0 = 0- to-1 transitions on TIO input decrement the counter 1 = 1-to-0 transitions on TIO input decrement the counter or Timer pulse inverted before it goes to TIO output GPIO Bit 6 0 = TIO is Timer IO 1 = TIO is GPIO if TC2-TC0 are clear Data Input Bit 9 0 = Zero read on TIO pin 1 = One read on TIO pin Timer Enable Bit 0 0 = Timer Disabled 1 = Timer Enabled 23 *0 •• • 15 14 13 12 11 10 *0 *0 *0 *0 *0 DO 9 8 DI DIR 7 6 5 4 3 2 TS GPIO TC2 TC1 TC0 INV 1 0 TIE TE * = Reserved, Program as zero Figure B-34 Timer Control and Status Register (TCSR) MOTOROLA DSP56002 User’s Manual Addendum For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. OnCE is a trademark of Motorola, Inc. All product and brand names appearing herein are trademarks or registered trademarks of their respective holders. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical”, must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and b are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, United Kingdom. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR USER’S MANUAL ADDENDUM Order this document by: DSP56002UMAD2/D DSP56002 24-BIT DIGITAL SIGNAL PROCESSOR FAMILY This document, containing changes, additional features, further explanations, and clarifications, is a second addendum to the original document listed below: Document Name: Order Number: Revision: DSP56002 User’s Manual DSP56002UM/AD 1 Freescale Semiconductor, Inc... Change the following: Page 5-43 - In the first paragraph after item l0, delete “The code shown in Figure 5-25 is an excerpt from the Host I/O Port Technical Bulletin (in-house document).” Change the next sentence so that it begins “The MAIN PROGRAM in Figure 5-25 initializes...” Page 7-4 - Change “In Timer Modes 4 and 5” to read “In Timer Modes 4, 5 and 6” in the first line of the last paragraph. Page 7-6 - In the second paragraph of section 7.4.4, change “...is given in Chapter 3” to “...is given in Section 7.5.” Page 7-20 - In the fifth line of code, change the operand from “#$CF,MR” to #$FC,MR” for the ANDI instruction. Page 7-21 - In the eleventh line of code in section 7.8.4, change the operand from “#$CF,MR” to #$FC,MR” for the ANDI instruction. Page 7-22 - In the ninth line of code on the page, “#$CF,MR” to #$FC,MR” for the ANDI instruction. Page B-3 - In Figure B-1, the Timer Count Register should be shown as 24 bits long instead of 16 bits long. ©1996 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. OnCE, Motorola, and are registered trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. How to reach us: Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC Toshikatsu Otsuki 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 03-3521-8315 USA/Europe: Motorola Literature Distribution P.O. Box 20912 Phoenix, Arizona 85036 1 (800) 441-2447 Hong Kong: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-2662928 MFAX: [email protected] TOUCHTONE (602) 244-6609 Internet: http://motserv.indirect.com/dsp/DSPhome.html For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 1 INTRODUCTION TO THE DSP56002 MOTOROLA For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. SECTION CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW. . . . . . . . . . . . . . . . 1-4 1.4 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Freescale Semiconductor, Inc... 1.1 1-2 INTRODUCTION TO THE DSP56002 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION 1.1 INTRODUCTION This manual describes the DSP56002 24-bit digital signal processor, its memory and operating modes, and its peripheral modules. It is intended to be used with the DSP56K Central Processing Unit Manual (DSP56KFAMUM/AD), which describes the central processing unit, programming models, and includes details of the instruction set. The DSP56002 Technical Data Sheet (DSP56002/D) provides timing, pinout, and packaging descriptions (see Figure 1-1). Freescale Semiconductor, Inc... This section presents the DSP56002 features. 24-bit DSP56002 DSP56000 Family Manual Products Central Processor and Instruction Manual • central processor • instruction set # DSP56KFAMUM/AD DSP56002 User’s Manual # DSP56002UM/AD Device Manual • peripherals • memories DSP56002 Technical Data Specification • electrical • mechanical # DSP56002/D Figure 1-1 DSP56002 Technical Literature MOTOROLA INTRODUCTION TO THE DSP56002 For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. FEATURES Freescale Semiconductor, Inc... 1.2 FEATURES DSP56K Central Processing Unit (CPU) Features • 20 Million Instructions per Second (MIPS) at 40 MHz • Single-Cycle 24 x 24 Bit Parallel Multiply-Accumulator • Highly Parallel Instruction Set with Unique DSP Addressing Modes • Zero Overhead Nested DO Loops • Fast Auto-Return Interrupts • Fully Static Logic, Operation Frequency Down to DC • Very Low-power CMOS Design • STOP and WAIT Low-power Standby Modes DSP56002 Features • 512 x 24 Program RAM • Two 256 x 24 Data RAM • Two 256 x 24 Data ROM (Sine and Cosine Tables) • Full Speed Memory Expansion Port with 16-bit Address and 24-bit Data Buses • Byte-wide Host Interface with DMA Support • Synchronous Serial Interface Port • Serial Communication Interface (Asynchronous) Port • 24 General Purpose I/O Pins • 24-bit Timer/Event Counter* • On-chip Emulator (OnCE) for Unobtrusive, Full Speed Debugging • Optional Program Security Feature Disables Unauthorized Program ROM and OnCE Access • PLL Based Clocking with Wide Input Frequency Range, Wide Range Frequency Multiplication (1 to 4096) and Power Saving Clock Divider (2i, i=0,...,15) to Reduce Clock Noise 1.3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW The DSP56K series of 24-bit modular processors is built on a common central processing unit (CPU). In the expansion area around the CPU, the chip can support various configurations of memory and peripheral modules which may change between series members. * The first version of the DSP56002 (mask number D41G) did not have the timer/event counter. Later versions of the DSP56002 which have different mask numbers do have the timer/event counter. This mask number can be found below the part number on each chip. 1-4 INTRODUCTION TO THE DSP56002 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MANUAL ORGANIZATION Freescale Semiconductor, Inc... The central components are: • Data Buses • Address Buses • Data Arithmetic Logic Unit (data ALU) • Address Generation Unit (AGU) • Program Control Unit (PCU) • Memory Expansion (Port A) Figure 1-2 shows a block diagram of the DSP56002, including the CPU and the expansion area for memory and peripherals. The DSP56000 Family Manual (DSP56KFAMUM/AD) presents the details of each of the above CPU components. 1.4 MANUAL ORGANIZATION This manual includes the following sections: SECTION 2 — PIN DESCRIPTIONS presents the DSP56002 pinout. SECTION 3 — MEMORY MODULES AND OPERATING MODES presents the details of the DSP56002 memory maps and explains the various operating modes that affect the processor’s program and data memories. SECTION 4 — PORT A describes the external memory port, its registers, and control signals. SECTION 5 — PORT B describes the port B parallel I/O and the host interface, their registers, and their controls. SECTION 6 — PORT C describes the port C parallel I/O, the Synchronous Serial Interface, the Synchronous Communication Interface, their registers, and their controls. SECTION 7 — DSP56002 TIMER AND EVENT COUNTER describes the timer/counter and its registers and controls. APPENDIX A — BOOTSTRAP PROGRAM APPENDIX B — PROGRAMMING SHEETS TROUBLE REPORT — This trouble report is a form that allows the reader to notify the factory of any errors or discrepancies discovered in this manual. MOTOROLA INTRODUCTION TO THE DSP56002 For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. MANUAL ORGANIZATION 15 RAM 256X24 SINE ROM 256X24 YAB XAB PAB EXTERNAL ADDRESS BUS SWITCH BUS CONTROL 16 10 YDB INTERNAL DATA BUS SWITCH 5 PLL CLOCK GENERATOR XDB PDB EXTERNAL DATA BUS SWITCH 24 GDB PROGRAM PROGRAM PROGRAM DATA ALU INTERRUPT ADDRESS DECODE 24X24+56→56-BIT MAC CONTROLLER GENERATOR TWO 56-BIT ACCUMULATORS CONTROLLER Program Control Unit OnCE 4 2 CLOCK CONTROL 16 BITS 24 BITS Figure 1-2 DSP56002 Block Diagram 1-6 INTRODUCTION TO THE DSP56002 For More Information On This Product, Go to: www.freescale.com MOTOROLA PORT A ADDRESS GENERATION UNIT X MEMORY RAM 256X24 µ/A ROM 256X24 ADDRESS 24-Bit 56K CPU PROGRAM 512x24 RAM BOOTSTRAP 64x24 ROM DATA Freescale Semiconductor, Inc... HOST SSI SCI INTERFACE INTERFACE INTERFACE EXPANSION AREA Y MEMORY CONTROL 6 3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION 2 DSP56002 PIN DESCRIPTIONS MOTOROLA For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. SECTION CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 ON-CHIP EMULATION (OnCE) PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.4 PLL PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Freescale Semiconductor, Inc... 2.1 2-2 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION 2.1 INTRODUCTION This section introduces pins associated with the DSP56002. It divides the pins into their functional groups and explains the role each pin plays in the operation of the chip. It acts as a reference for following chapters which explain the chip’s peripherals in detail. Freescale Semiconductor, Inc... 2.2 SIGNAL DESCRIPTIONS The DSP56002 is available in a 132-pin grid array package or surface mount (Plastic Quad Flat Pack, or PQFP). The input and output signals are organized into the functional groups indicated in Section Figure 2-1. The signals are discussed in the paragraphs that follow. Number of Pins Functional Group Port A Data Bus 24 Port A Address 19 Port A Bus Control 7 Port B Host Interface 15 Port C Synchronous Comm. Interface 3 Port C Synchronous Serial Interface 6 Interrupt and Mode Control 4 PLL and Clock 7 On-chip Emulation (OnCE) 4 Power (VCC) 16 Ground (GND) 24 Timer 1 Reserved 2 Total (for the PGA package) 132 D0-D23 DGND(6) DVCC(3) A0-A15 PS DS X/Y AGND(5) AVCC(3) BN RD WR BR BG WT BS CGND CVCC MODC/NMI MODB/IRQB MODA/IRQA RESET EXTAL XTAL QGND(4) QVCC(4) TIO DSP56002 Port B HOST H0-H7 HA0-HA2 HR/W HEN HREQ HACK HGND(4) HVCC(2) Port C SCI RXD TXD SCLK Port A Data Port A Address Port A Control SVCC SGND(2) Port C SSI 132 pins OnCE DSCK/OS1 DSI/OS0 DSO DR PLL PVCC PGND PCAP CKP PLOCK PINIT Interrupt/ Mode Control Timer RESERVED (2) SC0-SC2 SCK SRD STD CLVCC CLGND CKOUT Figure 2-1 DSP56002 Signals 2.2.1 Port A Address and Data Bus The Port A address and data bus signals control the access to external memory. They are three-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation. Note: All unused inputs should have pull-up resistors for two reasons: 1) floating inputs draw excessive power, and 2) a floating input can cause erroneous operation. For MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc... example, during reset, all signals are three-stated. Without pull-up resistors, the BR and WT signals may become active, causing two or more memory chips to try to simultaneously drive the external bus, which can damage the memory chips. A pullup resistor in the 50K-ohm range should be sufficient. Also, for future enhancements, all reserved pins (see Section Figure 2-1) should be left unconnected. 2.2.1.1 Address (A0–A15) These three-state output pins specify the address for external program and data memory accesses. To minimize power dissipation, A0–A15 do not change state when external memory spaces are not being accessed. 2.2.1.2 Data Bus (D0–D23) These pins provide the bidirectional data bus for external program and data memory accesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted. 2.2.2 Port A Bus Control The Port A bus control signals are discussed in the following paragraphs. The bus control signals provide a means to connect additional bus masters (which may be additional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) through port A to the DSP56002. They are three-stated during reset and may require pull-up resistors to prevent erroneous operation. 2.2.2.1 Program Memory Select (PS) This three-state output is asserted only when external program memory is referenced (see Table 2-1). Table 2-1 Program and Data Memory Select Encoding 2-4 PS DS X/Y External Memory Reference 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data Memory on Data Bus 0 1 1 Program Memory on Data Bus (Not Exception) 0 1 0 External Exception Fetch: Vector or Vector +1 (Development Mode Only) 0 0 X Reserved 1 1 0 Reserved DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS 2.2.2.2 Data Memory Select (DS) This three-state output is asserted only when external data memory is referenced (see Table 2-1). 2.2.2.3 X/Y Select (X/Y) This three-state output selects which external data memory space (X or Y) is referenced by DS (see Table 2-1). Freescale Semiconductor, Inc... 2.2.2.4 Read Enable (RD) This three-state output is asserted to read external memory on the data bus (D0–D23). 2.2.2.5 Write Enable (WR) This three-state output is asserted to write external memory on the data bus (D0–D23). 2.2.2.6 Bus Needed (BN) The BN output pin is asserted whenever the chip requires the external memory expansion port (Port A). During instruction cycles where the external bus is not required, BN is deasserted. If an external device has requested the bus by asserting the BR input and the DSP has granted the bus (by asserting BG), the DSP will continue processing as long as no external accesses are required. If an external access is required and the chip is not the bus master, it will stop processing and remain in wait states until bus ownership is returned. If the BN pin is asserted when the chip is not the bus master, this indicates that processing has stopped and the DSP is waiting to acquire bus ownership. An external arbiter may use this pin to help decide when to return bus ownership to the DSP. Note: The BN pin cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signal BS. During hardware reset, BN is deasserted. 2.2.2.7 Bus Request (BR) When the bus request input (BR) is asserted, the DSP56002 will always relinquish the bus to an external device such as a processor or DMA controller. The external device will become the new master of the external address and data buses while the DSP continues internal operations using internal memory spaces. When BR is deasserted, the DSP56002 will again assume bus mastership. When BR is asserted, the DSP56002 will always release Port A, including A0–A15, D0– D23, and the bus control pins (PS, DS, X/Y, RD, WR, and BS) by placing them in the highimpedance state, after the execution of the current instruction has been completed. Note: To prevent erroneous operation, the BR pin should be pulled up when it is not in use. MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc... 2.2.2.8 Bus Grant (BG) When this output is asserted, it signals to the external device that it has been granted the external bus (i.e. Port A has been three-stated).This output is deasserted during hardware reset. 2.2.2.9 Bus Strobe (BS) The BS output is asserted when the DSP accesses Port A. It acts as an early indication of the state of the external bus access by the DSP56002. It may also be used with the bus wait input, WT, to generate wait states, a feature which provides capabilities such as connecting asynchronous devices to the DSP, allowing devices with differing timing requirements to reside in the same memory space, allowing a bus arbiter to provide a fast multiprocessor bus access, and providing an alternative to the WAIT and STOP instructions to halt the DSP at a known program location and have a fast restart. This output is deasserted during hardware reset. 2.2.2.10 Bus Wait (WT) For as long as it is asserted by an external device, this input allows that device to force the DSP56002 to generate wait states. If WT is asserted when BS is asserted, wait states will be inserted into the current cycle (see the DSP56002 Technical Data Sheet (DSP56002/D) for timing details. 2.2.3 Interrupt and Mode Control The interrupt and mode control pins select the chip’s operating mode as it comes out of hardware reset, and they receive interrupt requests from external sources. 2.2.3.1 Mode Select A/External Interrupt Request A (MODA/IRQA)/STOP Recovery This input pin has three functions. It works with the MODB and MODC pins to select the chip’s operating mode, it receives an interrupt request from an external source, and it turns on the internal clock generator, causing the chip to recover from the stop processing state. Reset causes this input to act as MODA. During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of MODA, MODB, and MODC and writes the information to the Operating Mode Register to set the chip’s operating mode. (Operating Modes are discussed in SECTION 3 MEMORY MODULES AND OPERATING MODES.) After the chip has left the reset state, the MODA pin automatically changes to external interrupt request IRQA. IRQA receives external interrupt requests. It can be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall 2-6 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases. Freescale Semiconductor, Inc... 2.2.3.2 Mode Select B/External Interrupt Request B (MODB/IRQB) This input pin works with the MODA and MODC pins to select the chip’s operating mode, and it receives an interrupt request from an external source. Reset causes this input to act as MODB. During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of the mode pins and writes the information to the Operating Mode Register, which sets the chip’s operating mode. After the chip has left the reset state, the MODB pin automatically changes to external interrupt request IRQB. IRQB receives external interrupt requests. It can be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. 2.2.3.3 Mode Select C/Non-Maskable Interrupt Request (MODC/NMI) This input pin works with the MODA and MODB pins to select the chip’s operating mode, and it receives an interrupt request from an external source. Reset causes this input to act as MODC. During reset, this pin should be forced to the desired state, because as the chip comes out of reset, it reads the states of the mode pins and writes the information to the Operating Mode Register, which sets the chip’s operating mode. After the chip has left the reset state, the MODC pin automatically changes to a nonmaskable interrupt request (NMI) input. The negative-edge triggered NMI receives nonmaskable interrupt requests. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. 2.2.3.4 Reset (RESET) This Schmitt trigger input pin is used to reset the DSP56002. When RESET is asserted, the DSP56002 is initialized and placed in the reset state. When RESET is deasserted, the chip writes the mode pin (MODA, MODB, MODC) information to the operating mode MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS register, setting the chip’s operating mode. The chip also samples the PINIT pin and writes its information into the PEN bit of the PLL Control Register, and it samples the CKP pin to determine the polarity of the CKOUT signal. When the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal. Freescale Semiconductor, Inc... 2.2.4 Power and Clock The power and clock signals are presented in the following paragraphs. 2.2.4.1 Power (Vcc), Ground (GND) There are six sets of power and ground pins: a set of eight (four power, four ground) for internal logic; a set of eight (three power, five ground) for the address bus output buffer; a set of nine (three power, six ground) for the data bus output buffer; a set of eleven (four power, seven ground) for ports B and C and for the OnCE; a set of one power and one ground for the PLL; and a set of one power and one ground for the CKOUT pin. Refer to the pin assignments in the Layout Practices section of the DSP56002 Technical Data Sheet (DSP56002/D). 2.2.4.2 External Clock/Crystal Input (EXTAL) The EXTAL input interfaces the internal crystal oscillator input to an external crystal or an external clock. 2.2.4.3 Crystal Output (XTAL) This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL should not be connected. It may be disabled through software control using the XTLD bit in the PLL control register. 2.2.5 Host Interface The following paragraphs discuss the host interface signals, which provide a convenient connection to another processor through Port B on the DSP56002. 2.2.5.1 Host Data Bus (H0–H7) This bidirectional data bus transfers data between the host processor and the DSP56002. It acts as an input unless HEN is asserted and HR/W is high, making H0–H7 become outputs and allowing the host processor to read DSP56002 data. It is high impedance when HEN is deasserted. H0–H7 can be programmed as general-purpose I/O pins (PB0–PB7) 2-8 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset. Freescale Semiconductor, Inc... 2.2.5.2 Host Address (HA0–HA2) These inputs provide the address selection for each host interface register. HA0–HA2 can be programmed as general-purpose I/O pins (PB8–PB10) when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset. 2.2.5.3 Host Read/Write (HR/W) This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W is stable when HEN is asserted. It can be programmed as a general-purpose I/O pin (PB11) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset. 2.2.5.4 Host Enable (HEN) This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56002 data. When HEN is asserted and HR/W is low, H0–H7 become inputs. When HEN is deasserted, host data is latched inside the DSP. Normally, a chip select signal derived from host address decoding and an enable clock are used to generate HEN. HEN can be programmed as a general-purpose I/O pin (PB12) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset. 2.2.5.5 Host Request (HREQ) This open-drain output signal is used by the host interface to request service from the host processor, DMA controller, or a simple external controller. HREQ can be programmed as a general-purpose I/O (not open-drain) pin (PB13) when the host interface is not being used. 2.2.5.6 Host Acknowledge (HACK) This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 Family processors. When the port is defined as the host interface and neither of the HACK pin’s two functions are being used, the user may program this input as a general-purpose I/O pin. For more details about the programming options for this pin, see Section 5.3.4.6 Host Acknowledge (HACK). This pin is configured as a GPIO input pin during hardware reset. Note: HACK should always be pulled high when it is not in use. MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2-9 Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc... 2.2.6 Serial Communication Interface (SCI) The following signals relate to the SCI. They are introduced briefly here and described in more detail in SECTION 6 - PORT C. 2.2.6.1 Receive Data (RXD) This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data is sampled on the positive or the negative edge of the receive clock, depending on how the SCI control register is programmed. RXD can be programmed as a general-purpose I/O pin (PC0) when it is not being used as an SCI pin, and it is configured as a GPIO input pin during hardware reset. 2.2.6.2 Transmit Data (TXD) This output transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the transmit clock. This output is stable on the positive or the negative edge of the transmit clock, depending on how the SCI control register is programmed. TXD can be programmed as a general-purpose I/O pin (PC1) when the SCI TXD function is not being used, and it is configured as a GPIO input pin during hardware reset. 2.2.6.3 SCI Serial Clock (SCLK) This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is transferred in the synchronous mode. SCLK can be programmed as a general-purpose I/O pin (PC2) when the SCI SCLK function is not being used, and it is configured as a GPIO input pin during hardware reset. 2.2.7 Synchronous Serial Interface (SSI) The SSI signals are presented in the following paragraphs.The SSI operating mode affects the definition and function of SSI control pins SC0, SC1, and SC2. They are introduced briefly here and are described in more detail in SECTION 6 - PORT C. 2.2.7.1 Serial Clock Zero (SC0) This bidirectional pin’s function is determined by whether the SCLK is in synchronous or asynchronous mode. In synchronous mode, this pin is used for serial flag I/O. In asynchronous mode, this pin receives clock I/O. SC0 can be programmed as a general-purpose I/O pin (PC3) when the SSI SC0 function is not being used, and it is configured as a GPIO input pin during hardware reset. 2 - 10 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. ON-CHIP EMULATION (OnCE) PINS Freescale Semiconductor, Inc... 2.2.7.2 Serial Control One (SC1) The SSI uses this bidirectional pin to control flag or frame synchronization. This pin’s function is determined by whether the SCLK is in synchronous or asynchronous mode.In asynchronous mode, this pin is frame sync I/O. For synchronous mode with continuous clock, this pin is serial flag SC1 and operates like the SC0. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC1 can be programmed as a general-purpose I/O pin (PC4) when the SSI SC1 function is not being used, and it is configured as a GPIO input pin during hardware reset. 2.2.7.3 Serial Control Two (SC2) The SSI uses this bidirectional pin to control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. SC2 can be programmed as a general-purpose I/O pin (PC5) when the SSI SC2 function is not being used, and it is configured as a GPIO input pin during hardware reset. 2.2.7.4 SSI Serial Clock (SCK) This bidirectional pin provides the serial bit rate clock for the SSI when only one clock is being used. SCK can be programmed as a general-purpose I/O pin (PC6) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset. 2.2.7.5 SSI Receive Data (SRD) This input pin receives serial data into the SSI receive shift register. SRD can be programmed as a general-purpose I/O pin (PC7) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset. 2.2.7.6 SSI Transmit Data (STD) This output pin transmits serial data from the SSI transmit shift register. STD can be programmed as a general-purpose I/O pin (PC8) when it is not needed as an SSI pin, and it is configured as a GPIO input pin during hardware reset. 2.3 ON-CHIP EMULATION (OnCE) PINS The following paragraphs describe the OnCE pins associated with the OnCE controller and its serial interface. 2.3.1 Debug Serial Input/Chip Status 0 (DSI/OS0) Serial data or commands are provided to the OnCE controller through the DSI/OS0 pin when it is an input. The data received on the DSI pin will be recognized only when the DSP56K has entered the debug mode of operation. Data is latched on the falling edge of MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2 - 11 Freescale Semiconductor, Inc. ON-CHIP EMULATION (OnCE) PINS the DSCK serial clock. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSI/OS0 pin is an output, it works in conjunction with the OS1 pin to provide chip status information (see Section 10 ON CHIP EMULATION (OnCE) in the DSP56000 Family Manual). The DSI/OS0 pin is an output when the processor is not in debug mode. When switching from output to input, the pin is three-stated. During hardware reset, this pin is defined as an output and it is driven low. Freescale Semiconductor, Inc... Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin. 2.3.2 Debug Serial Clock/Chip Status 1 (DSCK/OS1) The DSCK/OS1 pin supplies the serial clock to the OnCE when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The pin is three-stated when it is changing from input to output. When it is an output, it works with the OS0 pin to provide information about the chip status (see SECTION 10 ON CHIP EMULATION (OnCE) in the DSP56000 Family Manual). It is an output when the chip is not in debug mode. During hardware reset, this pin is defined as an output and is driven low. Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin. 2.3.3 Debug Serial Output (DSO) The DSP reads serial data from the OnCE through the DSO output pin, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port most significant bit (MSB) first. Data is clocked out of the OnCE serial port on the rising edge of DSCK. The DSO pin also provides acknowledge pulses to the external command controller. When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After receiving a read command, the DSO pin will be pulsed low to indicate that the requested data is available and the OnCE serial port is ready to receive clocks in order to deliver the data. After receiving a write command, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. During hardware reset and when the processor is idle, the DSO pin is held high. 2 - 12 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... PLL PINS 2.3.4 Debug Request Input (DR) The debug request input (DR) allows the user to enter the debug mode of operation from the external command controller. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the DSI line. While in debug mode, the DR pin lets the user reset the OnCE controller by asserting it and deasserting it after receiving an acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. Asserting DR when the DSP is in the WAIT or the STOP state, and keeping it asserted until an acknowledge pulse in the DSP is produced, sends the DSP into the debug mode. After receiving the acknowledge, DR must be deasserted before sending the first OnCE command. For more information, see Section 10.6 METHODS OF ENTERING THE DEBUG MODE in the DSP56000 Family Manual (DSP56KFAMUM/AD). 2.4 PLL PINS The following pins are dedicated to the PLL operation: • • • • • Analog PLL Circuit Power (PVCC) — The Vcc input is dedicated to the analog PLL circuits. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the Vcc power rail. PVcc should be bypassed to PGND by a 0.1µF capacitor located as close as possible to the chip package. Analog PLL Circuit Ground (PGND) — This GND input is dedicated to the analog PLL circuits. The pin should be provided with an extremely low impedance path to ground. PVcc should be bypassed to PGND by a 0.1µF capacitor located as close as possible to the chip package. CKOUT Power (CLVCC) — This input acts as VCC for the CKOUT output. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the VCC power rail. CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as close as possible to the chip package. CKOUT Ground (CLGND) — This input acts as GND for the CKOUT output. The pin should be provided with an extremely low impedance path to ground. CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as close as possible to the chip package. PLL Filter Capacitor (PCAP) — This input is used to connect an external capacitor needed for the PLL filter. One terminal of the capacitor is connected to PCAP while the other terminal is connected to PVCC. The capacitor value is specified in the DSP56002 Technical Data Sheet (DSP56002/D). MOTOROLA DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com 2 - 13 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TIMER/EVENT COUNTER MODULE PIN • Output Clock (CKOUT) — This output pin provides a 50% duty cycle output clock synchronized to the internal processor clock when the PLL is enabled and locked. When the PLL is disabled, the output clock at CKOUT is derived from, and has the same frequency and duty cycle as, EXTAL. Note: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CKOUT is synchronized to EXTAL. (For information on the DSP56002’s PLL multiplication factor, see Section Section 3.6 PLL MULTIPLICATION FACTOR. • CKOUT Polarity Control (CKP) — This input pin defines the polarity of the CKOUT clock output. Strapping CKP through a resistor to GND will make the CKOUT polarity the same as the EXTAL polarity. Strapping CKP through a resistor to Vcc will make the CKOUT polarity the inverse of the EXTAL polarity. The CKOUT clock polarity is internally latched at the end of the hardware reset, so that any changes of the CKP pin logic state after deassertion of hardware reset will not affect the CKOUT clock polarity. PLL Initialization Input (PINIT) — During the assertion of hardware reset, the value at the PINIT input pin is written into the PEN bit of the PLL control register. The PEN bit enables the PLL by causing it to derive the internal clocks from the PLL VCO output. When the bit is clear, the PLL is disabled and the chip’s internal clocks are derived from the clock connected to the EXTAL pin. After hardware reset is deasserted, the PINIT pin is ignored. Phase and Frequency Locked (PLOCK) — The PLOCK output originates from the Phase Detector. The chip asserts PLOCK when the PLL is enabled and has locked on the proper phase and frequency of EXTAL. The PLOCK output is deasserted by the chip if the PLL is enabled and has not locked on the proper phase and frequency. PLOCK is asserted if the PLL is disabled. PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the hardware reset state. During hardware reset, the PLOCK state is determined by PINIT and by the PLL lock condition. • • 2.5 TIMER/EVENT COUNTER MODULE PIN The bidirectional TIO pin is the pin that provides an interface to the timer/event counter module. When the TIO is used as an input, the module functions as an external event counter, or it measures external pulse width/signal period. When the TIO is used as an output, the module functions as a timer and the signal on the TIO pin is the timer pulse. When the timer module is not using the TIO pin, the TIO can act as a general purpose I/O pin. 2 - 14 DSP56002 PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 3 Freescale Semiconductor, Inc... MEMORY MODULES AND OPERATING MODES MOTOROLA For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. SECTION CONTENTS MEMORY MODULES AND OPERATING MODES . . . . . . . . . . . . . . . . . . . 3-3 3.2 DSP56002 DATA AND PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 DSP56002 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . . . . 3-4 3.4 DSP56002 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5 DSP56002 INTERRUPT PRIORITY REGISTER. . . . . . . . . . . . . . . . . . . . . 3-12 3.6 DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR . . 3-13 Freescale Semiconductor, Inc... 3.1 3-2 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MEMORY MODULES AND OPERATING MODES Freescale Semiconductor, Inc... 3.1 MEMORY MODULES AND OPERATING MODES The memory of the DSP56002 can be partitioned in several ways to provide high-speed parallel operation and additional off-chip memory expansion. Program and data memory are separate, and the data memory is, in turn, divided into two separate memory spaces, X and Y. Both the program and data memories can be expanded off-chip. There are also two on-chip data read-only memories (ROMs) that can overlay a portion of the X and Y data memories, and a bootstrap ROM that can overlay part of the program random-access memory (RAM). The data memories are divided into two independent spaces to work with the two address arithmetic logic units (ALUs) to feed two operands simultaneously to the data ALU. The DSP operating modes determine the memory maps for program and data memories and the start-up procedure when the DSP leaves the reset state. This section describes the DSP56002 Operating Mode Register (OMR), its operating modes and their associated memory maps, and discusses how to set and reset operating modes. This section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the PLL multiplication factor. 3.2 DSP56002 DATA AND PROGRAM MEMORY The DSP56002 has 512 words of program RAM, 64 words of bootstrap ROM, 256 words of RAM and 256 words of ROM for each of the X and Y internal data memories. The memory maps are shown in Section Figure 3-1 DSP56002 Memory Maps. 3.2.1 Program Memory The DSP56002 has 512 words of program RAM and 64 words of factory-programmed bootstrap ROM. The bootstrap ROM is programmed to perform the bootstrap operation from the memory expansion port (port A), from the host interface, or from the SCI. It provides a convenient, low cost method of loading the program RAM with a user program after power-on reset. The bootstrap ROM activity is controlled by the MA, MB, and MC bits in the OMR (see 3.3 DSP56002 OPERATING MODE REGISTER (OMR) for a complete explanation of the OMR and the DSP56002’s operating modes and memory maps). Addresses are received from the program control logic (usually the program counter) over the PAB. Program memory may be written using the program memory (MOVEM) instructions. The interrupt vectors are located in the bottom 128 locations ($0000-$007F) of program memory. Program memory may be expanded to 64K off-chip. MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. DSP56002 OPERATING MODE REGISTER (OMR) Freescale Semiconductor, Inc... 3.2.2 X Data Memory The on-chip X data RAM is a 24-bit-wide, static internal memory occupying the lowest 256 locations (0–255) in X memory space. The on-chip X data ROM occupies locations 256– 511 in the X data memory space and is controlled by the DE bit in the OMR. (See the explanation of the DE bit in Section 3.3.2 Data ROM Enable (Bit 2). Also, see Figure 31.)The on-chip peripheral registers occupy the top 64 locations of the X data memory ($FFC0–$FFFF). The 16-bit addresses are received from the XAB, and 24-bit data transfers to the data ALU occur on the XDB. The X memory may be expanded to 64K off-chip. 3.2.3 Y Data Memory The on-chip Y data RAM is a 24-bit-wide internal static memory occupying the lowest 256 locations (0–255) in the Y memory space. The on-chip Y data ROM occupies locations 256–511 in Y data memory space and is controlled by the DE and YD bits in the OMR. (See the explanations of the DE and YD bits in Sections Section 3.3.2 Data ROM Enable (Bit 2) and Section 3.3.3 Internal Y Memory Disable Bit (Bit 3), respectively. Also, see Figure 3-1.) The 16-bit addresses are received from the YAB, and 24-bit data transfers to the data ALU occur on the YDB. Y memory may be expanded to 64K off-chip. Note: The off-chip peripheral registers should be mapped into the top 64 locations ($FFC0– $FFFF) to take advantage of the move peripheral data (MOVEP) instruction. 3.3 DSP56002 OPERATING MODE REGISTER (OMR) Operating modes determine the memory maps for program and data memories, and the start-up procedure when the DSP leaves the reset state. The processor samples the MODA, MODB, and MODC pins as it leaves the reset state, establishes the initial operating mode, and writes the operating mode information to the Operating Mode Register. When the processor leaves the reset state, the MODA and MODB pins become general-purpose interrupt pins, IRQA and IRQB, respectively, and the MODC pin becomes the nonmaskable interrupt pin NMI. The OMR is a 24-bit register (only six bits are defined) that controls the current operating mode of the processor. It is located in the DSP56002’s Program Control Unit (described in Section 5 of the DSP56000 Family Manual). The OMR bits are only affected by processor reset and by the ANDI, ORI, MOVEC, BSET, BCLR, and BCHG instructions, which directly reference the OMR. The OMR format for the DSP56002 is shown in Figure 3-2 OMR Format. 3-4 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 OPERATING MODE REGISTER (OMR) $FFFF $FFFF $FFFF PROGRAM MEMORY SPACE X DATA MEMORY SPACE Y DATA MEMORY SPACE $7F INTERRUPT VECTORS Freescale Semiconductor, Inc... $0 $0 OPERATING MODE DETERMINES PROGRAM MEMORY AND RESET STARTING ADDRESS MODE 0 MC=0 MB=0 MA=0 MODE 3 MODE 2 MC=0 MB=1 MA=0 MC=0 MB=1 MA=1 $FFFF $FFFF $FFFF EXTERNAL EXTERNAL $003F INTERRUPTS $0 $01FF INTERNAL RAM $003F RESET INTERNAL P: RAM INTERNAL RESET $003F INTERRUPTS INTERRUPTS $0 $0 RESET $01FF INTERNAL X ROM +A-LAW/LIN $017F INTERNAL X ROM +MU-LAW/LIN $00FF INTERNAL $0 ON-CHIP PERIPHERAL MAP HOST COMMANDS DE = 0 YD = 0 $FFFF ON-CHIP $FFC0 PERIPHERALS EXTERNAL X DATA MEMORY EXTERNAL Y DATA MEMORY EXTERNAL Y DATA MEMORY INTERNAL Y ROM FULL SINE-WAVE INTERNAL Y RAM $00FF INTERNAL INTERNAL X RAM Y RAM $0 DATA ROMS DISABLED DE = 1 YD = 1 $FFFF ON-CHIP $FFC0 PERIPHERALS $FFBF EXTERNAL PERIPHERALS EXTERNAL PERIPHERALS DE = 0 YD = 1 $FFFF ON-CHIP $FFC0 PERIPHERALS EXTERNAL PERIPHERALS $FFFF INTERRUPT PRIORITY BUS CONTROL SCI INTERFACE SSI INTERFACE HOST INTERFACE PARALLEL I/0 INTERFACE TIMER ILLEGAL INSTRUCTION INT. TIMER INTERRUPT HOST COMMANDS SCI INTERRUPTS SSI INTERRUPTS EXTERNAL INTERRUPTS SWI INTERRUPT TRACE INTERRUPT STACK ERROR INTERRUPT $0000 RESET X RAM EXTERNAL PERIPHERALS DATA ROMS ENABLED INTERNAL P: RAM NO INTERNAL P: RAM EXTERNAL RESET EXTERNAL RESET INTERRUPT MAP $007F $0040 $003E $003C $003A $0024 EXTERNAL X DATA MEMORY EXTERNAL $01FF INTERNAL RAM DE = 1 YD = 0 $FFFF ON-CHIP $FFC0 PERIPHERALS $FFBF RESET $E000 $01FF $0 DE and YD BITS IN THE OMR DETERMINE THE X AND Y DATA MEMORY MAPS $FFDE RESERVED $FFC0 EXTERNAL X DATA MEMORY EXTERNAL Y DATA MEMORY EXTERNAL Y DATA MEMORY $01FF INTERNAL X ROM +A-LAW/LIN $017F INTERNAL X ROM +MU-LAW/LIN $00FF INTERNAL $0 X RAM $00FF INTERNAL X RAM $0 NOTE: Addresses $FFC0–$FFFF in X data memory are NOT available externally Figure 3-1 DSP56002 Memory Maps MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3-5 Freescale Semiconductor, Inc. DSP56002 OPERATING MODE REGISTER (OMR) 23 8 * 7 6 5 4 3 * SD * MC YD 2 1 0 DE MB MA OPERATING MODES A, B DATA ROM ENABLE INTERNAL Y MEMORY DISABLE OPERATING MODE C RESERVED STOP DELAY Freescale Semiconductor, Inc... RESERVED RESERVED Figure 3-2 OMR Format 3.3.1 Chip Operating Mode (Bits 0 and 1) The chip operating mode bits, MB and MA, together with MC, define the program memory maps and the operating mode of the DSP56002. On processor reset, MB and MA are loaded from the external mode select pins, MODB and MODA, respectively. After the DSP leaves the reset state, MB and MA can be changed under software control. 3.3.2 Data ROM Enable (Bit 2) The DE bit enables the two, on-chip, 256X24 data ROMs located between addresses $0100–$01FF in the X and Y memory spaces. When DE is cleared, the $0100–$01FF address space is part of the external X and Y data spaces, and the on-chip data ROMs are disabled. Hardware reset clears the DE bit. 3.3.3 Internal Y Memory Disable Bit (Bit 3) Bit 3 is defined as Internal Y Memory Disable (YD). When set, all Y Data Memory addresses are considered to be external, disabling access to internal Y Data Memory. When cleared, internal Y Data Memory may be accessed according to the state of the DE control bit. The content of the internal Y Data Memory is not affected by the state of the YD bit. The YD bit is cleared during hardware reset. Figure 3-1 DSP56002 Memory Maps shows a graphic representation of the DE and YD bit effects on the X and Y data memory maps. Table 3-1 also compares the DE and YD effects on the memory maps. 3-6 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 OPERATING MODES Freescale Semiconductor, Inc... Table 3-1 Memory Mode Bits DE YD Data Memory 0 0 Internal ROMs Disabled and their addresses are part of External Memory 0 1 Internal X Data ROM is Disabled and is part of External Memory. Internal Y Data RAM and ROM are Disabled and are part of External Memory 3.3.4 Chip Operating Mode (Bit 4) The MC bit, together with bits MA and MB, define the program memory map and the operating mode of the chip. Upon reset, the processor loads this bit from the MODC external mode select pin. After the DSP leaves the reset state, MC can be changed under software control. 3.3.5 Reserved (Bit 5) This bit is reserved for future expansion and will be read as zero during read operations. 3.3.6 Stop Delay (Bit 6) The SD bit determines the length of the clock stabilization delay that occurs when the processor leaves the stop processing state. If the stop delay bit is zero when the chip leaves the stop state, a 64K clock cycle delay is selected before continuing the stop instruction cycle. However, if the stop delay bit is one, the delay before continuing the instruction cycle is long enough to allow a clock stabilization period for the internal clock to begin oscillating and to stabilize. (See the DSP56002 Technical Data Sheet (DSP56002/D) for the actual timing values.) When a stable external clock is used, the shorter delay allows faster start-up of the DSP. 3.3.7 Reserved OMR Bits (Bits 7–23) These bits are reserved for future expansion and will be read as zero during read operations. 3.4 DSP56002 OPERATING MODES The user can set the chip operating mode through hardware by pulling high the MODC, MODB, and MODA pins appropriately, and then assert the RESET pin. When the DSP leaves the reset state, it samples the mode pins and writes to the OMR to set the initial operating mode. MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3-7 Freescale Semiconductor, Inc. DSP56002 OPERATING MODES Chip operating modes can also be changed using software to write the operating mode bits (MC, MB, MA) in the OMR. Changing operating modes does not reset the DSP. Note: The user should disable interrupts immediately before changing the OMR to prevent an interrupt from going to the wrong memory location. Also, one no-operation (NOP) instruction should be included after changing the OMR to allow for remapping to occur. Freescale Semiconductor, Inc... Table 3-2 DSP56002 Operating Mode Summary Operating Mode M C M B M A 0 0 0 0 Single-Chip Mode - P: RAM enabled, reset @ $0000 1 0 0 1 Bootstrap from EPROM, exit in Mode 0 2 0 1 0 Normal Expanded Mode - P: RAM enabled, reset @ $E000 3 0 1 1 Development Mode - P: RAM disabled, reset @ $0000 4 1 0 0 Reserved for Bootstrap 5 1 0 1 Bootstrap from Host, exit in Mode 0 6 1 1 0 Bootstrap from SCI (external clock), exit in Mode 0 7 1 1 1 Reserved for Bootstrap Description 3.4.1 Single Chip Mode (Mode 0) In the single-chip mode, all internal program and data RAM memories are enabled (see Figure 3-1). A hardware reset causes the DSP to jump to internal program memory location $0000 and resume execution. The memory maps for mode 0 and mode 2 (see Figure 3-1) are identical. The difference between the two modes is that reset vectors to program memory location $0000 in mode 0 and vectors to location $E000 in mode 2. 3.4.2 Bootstrap From EPROM (Mode 1) The bootstrap modes allow the DSP to load a program from an inexpensive byte-wide ROM into internal program memory during a power-on reset. On power-up, the waitstate generator adds 15 wait states to all external memory accesses so that slow memory can be used. The bootstrap program uses the bytes in three consecutive memory locations in the external ROM to build a single word in internal program memory. 3-8 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 OPERATING MODES In the bootstrap mode, the chip enables the bootstrap ROM and executes the bootstrap program. (The bootstrap program code is shown in Appendix A.) The bootstrap ROM contains the bootstrap firmware program that performs initial loading of the DSP56002 program RAM. Written in DSP56002 assembly language, the program initializes the program RAM by loading from an external byte-wide EPROM starting at location P:$C000. Freescale Semiconductor, Inc... The EPROM is typically connected to the chip’s address and data bus.The data contents of the EPROM must be organized as shown in Table 3-3 Organization of EPROM Data Contents. +5 V DR DSP56002 BR HACK WT MODA/IRQA FROM OPEN COLLECTOR BUFFER 2716 MODC/NMI MBD301* PS MBD301* A0-A10 FROM RESET FUNCTION RESET D0-D7 CE 11 8 A0-A10 D0-D7 MBD301* FROM OPEN COLLECTOR BUFFER MODB/IRQB Notes: 1. *These diodes must be Schottky diodes. 2. All resistors are 15KΩ unless noted otherwise. 3. When in RESET, IRQA, IRQB and NMI must be deasserted by external peripherals. ADDRESS OF EXTERNAL BYTE-WIDE P MEMORY CONTENTS LOADED TO INTERNAL P: RAM AT: P:$C000 P:$C001 P:$C002 • • • P:$C5FD P:$C5FE P:$C5FF P:$0000 LOW BYTE P:$0000 MID BYTE P:$0000 HIGH BYTE • • • P:$01FF LOW BYTE P:$01FF MID BYTE P:$01FF HIGH BYTE Figure 3-3 Port A Bootstrap Circuit MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3-9 Freescale Semiconductor, Inc. DSP56002 OPERATING MODES Table 3-3 Organization of EPROM Data Contents Freescale Semiconductor, Inc... Address of External Byte-Wide Memory: Contents Loaded to Internal Program RAM at: P:$C000 P:$0000 low byte P:$C001 P:$0000 mid byte P:$C002 P:$0000 high byte • • • • • • P:$C5FD P:$01FF low byte P:$C5FE P:$01FF mid byte P:$C5FF P:$01FF high byte After loading the internal memory, the DSP switches to the single-chip mode (Mode 0) and begins program execution at on-chip program memory location $0000. If the user selects Mode 1 through hardware (MODA, MODB, MODC pins), the following actions occur once the processor comes out of the reset state. 1. The control logic maps the bootstrap ROM into the internal DSP program memory space starting at location $0000. 2. The control logic causes program reads to come from the bootstrap ROM (only address bits 5–0 are significant) and all writes go to the program RAM (all address bits are significant). This condition allows the bootstrap program to load the user program from $0000–$01FF. 3. Program execution begins at location $0000 in the bootstrap ROM. The bootstrap ROM program loads program RAM from the external byte-wide EPROM starting at P:$C000. 4. The bootstrap ROM program ends the bootstrap operation and begins executing the user program. The processor enters Mode 0 by writing to the OMR. This action is timed to remove the bootstrap ROM from the program memory map and re-enable read/write access to the program RAM. The change to Mode 0 is timed to allow the bootstrap program to execute a single-cycle instruction (clear status register), then a JMP #<00, and begin execution of the user program at location $0000. 3 - 10 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 OPERATING MODES The user can also get into the bootstrap mode (Mode 1) through software by writing zero to MC and MB, and one to MA in the OMR. This selection initiates a timed operation to map the bootstrap ROM into the program address space (after a delay to allow execution of a single-cycle instruction), and then a JMP #<00 to begin the bootstrap process described previously in steps 1 through 4. This technique allows the user to reboot the system (with a different program, if desired). Freescale Semiconductor, Inc... The code to enter the bootstrap mode is as follows: MOVEP #0,X:$FFFF ;Disable interrupts. MOVEC #1,OMR ;The bootstrap ROM is mapped ;into the lowest 64 locations ;in program memory. NOP JMP ;Allow one cycle delay for the ;remapping. <$0 ;Begin bootstrap. The code disables interrupts before executing the bootstrap code. Otherwise, an interrupt could cause the DSP to execute the bootstrap code out of sequence because the bootstrap program overlays the interrupt vectors. 3.4.3 Normal Expanded Mode (Mode 2) In this mode, the internal program RAM is enabled and the hardware reset vectors to location $E000. (The memory maps for Mode 0 and Mode 2 are identical. The difference for Mode 0 is that, after reset, the instruction at location $E000 is executed instead of the instruction at $0000 — see Figure 3-1 and Table 3-2). 3.4.4 Development Mode (Mode 3) In this mode, the internal program RAM is disabled and the hardware reset vectors to location $0000. All references to program memory space are directed to external program memory. The reset vector points to location $0000. The memory map for this mode is shown in Figure 3-1 and Table 3-2. 3.4.5 Reserved (Mode 4) This mode is reserved for future definition. If selected, it defaults to Mode 5. 3.4.6 Bootstrap From Host (Mode 5) In this mode, the Bootstrap ROM is enabled and the bootstrap program is executed. This is similar to Mode 1 except that the bootstrap program loads internal P: RAM from the Host Port. MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3 - 11 Freescale Semiconductor, Inc. DSP56002 INTERRUPT PRIORITY REGISTER Freescale Semiconductor, Inc... Note: The difference between Modes 1 and 5 in the DSP56002 and Mode 1 in the DSP56001 may be considered software incompatibility. A DSP56001 program that reloads the internal P: RAM from the Host Port by setting MB-MA = 01 (assuming external pull-up resistor on bit 23 of P:$C000) will not work correctly in the DSP56002. In the DSP56002, the program would trigger a bootstrap from the external EPROM. The solution is to modify the DSP56001 program to set MC-MA = 101. 3.4.7 Bootstrap From SCI (Mode 6) In this mode, the Bootstrap ROM is enabled and the bootstrap program is executed. The internal and/or external program RAM is loaded from the SCI serial interface. The number of program words to load and the starting address must be specified. The SCI bootstrap code expects to receive 3 bytes specifying the number of program words, 3 bytes specifying the address from which to start loading the program words, and then 3 bytes for each program word to be loaded. The number of words, the starting address and the program words are received least significant byte first, followed by the mid-, and then by the most significant byte. After receiving the program words, program execution starts at the address where the first instruction was loaded. The SCI is programmed to work in asynchronous mode with 8 data bits, 1 stop bit, and no parity. The clock source is external and the clock frequency must be 16x the baud rate. After each byte is received, it is echoed back through the SCI transmitter. 3.4.8 Reserved (Mode 7) This mode is reserved for future definition. If selected, the processor defaults to Mode 6. 3.5 DSP56002 INTERRUPT PRIORITY REGISTER Section 7 of the DSP56000 Family Manual describes interrupt (exception) processing in detail. It discusses interrupt sources, interrupt types, and interrupt priority levels (IPL). Interrupt priority levels for each on-chip peripheral device and for each external interrupt source can be programmed under software control by writing to the interrupt priority register. Level 3 interrupts are nonmaskable, and interrupts of levels 0-2 are maskable. The DSP56002 Interrupt Priority Register (IPR) configuration is shown in Section Figure 3-4 DSP56002 Interrupt Priority Register (IPR). The starting addresses of interrupt vectors in the DSP56002 are defined as shown in Section Table 3-4 Interrupt Vectors, while the relative priorities of exceptions within the same IPL are defined as shown in Section Table 3-5 Exception Priorities Within an IPL). 3 - 12 MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR 11 10 9 8 7 6 HPL1 HPL0 5 4 3 2 1 0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 IRQA MODE IRQB MODE RESERVED HOST IPL Freescale Semiconductor, Inc... 23 22 21 20 19 18 17 16 15 14 13 12 TIL1 TIL0 SCL1 SCL0 SSL1 SSL0 SSI IPL SCI IPL TIMER IPL RESERVED Reserved, read as zero and should be written with zero for future compatibility. Figure 3-4 DSP56002 Interrupt Priority Register (IPR) 3.6 DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR Section 9 of the DSP56000 Family Manual discusses the details of the PLL. The multiplication factor determines the frequency at which the Voltage Controlled Oscillator (VCO) will oscillate. The user sets the multiplication factor by writing to the MF0-MF11 bits in the PLL control register. The DSP56002 PLL multiplication factor is set to 1 during hardware reset, which means that the Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $000. MOTOROLA MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3 - 13 Freescale Semiconductor, Inc. DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR Freescale Semiconductor, Inc... Table 3-4 Interrupt Vectors 3 - 14 Interrupt Starting Address IPL P:$0000 3 Hardware RESET P:$0002 3 Stack Error P:$0004 3 Trace P:$0006 3 SWI P:$0008 0-2 IRQA P:$000A 0-2 IRQB P:$000C 0-2 SSI Receive Data P:$000E 0-2 SSI Receive Data With Exception Status P:$0010 0-2 SSI Transmit Data P:$0012 0-2 SSI Transmit Data with Exception Status P:$0014 0-2 SCI Receive Data P:$0016 0-2 SCI Receive Data with Exception Status P:$0018 0-2 SCI Transmit Data P:$001A 0-2 SCI Idle Line P:$001C 0-2 SCI Timer P:$001E 3 P:$0020 0-2 Host Receive Data P:$0022 0-2 Host Transmit Data P:$0024 0-2 Host Command (Default) P:$0026 0-2 Available for Host Command P:$003A 0-2 Available for Host Command P:$003C 0-2 Timer P:$003E 3 P:$0040 0-2 Available for Host Command P:$007E 0-2 Available for Host Command Interrupt Source NMI Illegal Instruction MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR Table 3-5 Exception Priorities Within an IPL Priority Exception Level 3 (Nonmaskable) Highest Hardware RESET Illegal Instruction NMI Freescale Semiconductor, Inc... Stack Error Trace Lowest SWI Levels 0, 1, 2 (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) Host Command Interrupt Host Receive Data Interrupt Host Transmit Data Interrupt SSI RX Data with Exception Interrupt SSI RX Data Interrupt SSI TX Data with Exception Interrupt SSI TX Data Interrupt SCI RX Data with Exception Interrupt SCI RX Data Interrupt SCI TX Data with Exception Interrupt SCI TX Data Interrupt SCI Idle Line Interrupt SCI Timer Interrupt Lowest MOTOROLA Timer Interrupt MEMORY MODULES AND OPERATING MODES For More Information On This Product, Go to: www.freescale.com 3 - 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 4 Freescale Semiconductor, Inc... PORT A MOTOROLA For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION CONTENTS 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 PORT A INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 PORT A TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4 PORT A WAIT STATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.5 BUS CONTROL REGISTER (BCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.6 BUS STROBE AND WAIT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.7 BUS ARBITRATION AND SHARED MEMORY. . . . . . . . . . . . . . . . . . . . . . 4-16 4-2 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION 4.1 INTRODUCTION Port A provides a versatile interface to external memory, allowing economical connection with fast memories/devices, slow memories/devices, and multiple bus master systems. Freescale Semiconductor, Inc... Port A has two power-reduction features. It can access internal memory spaces, toggling only the external memory signals that need to change, thereby eliminating unneeded switching current. Also, if conditions allow the processor to operate at a lower memory speed, wait states can be added to the external memory access to significantly reduce power while the processor accesses those memories. 4.2 PORT A INTERFACE The DSP56002 processor can access one or more of its memory sources (X data memory, Y data memory, and program memory) while it executes an instruction. The memory sources may be either internal or external to the DSP. Three address buses (XAB, YAB, and PAB) and four data buses (XDB, YDB, PDB, and GDB) are available for internal memory accesses during one instruction cycle. Port A’s one address bus and one data bus are available for external memory accesses. If all memory sources are internal to the DSP, one or more of the three memory sources may be accessed in one instruction cycle (i.e., program memory access or program memory access plus an X, Y, XY, or L memory reference). However, when one or more of the memories are external to the chip, memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle. If an instruction cycle requires more than one external access, the processor will make the accesses in the following priority: X memory, Y memory, and program memory. It takes one instruction cycle for each external memory access – i.e., one access can be executed in one instruction cycle, two accesses take two instruction cycles, etc. Since the external data bus is only 24 bits wide, one XY or long external access will take two instruction cycles. The 16-bit address bus can sustain a rate of one memory access per instruction cycle (using no-wait-state memory which is discussed in 4.4 PORT A WAIT STATES). Figure 4-1 shows the port A signals divided into their three functional groups: address bus signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can be subdivided into three additional groups: read/write control (RD and WR), address space selection (including program memory select (PS), data memory select (DS), and X/Y select) and bus access control (BN, BR, BG, WT, BS). The read/write controls can act as decoded read and write controls, or, as seen in Figure 4-2, Figure 4-3, and Figure 4-4, the write signal can be used as the read/write control, and the read signal can be used as an output enable (or data enable) control for the memory. MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. PORT A INTERFACE 16 - BIT INTERNAL ADDRESS BUSES X ADDRESS (XA) 16 Y ADDRESS (YA) EXTERNAL ADDRESS BUS SWITCH EXTERNAL ADDRESS BUS A0 - A15 Freescale Semiconductor, Inc... PROGRAM ADDRESS (PA) 24 - BIT INTERNAL DATA BUSES X DATA (XD) 24 Y DATA (YD) EXTERNAL DATA BUS D0 - D23 EXTERNAL DATA BUS SWITCH PROGRAM DATA (PD) GLOBAL DATA (GD) BUS CONTROL SIGNALS EXTERNAL BUS CONTROL LOGIC RD –- READ ENABLE WR – WRITE ENABLE PS – PROGRAM MEMORY SELECT DS – DATA MEMORY SELECT X/Y – X MEMORY/Y MEMORY SELECT BN –- BUS NEEDED BR – BUS REQUEST BG – BUS GRANT WT – BUS WAIT BS – BUS STROBE Figure 4-1 Port A Signals Decoding in such a way simplifies connection to high-speed random-access memories 4-4 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PORT A INTERFACE VCC +5 V VSS GROUND 16 ADDRESS BUS A0 - A15 PROGRAM MEMORY ADDRESS 24 Freescale Semiconductor, Inc... DATA BUS D0 - D23 DATA DSP56002 BUS CONTROL RD OE WR R/W PS CS 24 BIT x N WORDS DS X/Y BN BR BG WT BS Figure 4-2 External Program Space (RAMs). The program memory select, data memory select, and X/Y select can be considered additional address signals, which extend the directly addressable memory from 64K words to 192K words total. Since external logic delay is large relative to RAM timing margins, timing becomes more difficult as faster DSPs are introduced. The separate read and write strobes used by the DSP56002 are mutually exclusive, with a guard time between them to avoid an instance where two data buffers are enabled simultaneously. Other methods using external logic gates to generate the RAM control inputs require either faster RAM chips or external data buffers to avoid data bus buffer conflicts. Figure 4-2 shows an example of external program memory. A typical implementation of this circuit would use three-byte-wide static memories and would not require any additional logic. The PS signal is used as the program-memory chip-select signal to enable the program memory at the appropriate time. Figure 4-3 shows a similar circuit using the DS signal to enable two data memories and MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4-5 Freescale Semiconductor, Inc. PORT A INTERFACE VCC +5 V VSS GROUND 16 ADDRESS BUS A0 - A15 24 Freescale Semiconductor, Inc... DATA BUS D0 - D23 DATA ADDRESS DATA X DATA MEMORY 24 BITS x N WORDS DSP56002 OE R/W CS ADDRESS Y DATA MEMORY 24 BITS x N WORDS CE OE R/W CS CE BUS CONTROL RD WR PS DS X/Y BN BR BG WT BS Figure 4-3 External X and Y Data Space using the X/Y signal to select between them. The three external memory spaces (program, X data, and Y data) do not have to reside in separate physical memories; a single memory can be employed by using the PS, DS, and X/Y signals as additional address lines to segment the memory into three spaces (see Figure 4-4). Table 4-1 shows how the PS, DS, and X/Y signals are decoded. If the DSP is in the development mode, an exception fetch to any interrupt vector location will cause the X/Y signal to go low when PS is asserted. This procedure is useful for debugging and for allowing external circuitry to track interrupt servicing. 4-6 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PORT A INTERFACE PS DS X/Y External Memory Reference 1 1 1 No Activity 1 0 1 X Data Memory on Data Bus 1 0 0 Y Data Memory on Data Bus 0 1 1 Program Memory on Data Bus (Not an Exception) 0 1 0 External Exception Fetch: Vector or Vector +1 (Development Mode Only) 0 0 X Reserved 1 1 0 Reserved Figure 4-5 shows a system that uses internal program memory loaded from an external VCC +5 V VSS GROUND EXTERNAL PROGRAM X AND Y MEMORY 16 A0-A10 $3FFF DSP56002 A15 A14 ADDRESS BUS A0 - A15 A13 Freescale Semiconductor, Inc... Table 4-1 Program and Data Memory Select Encoding CE U1 4K PROGRAM MEMORY 24 DATA BUS D0 - D23 BUS CONTROL OE R/W RD WR PS U2 $2FFF CS A12 2K X DATA MEMORY A11 $27FF DS X/Y $2800 A11 U3 BN BR $3000 U4 BG 2K Y DATA MEMORY WT $2000 BS 24 BITS Figure 4-4 Memory Segmentation MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4-7 4-8 For More Information On This Product, Go to: www.freescale.com PORT A FROM OPEN COLLECTOR BUFFER FROM RESET FUNCTION FROM OPEN COLLECTOR BUFFER MBD301* MBD301* MODB/IRQB RESET MODC/NMI X/Y RD WR DS D0-D23 A0-A10 PS DR DSP56002 BR HACK WT MODA/IRQA CE 11 8 10 24 D0-D23 2018-55 (3) A0-A9 A10 CS WE OE Notes: 1. *These diodes must be Schottky diodes. 2. All resistors are 15KΩ unless noted otherwise. 3. When in RESET, IRQA, IRQB and NMI must be deasserted by external peripherals. D0-D7 2716 A0-A10 Figure 4-5 Port A Bootstrap ROM with X and Y RAM MBD301* +5 V Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. PORT A INTERFACE ROM during power-up and splits the data memory space of a single memory bank into X: MOTOROLA Freescale Semiconductor, Inc. PORT A TIMING Freescale Semiconductor, Inc... and Y: memory spaces. Although external program memory must be 24 bits, external data memory does not. Of course, this is application specific. Many systems use 16 or fewer bits for A/D and D/A conversion and, therefore, they may only need to store 16, 12, or even eight bits of data. The 24/56 bits of internal precision is usually sufficient for intermediate results. This is a cost saving feature which can reduce the number of external memory chips. 4.3 PORT A TIMING The external bus timing is defined by the operation of the address bus, data bus, and bus control pins. The transfer of data over the external data bus is synchronous with the clock. The timing A, B, and C relative to the edges of an external clock (see Figure 4-6 and Figure 4-7) are provided in the DSP56002 Advance Information Data Sheet (DSP56002/D). This timing is essential for designing synchronous multiprocessor systems. Figure 4-6 shows the port A timing with no wait states (wait-state control is discussed in Section 4.4). One instruction cycle equals two clock cycles or four clock phases. The clock phases, which are numbered T0 – T3, are used for timing on the DSP. Figure 4-7 shows the same timing with two wait states added to the external X: memory access. Four TW clock phases have been added because one wait state adds two T phases and ONE INSTRUCTION CYCLE ONE CLOCK CYCLE T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 INTERNAL CLOCK PHASES ADDRESS PS, DS, X/Y A RD B READ CYCLE DATA IN WR WRITE CYCLE C DATA OUT Figure 4-6 Port A Bus Operation with No Wait States MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4-9 Freescale Semiconductor, Inc. PORT A TIMING ONE INSTRUCTION CYCLE TWO WAIT STATES ONE CLOCK CYCLE T0 INTERNAL CLOCK PHASES T1 T2 TW TW TW TW T3 T0 T1 ADDRESS PS, DS, X/Y Freescale Semiconductor, Inc... A RD B READ CYCLE DATA IN WRITE CYCLE WR C DATA OUT DATA LATCHED HERE Figure 4-7 Port A Bus Operation with Two Wait States is equivalent to repeating the T2 and T2 clock phases. The write signal is also delayed from the T1 to the T2 state when one or more wait states are added to ease interfacing to the port. Each external memory access requires the following procedure: 1. The external memory address is defined by the address bus (A0–A15) and the memory reference selects (PS, DS, and X/Y). These signals change in the first phase (T0) of the bus cycle. Since the memory reference select signals have the same timing as the address bus, they may be used as additional address lines. The address and memory reference signals are also used to generate chip-select signals for the appropriate memory chips. These chip-select signals change the memory chips from low-power standby mode to active mode and begin the read access time. This mode change allows slower memories to be used since the chip-select signals can be address based rather than read or write enable based. Read and write enable do not become active until after the address is valid. See the timing diagrams in the DSP56002 Advance Information Data Sheet (DSP56002/D) for detailed timing information. 2. When the address and memory reference signals are stable, the data transfer 4 - 10 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... PORT A TIMING is enabled by read enable (RD) or write enable (WR). RD or WR is asserted to “qualify” the address and memory reference signals as stable and to perform the read or write data transfer. RD and WR are asserted in the second phase of the bus cycle (if there are no wait states). Read enable is typically connected to the output enable (OE) of the memory chips and simply controls the output buffers of the chip-selected memory. Write enable is connected to the write enable (WE) or write strobe (WS) of the memory chips and is the pulse that strobes data into the selected memory. For a read operation, RD is asserted and WR remains deasserted. Since write enable remains negated, a memory read operation is performed. The DSP data bus becomes an input, and the memory data bus becomes an output. For a write operation, WR is asserted and RD remains deasserted. Since read enable remains deasserted, the memory chip outputs remain in the high-impedance state even before write strobe is asserted. This state assures that the DSP and the chip-selected memory chips are not enabled onto the bus at the same time. The DSP data bus becomes an output, and the memory data bus becomes an input. 3. Wait states are inserted into the bus cycle by a wait-state counter or by asserting WT. The wait-state counter is loaded from the bus control register. If the value loaded into the wait-state counter is zero, no wait states are inserted into the bus cycle, and RD and WR are asserted as shown in Figure 4-6. If a value W≠0 is loaded into the wait state counter, W wait states are inserted into the bus cycle. When wait states are inserted into an external write cycle, WR is delayed from T1 to T2. The timing for the case of two wait states (W=2) is shown in Figure 4-7. 4. When RD or WR are deasserted at the start of T3 in a bus cycle, the data is latched in the destination device – i.e., when RD is deasserted, the DSP latches the data internally; when WR is deasserted, the external memory latches the data on the positive-going edge. The address signals remain stable until the first phase of the next external bus cycle to minimize power dissipation. The memory reference signals (PS, DS, and X/Y) are deasserted (held high) during periods of no bus activity, and the data signals are three-stated. For read-modify-write instructions such as BSET, the address and memory reference signals remain active for the complete composite (i.e., two Icyc) instruction cycle. MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 11 Freescale Semiconductor, Inc. PORT A TIMING PORT A BUS CONTROL REGISTER (BCR) EXTERNAL X MEMORY 15 X:$FFFE EXTERNAL Y MEMORY 12 11 0100 EXTERNAL P MEMORY 8 7 EXTERNAL I/0 MEMORY 4 1000 3 0 1010 1101 D/A CONVERTER CS WR D CS RD 350 ns (13 WAIT STATES) A15 A0 - A15 A15 D0 - D23 INTERNAL MEMORY (0 WAIT STATES) Freescale Semiconductor, Inc... D A/D CONVERTER 40 MHz DSP56002 6242 - 15 6242 - 15 2764 - 25 27256 - 30 2764 - 25 27256 - 30 6242 - 15 2764 - 25 27256 - 30 8K x 24 X RAM 150 ns 8K x 24 Y ROM 250 ns 32K x 24 P ROM 300 ns (4 WAIT STATES) (8 WAIT STATES) (10 WAIT STATES) CS CS WE OE CS OE CE OE X/Y DS WR RD PS Figure 4-8 Mixed-Speed Expanded System 4 - 12 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PORT A WAIT STATES Freescale Semiconductor, Inc... Figure 4-8 shows an example of mixing different memory speeds and memory-mapped peripherals in different address spaces. The internal memory uses no wait states, X: memory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states, and the analog converters use 14 wait states. Controlling five different devices at five different speeds requires only one additional logic package. Half the gates in that package are used to map the analog converters to the top 64 memory locations in Y: memory. 4.4 PORT A WAIT STATES The DSP56002 features two methods to allow the user to accommodate slow memory by changing the port A bus timing. The first method uses the bus control register (BCR), which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces: X, Y, P, and I/O. The second method uses the bus strobe (BS) and bus wait (WT) facility, which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or I/O space. Wait states are executed until the external device releases the DSP to finish the external memory cycle. Table 4-2 Wait State Control BCR Contents WT 0 Deasserted 0 Asserted >0 Deasserted >0 Asserted Number of Wait States Generated 0 2 (minimum) Equals value in BCR Minimum equals 2 or value in BCR. Maximum is determined by BCR or WT, whichever is larger. 4.5 BUS CONTROL REGISTER (BCR) The BCR determines the expansion bus timing by controlling the timing of the bus interface signals, RD and WR, and the data output lines. It is a memory mapped register located at X:$FFFE. Each of the memory spaces in Figure 4-9 (X data, Y data, program data, and I/O) has its own 4-bit BCR, which can be programmed for inserting up to 15 wait states (each wait state adds one-half instruction cycle to each memory access – i.e., 50 ns for a 20-Mhz clock). In this way, external bus timing can be tailored to match the speed requirements of the different memory spaces. On processor reset, the BCR is preset to all ones (15 wait states). This allows slow memory to be used for boot strapping. The BCR needs to be set appropriately for the memory being used or the processor will insert 15 wait states between each memory fetch and cause the DSP to run slow. MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 13 Freescale Semiconductor, Inc. BUS CONTROL REGISTER (BCR) 15 X:$FFFE 12 EXTERNAL X MEMORY * 11 8 EXTERNAL Y MEMORY * 4 EXTERNAL P MEMORY * $FFFF $FFFF $FFFE Freescale Semiconductor, Inc... 7 $FFFF BUS CONTROL REGISTER EXTERNAL PERIPHERALS $FFC0 $FFC0 EXTERNAL X DATA MEMORY $200 $200 INTERNAL PROGRAM RAM $100 EXTERNAL Y DATA MEMORY $200 INTERNAL X ROM $100 INTERNAL X RAM 0 0 PROGRAM MEMORY SPACE 0 EXTERNAL I/0 MEMORY * ON-CHIP PERIPHERALS EXTERNAL PROGRAM MEMORY 3 INTERNAL Y ROM INTERNAL Y RAM 0 X DATA MEMORY SPACE Y DATA MEMORY SPACE * Zero to 15 wait states can be inserted into each external memory access. Figure 4-9 Bus Control Register Figure 4-9 illustrates which of the four BCR subregisters affect which external memory space. All the internal peripheral devices are memory mapped, and their control registers reside between X:$FFC0 and X:$FFFF. To load the BCR the way it is shown in Figure 4-8, execute a “MOVEP #$48AD, X:$FFFE” instruction. Or, change the individual bits in one of the four subregisters by using the BSET and BCLR instructions which are detailed in the DSP56000 Family Manual, SECTION 6 and APPENDIX A. Figure 4-8 shows an example of mixing different memory speeds and memory-mapped peripherals in different address spaces. The internal memory uses no wait states, X: memory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states, and the analog converters use 14 wait states. Controlling five different devices at five different speeds requires only one additional logic package. Half the gates in that package are used to map the analog converters to the top 64 memory locations in Y: memory. 4 - 14 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. BUS STROBE AND WAIT PINS OPERATING MODE REGISTER 7 6 5 4 3 2 1 0 EM SD 0 0 0 DE MB MA SET EM = 1 VCC VSS +5 V GROUND T0 Freescale Semiconductor, Inc... DSP56000/DSP56001 T1 T2 TW TW TW TW T3 T0 16 ADDRESS BUS A0 - A15 A0 - A15, D0 - D23, PS, DS, X/Y 24 DATA BUS D0 - D23 BUS CONTROL WT IS SAMPLED WT IS SAMPLED WT IS SAMPLED RD WR PS DS X/Y WT T3 BS Figure 4-10 Bus Strobe/Wait Sequence Adding wait states to external memory accesses can substantially reduce power requirements. Consult the DSP56002 Technical Data Sheet (DSP56002/D) for specific power consumption requirements. 4.6 BUS STROBE AND WAIT PINS The ability to insert wait states using BS and WT provides a means to connect asynchronous devices to the DSP, allows devices with differing timing requirements to reside in the same memory space, allows a bus arbiter to provide a fast multiprocessor bus access, and provides another means of halting the DSP at a known program location with a fast restart. The timing of the BS and WT pins is illustrated in Figure 4-10. Every external access, BS is asserted concurrently with the address lines in T0. BS can be used by external wait- MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 15 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... BUS ARBITRATION AND SHARED MEMORY state logic to establish the start of an external access. BS is deasserted in T3 of each external bus cycle, signaling that the current bus cycle will complete. Since the WT signal is internally synchronized, it can be asserted asynchronously with respect to the system clock. The WT signal should only be asserted while BS is asserted. Asserting WT while BS is deasserted will give indeterminate results. However, for the number of inserted wait states to be deterministic, WT timing must satisfy setup and hold timing with respect to the negative-going edge of EXTAL. The setup and hold times are provided in the DSP56002 Advance Information Data Sheet (DSP56002/D). The timing of WR is controlled by the BCR and is independent of WT. The minimum number of wait states that can be inserted using the WT pin is two. The BCR is still operative when using BS and WT and defines the minimum number of wait states that are inserted. Table 4-2 summarizes the effect of the BCR and WT pin on the number of wait states generated. 4.7 BUS ARBITRATION AND SHARED MEMORY The DSP56002 has five pins that control port A. They are bus needed (BN), bus request (BR), bus grant (BG), bus strobe (BS) and bus wait (WT) and they are described in SECTION 2 DSP56002 PIN DESCRIPTIONS. The bus control signals provide the means to connect additional bus masters (which may be additional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) to the port A bus. They work together to arbitrate and determine what device gets access to the bus. If an external device has requested the external bus by asserting the BR input, and the DSP has granted the bus by asserting BG, the DSP will continue to process as long as it requires no external bus accesses itself. If the DSP does require an external access but is not the bus master, it will stop processing and remain in wait states until it regains bus ownership. The BN pin will have been asserted, and an external device may use BN to help “arbitrate”, or decide when to return bus ownership to the chip. Four examples of bus arbitration will be described later in this section: 1) bus arbitration using only BR and BG with internal control, 2) bus arbitration using BN, BR, and BG with external control, 3) bus arbitration using BR, BG and WT, BS with no overhead, and 4) signaling using semaphores. The BR input allows an external device to request and be given control of the external bus while the DSP continues internal operations using internal memory spaces. This allows a bus controller to arbitrate a multiple bus-master system. (A bus master can issue addresses on the bus; a bus slave can respond to addresses on the bus. A single device can be both a master and a slave, but can only be one or the other at any given time.) 4 - 16 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY BR BG A0 - A15, D0 - D23, PS, DS, X/Y, RD, WR A DIFFERENT BUS MASTER Freescale Semiconductor, Inc... DSP56002 BUS MASTER DSP56002 BUS MASTER Figure 4-11 Bus Request/Bus Grant Sequence Before BR is asserted, all port A signals are driven. When BR is asserted (see Figure 4-11), the DSP will assert BG after the current external access cycle completes and will simultaneously three-state (high-impedance) the port A signals (see the DSP56002 Technical Data Sheet (DSP56002/D) for exact timing of BR and BG). The bus is then available to whatever external device has bus mastership. The external device will return bus mastership to the DSP by deasserting BR. After the DSP completes the current cycle (an internally executed instruction with or without wait states), BG will be deasserted. When BG is deasserted, the A0-A15, PS, DS, X/Y, and RD, WR lines will be driven. However, the data lines will remain in three-state. All signals are now ready for a normal external access. During the wait state (see Section 7 in the DSP56000 Family Manual), the BR and BG circuits remain active. However, the port is inactive - the control signals are deasserted, the data signals are inputs, and the address signals remain as the last address read or written. When BR is asserted, all signals are three-stated (high impedance). Table 4-3 shows the status of BR and BG during the wait state. Table 4-3 BR and BG During WAIT Signal MOTOROLA Before BR Asserted While BG Asserted After BR Deasserted PORT A After Return to Normal State (BG Deasserted) For More Information On This Product, Go to: www.freescale.com After First External Access 4 - 17 Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY Freescale Semiconductor, Inc... 4.7.1 Bus Arbitration Using Only BR and BG With Internal Control Perhaps the simplest example of a shared memory system using a DSP56002 is shown in Figure 4-12. The bus arbitration is performed within the DSP#2 by using software. DSP#2 controls all bus operations by using I/O pin OUT2 to three-state its own port A and by never accessing port A without first calling the subroutine that arbitrates the bus. When the DSP#2 needs to use external memory, it uses I/O pin OUT1 to request bus access and I/O pin IN1 to read bus grant. DSP#1 does not need any extra code for bus arbitration since the BR and BG hardware handles its bus arbitration automatically. The protocol for bus arbitration is as follows: At reset: DSP#2 sets OUT2=0 (BR#2=0) and OUT1=1 (BR#1=1), which gives DSP#1 access to the bus and suspends DSP#2 bus access. When DSP#2 wants control of the memory, the following steps are performed (see Figure 4-13): 1. DSP# 2 sets OUT1=0 (BR#1=0). 2. DSP# 2 waits for IN1=0 (BG#1=0 and DSP#1 off the bus). 3. DSP#2 sets OUT2=1 (BR#2=1 to let DSP#2 control the bus). 4. DSP#2 accesses the bus for block transfers, etc. at full speed. 5. To release the bus, DSP#2 sets OUT2=0 (BR#2=0) after the last external access. 6. DSP#2 then sets OUT1=1 (BR#1=1) to return control of the bus to DSP#1. 7. DSP#1 then acknowledges mastership by deasserting BG#1. 4.7.2 Bus Arbitration Using BN, BR, and BG With External Control Figure 4-14 can be implemented with external bus arbitration logic, which will save processing capacity on the DSPs and can make bus access much faster at a cost of additional hardware. The bus arbitration logic takes control of the external bus by deasserting an enable signal (E1, E2, and E3) to all DSPs, which will then acknowledge by granting the bus (BG=0). When a DSP (DSP#1 in Figure 4-14) needs the bus, it will enter the WAIT state with BN asserted. If DSP#1 has highest priority, the arbitration logic grants the bus to DSP#1 by asserting E1 (E2 for DSP#2; E3 for DSP#3) to let the DSP know that it can have the bus. DSP#1 will then deassert BG to tell the arbiter it has taken control of the bus. When the DSP no longer needs to make an external access it will deassert BN and the arbiter deasserts E1, after which the DSP deasserts BG. 4 - 18 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY BR OUT2 BR OUT1 BG IN1 Freescale Semiconductor, Inc... CONTROL CONTROL A0 - A15 A0 - A15 D0 - D23 D0 - D23 DSP56002 #1 DSP56002 #2 BUS ARBITER C A D MEMORY BANK Figure 4-12 Bus Arbitration Using Only BR and BG with Internal Control OUT1 IN1 OUT2 DATA TRANSFERRED HERE 1 2 3 4 5 6 7 Figure 4-13 Two DSPs with External Bus Arbitration Timing MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 19 Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY SYSTEM MEMORY 32K x 24 X DATA RAM 32K x 24 Y DATA RAM 32K x 24 PROGRAM RAM Freescale Semiconductor, Inc... ADDRESS DATA CONTROL ADDRESS 16 DATA 24 CONTROL A D C 5 A D C A D C DSP56002 #1 DSP56002 #2 DSP56002 #3 BG BR BN BG BR BN BG BR BN A1 E1 BR1 A2 E2 BR2 A3 E3 BR3 BUS ARBITRATION LOGIC WITH PRIORITY ENCODER Figure 4-14 Bus Arbitration Using BN, BR, and BG with External Control 4.7.3 Bus Arbitration Using BR and BG, and WT and BS With No Overhead By using the circuit shown in Figure 4-15, two DSPs can share memory with hardware arbitration that requires no software on the part of the DSPs. The protocol for bus arbitration in Figure 4-15 is as follows: At RESET assume DSP#1 is not making external accesses so that BR#2 is deasserted. Hence, BG of DSP#2 is deasserted, which three-states the buffers, giving DSP#2 control of the memory. 4 - 20 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY MEMORY D Freescale Semiconductor, Inc... DSP #1 A C THREE-STATE BUFFER DSP #2 D0 - D23 D0 - 23 A0 - A15 A0 - A15 RD, WR, RD, WR, DS, PS, X/Y DS, PS, X/Y DIR BS WT ENABLE BG BR Figure 4-15 Bus Arbitration Using BR and BG, and WT and BS with No Overhead When DSP#1 wants control of the memory the following steps are performed (see Figure 4-16): 1. DSP#1 makes an external access, thereby asserting BS, which asserts WT (causing DSP#1 to execute wait states in the current cycle) and asserts DSP#2 BR (requesting that DSP#2 release the bus). 2. When DSP#2 finishes its present bus cycle, it three-states its bus drivers and asserts BG. Asserting BG enables the three-state buffers, placing the DSP#1 signals on the memory bus. Asserting BG also deasserts WT, which allows DSP#1 to finish its bus cycle. 3. When DSP#1’s memory cycle is complete, it releases BS, which deasserts BR. DSP#2 then deasserts BG, three-stating the buffers and allowing DSP#2 to access the memory bus. MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 21 Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY BS WT BR Freescale Semiconductor, Inc... BG 1 2 DATA TRANSFERRED BETWEEN DSP#1 AND MEMORY HERE 3 Figure 4-16 Two DSPs with External Bus Arbitration Timing 4.7.4 Signaling Using Semaphores Figure 4-17 shows a more sophisticated shared memory system that uses external arbitration with both local external memory and shared memory. The four semaphores are bits in one of the words in each shared memory bank used by software to arbitrate memory use. Semaphores are commonly used to indicate that the contents of the semaphore’s memory blocks are being used by one processor and are not available for use by another processor. Typically, if the semaphore is cleared, the block is not allocated to a processor; if the semaphore is set, the block is allocated to a processor. Without semaphores, one processor may try to use data while it is being changed by another processor, which may cause errors. This problem can occur in a shared memory system when separate test and set instructions are used to “lock” a data block for use by a single processor. The correct procedure is to test the semaphore and then set the semaphore if it was clear to lock and gain exclusive use of the data block. The problem occurs when the second processor acquires the bus and tests the semaphore after the first processor tests the semaphore but before the first processor can lock the data block. The incorrect sequence is: 1. the first processor tests the semaphore and sees that the block is available 2. the second processor then tests the bit and also sees that the block is available 3. both processors then set the bit to lock the data 4. both proceed to use the data on the assumption that the data cannot be changed by another processor 4 - 22 PORT A For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. BUS ARBITRATION AND SHARED MEMORY 1 SEMAPHORE 3 BANK 3 0 SEMAPHORE 2 BANK 2 0 SEMAPHORE 1 BANK 1 Freescale Semiconductor, Inc... 1 SEMAPHORE 0 BANK 0 DSP56002 LOCAL MEMORY PROCESSOR LOCAL MEMORY DSP56002 ADDRESS DATA AND CONTROL BUSES BUS BUFFER BUS BUFFER PROCESSOR OR DMA ADDRESS DATA AND CONTROL BUSES ARBITRATION LOGIC Figure 4-17 Signaling Using Semaphores The DSP56K processor series has a group of instructions designed to prevent this problem. They perform an indivisible read-modify-write operation and do not release the bus between the read and write (specifically, A0–A15, DS, PS, and X/Y do not change state). Using a read-modify-write operation allows these instructions to test the semaphore and then to set, clear, or change the semaphore without the possibility of another processor testing the semaphore before it is changed. The instructions are bit test and change (BCHG), bit test and clear (BCLR), and bit test and set (BSET). (They are discussed in detail in the DSP56000 Family Manual.) The proper way to set the semaphore to gain exclusive access to a memory block is to use BSET to test the semaphore and to set it to one. After the bit is set, the result of the test operation will reveal if the semaphore was clear before it was set by BSET and if the memory block is available. If the bit was already set and the block is in use by another processor, the DSP must wait to access the memory block. MOTOROLA PORT A For More Information On This Product, Go to: www.freescale.com 4 - 23 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 5 Freescale Semiconductor, Inc... PORT B MOTOROLA For More Information On This Product, Go to: www.freescale.com 5-1 Freescale Semiconductor, Inc. SECTION CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 GENERAL PURPOSE I/O CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3 HOST INTERFACE (HI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Freescale Semiconductor, Inc... 5.1 5-2 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION Freescale Semiconductor, Inc... 5.1 INTRODUCTION Port B is a dual-purpose I/O port. It performs as 15 general-purpose I/O (GPIO) pins, each configurable as output or input, to be used for device control. Or, it can perform as an 8-bit bidirectional host interface (HI) (see Figure 5-1), where it provides a convenient connection to another processor. This section describes both configurations, including examples of how to configure and use the port. DEFAULT FUNCTION ALTERNATE FUNCTION 16 EXTERNAL ADDRESS SWITCH A0 - A15 — D0 - D23 — 24 EXTERNAL DATA SWITCH PS DS X/Y RD WR BN BR BG WT BS PORT A I/0 (47) BUS CONTROL 8 HOST/DMA PARALLEL INTERFACE PORT B I/0 (15) SCI INTERFACE PORT C I/0 (9) SSI INTERFACE — — — — — — — — — — 8 PB0 - PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 H0 - H7 HA0 HA1 HA2 HR/W HEN HREQ HACK or PB14 PC0 RXD PC1 TXD PC2 SCLK PC3 SC0 PC4 SC1 PC5 SC2 PC6 SCK PC7 SRD PC8 STD Figure 5-1 Port B Interface MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5-3 Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION 5.2 GENERAL PURPOSE I/O CONFIGURATION When it is configured as general-purpose I/O, Port B acts as three memory-mapped registers (see Figure 5-2) that control 15 I/O pins (see Figure 5-3). They are the Port B control register (PBC), Port B data direction register (PBDDR), and Port B data register (PBD). Freescale Semiconductor, Inc... The software and hardware resets clear the PBC and PBDDR, which configures Port B as general-purpose I/O, with all 15 pins as inputs. (External circuitry connected to these pins may need pullups until the pins are configured for operation.) To select between general purpose I/O and the HI, set PBC bits 0 and 1 as shown in Figure 5-2. Use the PBDDR to determine whether the corresponding bit in the PBD shall be an input pin (bit is set to zero) or an output pin (bit is set to one). If a pin is configured as a GPIO input (as shown in Figure 5-4) and the processor reads the PBD, the processor sees the logic level on the pin. If the processor writes to the PBD, the data is latched there, but does not appear on the pin because the buffer is in the highimpedance state. 23 X:$FFE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC1 BC0 0 0 Parallel I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK pin as GPIO) 1 1 Reserved 0 0 Function 23 X:$FFE2 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Direction 0 Input (Reset Condition) 1 Output 23 0 PORT B DATA DIRECTION REGISTER (PBDDR) 0 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 0 BDx X:$FFE4 PORT B CONTROL REGISTER (PBC) BC BC 1 0 0 0 0 0 0 0 0 0 0 PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORT B DATA REGISTER (PBD) Figure 5-2 Parallel Port B Registers 5-4 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION ENABLED BY BITS IN X:$FFE0 P O R T Freescale Semiconductor, Inc... B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 DIRECTION SELECTED BY X:$FFE2 INPUT/OUTPUT DATA X:$FFE4 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 Figure 5-3 Parallel Port B Pinout If a pin is configured as a GPIO output and the processor reads the PBD, the processor sees the contents of the PBD rather the logic level on the pin, which allows the PBD to be used as a general purpose 15-bit register. If the processor writes to the PBD, the data is latched there and appears on the pin during the following instruction cycle (see Section 5.2.2 Port B General Purpose I/O Timing). If a pin is configured as a host pin, the Port B GPIO registers can be used to help in debugging the HI. If the PBDDR bit for a given pin is cleared (configured as an input), the PBD will show the logic level on the pin, regardless of whether the HI function is using the pin as an input or an output. If the PBDDR is set (configured as an output) for a given pin that is configured as a host pin, when the processor reads the PBD, it sees the contents of the PBD rather than the logic level on the pin - another case which allows the PBD to act as a general purpose register. Note: The external host processor should be carefully synchronized to the DSP56002 to assure that the DSP and the external host will properly read status bits transmitted between them. There is more discussion of such port usage considerations in sections Section 5.3.2.7 Host Port Usage Considerations – DSP Side and Section 5.3.6.5 Host Port Usage Considerations – Host Side. 5.2.1 Programming General Purpose I/O Port B is a memory-mapped peripheral as are all of the DSP56002 peripherals (see Figure 5-5). The standard MOVE instruction transfers data between Port B and a register; as a result, MOVE takes two instructions to perform a memory-to-memory data MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5-5 Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION Port Control Register Bit Data Direction Register Bit 0 0 Pin Function Port Input Pin PIN Freescale Semiconductor, Inc... PORT B DATA (PBD) REGISTER BIT (GPIO POSITION) PORT REGISTERS DATA DIRECTION REGISTER (PBDDR) BIT PORT B CONTROL REGISTER (PBC) BIT (INPUT POSITION) PORT INPUT DATA BIT HI OUTPUT DATA BIT PERIPHERAL LOGIC HI DATA DIRECTION BIT HI INPUT DATA BIT Figure 5-4 Port B I/O Pin Control Logic transfer and uses a temporary holding register. The MOVEP instruction is specifically designed for I/O data transfer as shown in Figure 5-6. Although the MOVEP instruction may take twice as long to execute as a MOVE instruction, only one MOVEP is required for a memory-to-memory data transfer, and MOVEP does not use a temporary register. Using the MOVEP instruction allows a fast interrupt to move data to/from a peripheral to memory and execute one other instruction or move the data to an absolute address. MOVEP is the only memory-to-memory move instruction; however, one of the operands must be in the top 64 locations of either X: or Y: memory. The bit-oriented instructions that use I/O short addressing (BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, and JSSET) can also be used to address individual bits for faster I/O processing. The digital signal processor (DSP) does not have a hardware data strobe to strobe data out of the GPIO port. If a strobe is needed, it can be implemented using software to toggle one of the GPIO pins. 5-6 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION Freescale Semiconductor, Inc... 23 16 15 8 7 0 X:$FFFF INTERRUPT PRIORITY REGISTER (IPR) X:$FFFE PORT A — BUS CONTROL REGISTER (BCR) X:$FFFD PLL CONTROL REGISTER X:$FFFC OnCE GDB REGISTER X:$FFFB RESERVED X:$FFFA RESERVED X:$FFF9 RESERVED X:$FFF8 RESERVED X:$FFF7 RESERVED X:$FFF6 SCI HI - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF5 SCI MID - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF4 SCI LOW - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF3 SCI TRANSMIT DATA ADDRESS REGISTER (STXA) X:$FFF2 SCI CONTROL REGISTER (SCCR) X:$FFF1 SCI INTERFACE STATUS REGISTER (SSR) X:$FFF0 SCI INTERFACE CONTROL REGISTER (SCR) X:$FFEF SSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX) X:$FFEE SSI STATUS/TIME SLOT REGISTER (SSISR/TSR) X:$FFED SSI CONTROL REGISTER B (CRB) X:$FFEC SSI CONTROL REGISTER A (CRA) X:$FFEB HOST RECEIVE/TRANSMIT REGISTER (HRX/HTX) X:$FFEA RESERVED X:$FFE9 HOST STATUS REGISTER (HSR) X:$FFE8 HOST CONTROL REGISTER (HCR) X:$FFE7 RESERVED X:$FFE6 RESERVED X:$FFE5 PORT C — DATA REGISTER (PCD) X:$FFE4 PORT B — DATA REGISTER (PBD) X:$FFE3 PORT C — DATA DIRECTION REGISTER (PCDDR) X:$FFE2 PORT B — DATA DIRECTION REGISTER (PBDDR) X:$FFE1 PORT C — CONTROL REGISTER (PCC) X:$FFE0 PORT B — CONTROL REGISTER (PBC) X:$FFDF TIMER COUNT REGISTER (TCR) X:$FFDE TIMER CONTROL/STATUS REGISTER (TCSR) X:$FFC0 RESERVED = Read as random number; write as don’t care. Figure 5-5 On-Chip Peripheral Memory Map MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5-7 Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION • MOVE #$0,X:$FFE0 ;Select Port B to be general-purpose I/O MOVE #$7F00,X:$FFE2 ;Select pins PB0–PB7 to be inputs ;and pins PB8–PB14 to be outputs • • MOVEP #data_out,X:$FFE4 Freescale Semiconductor, Inc... MOVEP X:$FFE4,#data_in ;Put bits 8–14 of “data_out” on pins ;PB8–PB14 bits 0–7 are ignored ;Put PB0–PB7 in bits 0–7 of “data_in” Figure 5-6 Instructions to Write/Read Parallel Data with Port B Figure 5-7 details the process of programming Port B as GPIO. Normally, it is not good programming practice to activate a peripheral before programming it. However, reset activates the Port B general-purpose I/O as all inputs; the alternative is to configure Port B as an HI, which may not be desirable. In this case, it is probably better to insure that Port B is initially configured for general-purpose I/O, and then configure the data direction and data registers. It may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal. The order of steps 1, 2, and 3 in Figure 5-7 is optional and can be changed as needed. 5.2.2 Port B General Purpose I/O Timing General purpose data written to Port B is synchronized to the central processing unit (CPU) but delayed by one instruction cycle. For example, the instruction MOVE DATA15,X:PORTB DATA24,Y:EXTERN 1. writes 15 bits of data to the Port B register, but the output pins do not change until the following instruction cycle 2. writes 24 bits of data to the external Y memory, which appears on Port A during T2 and T3 of the current instruction As a result, if it is desirable to synchronize Port A and Port B outputs, two instructions must be used: MOVE NOP DATA15,X:PORTB DATA24,Y:EXTERN The NOP can be replaced by any instruction that allows parallel moves. Inserting one or more “MOVE DATA15,X:PORTB DATA24,Y:EXTERN” instructions between the first and 5-8 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL PURPOSE I/O CONFIGURATION second instruction effectively produces an external 39-bit write each instruction cycle with only one instruction cycle lost in setup time: Freescale Semiconductor, Inc... MOVE MOVE MOVE : : MOVE NOP DATA15,X:PORTB DATA15,X:PORTB DATA15,X:PORTB DATA15,X:PORTB DATA24,Y:EXTERN DATA24,Y:EXTERN DATA24,Y:EXTERN DATA24,Y:EXTERN One application of this technique is to create an extended address for Port A by concatenating the Port A address bits (instead of data bits) to the Port B general-purpose output bits. The Port B general-purpose I/O register would then work as a base address register, allowing the address space to be extended from 64K words (16 bits) to two billion words (16 bits +15 bits = 31 bits). STEP 1. ACITIVATE PORT B FOR GENERAL - PURPOSE I/O: SET BITS 0 AND 1 TO ZERO 15 X:$FFE0 0 * * * * * * * * * * * * * * BC BC PORT B 1 0 CONTROL REGISTER (PBC) STEP 2. SET INDIVIDUAL PINS TO INPUT OR OUTPUT: BDxx = 0 INPUT OR BDxx = 1 OUTPUT 15 X:$FFE2 * 0 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD PORT B DATA DIRECTION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER (PBDDR) STEP 3. WRITE OR READ DATA: PBxx INPUT IF BDxx = 0 OR PBxx OUTPUT IF BDxx = 1 15 X:$FFE4 * 0 PB 14 PB PB PB PB PB PB PB PB PB PB PB PB PB PB PORT B DATA 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER (PBD) *Reserved; write as zero. Figure 5-7 I/O Port B Configuration MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5-9 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... Port B uses the DSP CPU four-phase clock for its operation. Therefore, if wait states are inserted in the DSP CPU timing, they also affect Port B timing. The result is that ports A and B in the previous synchronization example will always stay synchronized, regardless of how many wait states are used. 5.3 HOST INTERFACE (HI) The HI is a byte-wide, full-duplex, double-buffered, parallel port which may be connected directly to the data bus of a host processor. The host processor may be any of a number of industry standard microcomputers or microprocessors, another DSP, or DMA hardware because this interface looks like static memory. The HI is asynchronous and consists of two banks of registers – one bank accessible to the host processor and a second bank accessible to the DSP CPU (see Figure 5-8). A brief description of the HI features is presented in the following listing: Speed 3.3 Million Word/Sec Interrupt Driven Data Transfer Rate (This is the maximum interrupt rate for the DSP56002 running at 40 MHz – i.e., one interrupt every six instruction cycles.) Signals (15 Pins) H0–H7 Host Data Bus HA0-HA2 Host Address Select HR/W Host Read/Write Control Host Transfer Enable HEN Host Request HREQ Host Acknowledge HACK Interface – DSP CPU Side Mapping: Three X: Memory Locations Data Word: 24 Bits Transfer Modes: DSP to Host Host to DSP Host Command Handshaking Protocols: Software Polled Interrupt Driven (Fast or Long Interrupts) Direct Memory Access Instructions: Memory-mapped registers allow the standard MOVE instruction to be used Special MOVEP instruction provides for I/O service capability using fast interrupts Bit addressing instructions (BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines I/O short addressing provides faster execution with fewer instruction words 5 - 10 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Interface – Host Side Mapping: Eight Consecutive Memory Locations Memory-Mapped Peripheral for Microprocessors, DMA Controllers, etc. Freescale Semiconductor, Inc... Data Word: Eight Bits Transfer Modes: DSP to Host Host to DSP Host Command Mixed 8-, 16-, and 24-Bit Data Transfers Handshaking Protocols: Software Polled Interrupt Driven and Compatible with MC68000 Cycle Stealing DMA with Initialization Dedicated Interrupts: Separate Interrupt Vectors for Each Interrupt Source Special host commands force DSP CPU interrupts under host processor control, which are useful for: Real-Time Production Diagnostics Debugging Window for Program Development Host Control Protocols and DMA Setup Figure 5-8 is a block diagram showing the registers in the HI. These registers can be divided vertically down the middle into registers visible to the host processor on the left and registers visible to the DSP on the right. They can also be divided horizontally into control at the top, DSP-to-host data transfer in the middle (HTX, RXH, RXM, and RXL), and host-to-DSP data transfer at the bottom (THX, TXM, TXL, and HRX). 5.3.1 Host Interface – DSP CPU Viewpoint The DSP CPU views the HI as a memory-mapped peripheral occupying three 24-bit words in data memory space. The DSP may use the HI as a normal memory-mapped peripheral, using either standard polled or interrupt programming techniques. Separate transmit and receive data registers are double buffered to allow the DSP and host processor to efficiently transfer data at high speed. Memory mapping allows DSP CPU communication with the HI registers to be accomplished using standard instructions and addressing modes. In addition, the MOVEP instruction allows HI-to-memory and memoryto-HI data transfers without going through an intermediate register. Both hardware and software reset disable the HI and change Port B to general-purpose I/O with all pins designated as inputs. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 11 Freescale Semiconductor, Inc. HOST INTERFACE (HI) X:$FFE8 INTERRUPT CONTROL REGISTER (READ/WRITE) $0 ICR DSP CPU GLOBAL DATA BUS HCR HOST CONTROL REGISTER (READ/WRITE) X:$FFE9 Freescale Semiconductor, Inc... $1 CVR $2 ISR COMMAND VECTOR REGISTER (READ/WRITE) HSR INTERRUPT STATUS REGISTER (READ ONLY) CONTROL HOST STATUS REGISTER (READ ONLY) LOGIC HOST MPU DATA BUS H0 - H7 $3 IVR INTERRUPT VECTOR REGISTER (READ/WRITE) $5 RXH RECEIVE BYTE REGISTERS (READ ONLY) 8 $6 RXM X:$FFEB 24 HTX HOST TRANSMIT DATA REGISTER (WRITE ONLY) $7 RXL X:$FFEB $5 TXH $6 TXM 24 TRANSMIT BYTE REGISTERS (WRITE ONLY) 24 HRX HOST RECIEVE DATA REGISTER (READ ONLY) $7 TXL Figure 5-8 HI Block Diagram 5.3.2 Programming Model – DSP CPU Viewpoint The HI has two programming models: one for the DSP programmer and one for the host processor programmer. In most cases, the notation used reflects the DSP perspective. The HI – DSP programming model is shown in Figure 5-9. There are three registers: a control register (HCR), a status register (HSR), and a data transmit/receive register (HTX/HRX). These registers can only be accessed by the DSP56002; they can not be accessed by the host processor. The HI host processor programming model is shown in Figure 5-12. 5 - 12 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) DSP CPU HI FLAGS HOST FLAG 3 HOST FLAG 2 7 0 0 X:$FFE8 0 0 HF3 (0) HF2 (0) HCIE (0) HTIE (0) HRIE (0) HOST CONTROL REGISTER (HCR) (READ/WRITE) Freescale Semiconductor, Inc... INTERRUPT ENABLES HOST RECEIVE HOST TRANSMIT HOST COMMAND HOST HI FLAGS HOST FLAG 1 HOST FLAG 0 7 X:$FFE9 0 DMA (0) 0 0 HF1 (0) HF0 (0) HCP (0) HTDE HRDF HOST STATUS REGISTER (HSR) (READ ONLY) (1) (0) HOST RECEIVE DATA FULL HOST TRANSMIT DATA EMPTY HOST COMMAND PENDING 23 16 15 8 7 0 X:$FFEB RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE RECEIVE LOW BYTE X:$FFEB TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE 7 0 7 0 7 HOST RECEIVE DATA REGISTER (HRX) (READ ONLY) HOST TRANSMIT DATA REGISTER (HTX) (WRITE ONLY) 0 NOTE: The numbers in parentheses are reset values. Figure 5-9 Host Interface Programming Model – DSP Viewpoint The following paragraphs describe the purpose and operation of each bit in each register MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 13 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... of the HI visible to the DSP CPU. The effects of the different types of reset on these registers are shown. A brief discussion of interrupts and operation of the DSP side of the HI complete the programming model from the DSP viewpoint. The programming model from the host viewpoint begins at Section 5.3.3.1 Programming Model – Host Processor Viewpoint. 5.3.2.1 Host Control Register (HCR) The HCR is an 8-bit read/write control register used by the DSP to control the HI interrupts and flags. The HCR cannot be accessed by the host processor. It occupies the low-order byte of the internal data bus; the high-order portion is zero filled. Any reserved bits are read as zeros and should be programmed as zeros for future compatibility. (The bit manipulation instructions are useful for accessing the individual bits in the HCR.) The contents of the HCR are cleared on hardware or software reset. The control bits are described in the following paragraphs. 5.3.2.1.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 The HRIE bit is used to enable a DSP interrupt when the host receive data full (HRDF) status bit in the host status register (HSR) is set. When HRIE is cleared, HRDF interrupts are disabled. When HRIE is set, a host receive data interrupt request will occur if HRDF is also set. Hardware and software resets clear HRIE. 5.3.2.1.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 The HTIE bit is used to enable a DSP interrupt when the host transmit data empty (HTDE) status bit in the HSR is set. When HTIE is cleared, HTDE interrupts are disabled. When HTIE is set, a host transmit data interrupt request will occur if HTDE is also set. Hardware and software resets clear the HTIE. 5.3.2.1.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 The HCIE bit is used to enable a vectored DSP interrupt when the host command pending (HCP) status bit in the HSR is set. When HCIE is cleared, HCP interrupts are disabled. When HCIE is set, a host command interrupt request will occur if HCP is also set. The starting address of this interrupt is determined by the host vector (HV). Hardware and software resets clear the HCIE. 5.3.2.1.4 HCR Host Flag 2 (HF2) Bit 3 The HF2 bit is used as a general-purpose flag for DSP-to-host communication. HF2 may be set or cleared by the DSP. HF2 is visible in the interrupt status register (ISR) on the host processor side (see Figure 5-10). Hardware and software resets clear HF2. 5 - 14 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.2.1.5 HCR Host Flag 3 (HF3) Bit 4 The HF3 bit is used as a general-purpose flag for DSP-to-host communication. HF3 may be set or cleared by the DSP. HF3 is visible in the ISR on the host processor side (see Figure 5-10). Hardware and software resets clear HF3. Note: There are four host flags: two used by the host to signal the DSP (HF0 and HF1) and two used by the DSP to signal the host processor (HF2 and HF3). They are general purpose flags and are not designated for any specific purpose. The host flags do not cause interrupts; they must be polled to see if they have changed. These flags can be used individually or as encoded pairs. See Section 5.3.2.7 Host Port Usage Considerations – DSP Side for additional information. An example of the usage of host flags is the bootstrap loader, which is listed in the DSP56001 Technical Data Sheet. Host flags are used to tell the bootstrap program whether or not to terminate early. 5.3.2.1.6 HCR Reserved Control (Bits 5, 6, and 7) These unused bits are reserved for future expansion and should be written with zeros for upward compatibility. 5.3.2.2 Host Status Register (HSR) The HSR is an 8-bit read-only status register used by the DSP to interrogate status and flags of the HI. It can not be directly accessed by the host processor. When the HSR is read to the internal data bus, the register contents occupy the low-order byte of the data bus; the high-order portion is zero filled. The status bits are described in the following paragraphs. 5.3.2.2.1 HSR Host Receive Data Full (HRDF) Bit 0 The HRDF bit indicates that the host receive data register (HRX) contains data from the host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HRX register. HRDF is cleared when HRX is read by the DSP. HRDF can also be cleared by the host processor using the initialize function. Hardware, software, individual, and STOP resets clear HRDF. 5.3.2.2.2 HSR Host Transmit Data Empty (HTDE) Bit 1 The HTDE bit indicates that the host transmit data register (HTX) is empty and can be written by the DSP. HTDE is set when the HTX register is transferred to the RXH:RXM:RXL registers. HTDE is cleared when HTX is written by the DSP. HTDE can also be set by the host processor using the initialize function. Hardware, software, individual, and STOP sets HTDE. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 15 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.2.2.3 HSR Host Command Pending (HCP) Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared by the DSP exception hardware when the exception is taken. The host can clear HC, which also clears HCP. Hardware, software, individual, and STOP resets clear HCP. 5.3.2.2.4 HSR Host Flag 0 (HF0) Bit 3 The HF0 bit in the HSR indicates the state of host flag 0 in the ICR on the host processor side. HF0 can only be changed by the host processor (see Figure 5-10). Hardware, software, individual, and STOP resets clear HF0. 5.3.2.2.5 HSR Host Flag 1 (HF1) Bit 4 The HF1 bit in the HSR indicates the state of host flag 1 in the ICR on the host processor side. HF1 can only be changed by the host processor (see Figure 5-10). Hardware, software, individual, and STOP resets clear HF1. HOST TO DSP56002 STATUS FLAGS 7 HOST $0 0 INIT HM1 HM0 HF1 HF0 0 TREQ 7 DSP56002 X:$FFE9 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) RREQ 0 DMA 0 0 HF1 HF0 HCP HTDE HOST STATUS REGISTER (HSR) (READ ONLY) HRDF DSP56002 TO HOST STATUS FLAGS 7 HOST $2 0 HREQ DMA 0 HF3 HF2 TRDY TXDE 7 DSP56002 X:$FFE8 INTERRUPT STATUS REGISTER (ISR) (READ ONLY) RXDF 0 0 0 0 HF3 HF2 HCIE HTIE HRIE HOST CONTROL REGISTER (HCR) (READ/WRITE) Figure 5-10 Host Flag Operation 5 - 16 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.2.2.6 HSR Reserved Status (Bits 5 and 6) These status bits are reserved for future expansion and read as zero during DSP read operations. 5.3.2.2.7 HSR DMA Status (DMA) Bit 7 The DMA bit indicates that the host processor has enabled the DMA mode of the HI by setting HM1 or HM0 to one. When the DMA bit is zero, it indicates that the DMA mode is disabled by the HM0 and HM1 bits in the ICR and that no DMA operations are pending. When the DMA bit is set, the DMA mode has been enabled if one or more of the host mode bits have been set to one. The channel not in use can be used for polled or interrupt operation by the DSP. Hardware, software, individual, and STOP resets clear the DMA bit. 5.3.2.3 Host Receive Data Register (HRX) The HRX register is used for host-to-DSP data transfers. The HRX register is viewed as a 24-bit read-only register by the DSP CPU. The HRX register is loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host processor side when both the transmit data register empty TXDE (host processor side) and DSP host receive data full (HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HRX register contains valid data when the HRDF bit is set. Reading HRX clears HRDF. The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set. Resets do not affect HRX. 5.3.2.4 Host Transmit Data Register (HTX) The HTX register is used for DSP-to-host data transfers. The HTX register is viewed as a 24-bit write-only register by the DSP CPU. Writing the HTX register clears HTDE. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set. The HTX register is transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) if both the HTDE bit (DSP CPU side) and receive data full (RXDF) status bits (host processor side) are cleared. This transfer operation sets RXDF and HTDE. Data should not be written to the HTX until HTDE is set to prevent the previous data from being overwritten. Resets do not affect HTX. 5.3.2.5 Register Contents After Reset Table 5-1 shows the results of four reset types on bits in each of the HI registers seen by the DSP CPU. The hardware reset (HW) is caused by the RESET signal; the software reset (SW) is caused by executing the RESET instruction; the individual reset (IR) is caused by clearing PBC register bits 0 and 1, and the stop reset (ST) is caused by executing the STOP instruction. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 17 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Table 5-1 Host Registers after Reset–DSP CPU Side Reset Type Register Name Register Data HW Reset SW Reset IR Reset ST Reset HF(3 - 2) 0 0 — — HCIE 0 0 — — HTIE 0 0 — — HRIE 0 0 — — DMA 0 0 0 0 HF(1 - 0) 0 0 0 0 HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 HRX HRX (23 - 0) — — — — HTX HTX (23 - 0) — — — — Freescale Semiconductor, Inc... HCR HSR 5.3.2.6 Host Interface DSP CPU Interrupts The HI may request interrupt service from either the DSP or the host processor. The DSP CPU interrupts are internal and do not require the use of an external interrupt pin (see Figure 5-11). When the appropriate mask bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in the HSR, which generates an interrupt request to the DSP CPU. The DSP acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. The three possible interrupts are 1) receive data register full, 2) transmit data register empty, and 3) host command. The host command can access any interrupt vector in the interrupt vector table although it has a set of vectors reserved for host command use. The DSP interrupt service routine must read or write the appropriate HI register (clearing HRDF or HTDE, for example) to clear the interrupt. In the case of host command interrupts, the interrupt acknowledge from the program controller will clear the pending interrupt condition. 5.3.2.7 Host Port Usage Considerations – DSP Side Synchronization is a common problem when two asynchronous systems are connected, and careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. The considerations for proper operation on the DSP CPU side are discussed in the following paragraphs, and considerations for the host processor 5 - 18 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) MASK 7 0 0 X:$FFE 0 0 HF3 HF2 HCIE HTIE HCR HRIE DSP CPU INTERRUPTS RECIEVE DATA FULL P:$0020 Freescale Semiconductor, Inc... TRANSMIT DATA EMPTY P:$0022 HOST COMMAND P:(2xHV ➞ $0000 - $007E) RESET ➞ HV = $0012 in CVR 7 X:$FFE 0 DMA 0 0 HF1 HF2 HCP HTDE HRDF HCR STATUS Figure 5-11 HSR–HCR Operation side are discussed in Section 5.3.6.5 Host Port Usage Considerations – Host Side. DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. The only system problem with reading status occurs if HF1 and HF0 are encoded as a pair because each of their four combinations (00, 01, 10, and 11) has significance. There is a small possibility that the DSP will read the status bits during the transition and receive “01” or “10” instead of “11”. The solution to this potential problem is to read the bits twice for consensus (See Section 5.3.6.5 Host Port Usage Considerations – Host Side for additional information). 5.3.3 Host Interface – Host Processor Viewpoint The HI appears to the host processor as eight words of byte-wide static memory. The host may access the HI asynchronously by using polling techniques or interrupt-based techniques. Separate transmit and receive data registers are double buffered to allow the DSP CPU and host processor to transfer data efficiently at high speed. The HI contains a rudimentary DMA controller, which makes generating addresses (HA0–HA2) for the TX/RX MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 19 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... registers in the HI unnecessary. 5.3.3.1 Programming Model – Host Processor Viewpoint The HI appears to the host processor as a memory-mapped peripheral occupying eight bytes in the host processor address space (see Figure 5-12 and Figure 5-13). These registers can be viewed as one control register (ICR), one status register (ISR), three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), and two vector registers (IVR and CVR). The CVR is a special command register that is used by the host processor to issue commands to the DSP. These registers can be accessed only by the host processor; they can not be accessed by the DSP CPU. Host processors may use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the HI registers. The HI registers are addressed so that 8-bit MC6801-type host processors can use 16-bit load (LDD) and store (STD) instructions for data transfers. The 16-bit MC68000/MC68010 host processor can address the HI using the special MOVEP instruction for word (16-bit) or long-word (32-bit) transfers. The 32-bit MC68020 host processor can use its dynamic bus sizing feature to address the HI using standard MOVE word (16-bit), long-word (32-bit) or quad-word (64-bit) instructions. The HREQ and HACK handshake flags are provided for polled or interrupt-driven data transfers with the host processor. Because the DSP interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed I/O (non-DMA) instruction rate without testing the handshake flags for each transfer. If the full handshake is not needed, the host processor can treat the DSP as fast memory, and data can be transferred between the host processor and the DSP at the fastest host processor data rate. DMA hardware may be used with the handshake flags to transfer data without host processor intervention. One of the most innovative features of the host interface is the host command feature. With this feature, the host processor can issue vectored exception requests to the DSP56002. The host may select any one of 64 DSP56002 exception routines to be executed by writing a vector address register in the HI. This flexibility allows the host programmer to execute up to 64 preprogrammed functions inside the DSP56002. For example, host exceptions can allow the host processor to read or write DSP56002 registers (X, Y, or program memory locations), force exception handlers (e.g., SSI, SCI, IRQA, IRQB exception routines), and perform control and debugging operations if exception routines are implemented in the DSP56002 to perform these tasks. 5.3.3.2 Interrupt Control Register (ICR) The ICR is an 8-bit read/write control register used by the host processor to control the HI interrupts and flags. ICR cannot be accessed by the DSP CPU. ICR is a read/write regis- 5 - 20 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) MODES FLAGS 7 INIT (0) $0 Freescale Semiconductor, Inc... 0 HM1 (0) HM0 (0) 0 0 Interrupt Mode (DMA Off) 0 1 24-Bit DMA Mode 1 0 16-Bit DMA Mode 1 1 8-Bit DMA Mode 7 HF0 (0) TREQ RREQ (0) (0) 0 5 HC (0) $1 HF1 (0) 0 HOST VECTOR ($12) 0 FLAGS COMMAND VECTOR REGISTER (CVR) (READ/WRITE) STATUS 7 $2 HREQ (0) INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) 0 DMA (0) 0 HF3 (0) HF2 (0) TRDY TXDE RXDF (1) (1) (0) 7 INTERRUPT STATUS REGISTER (ISR) (READ ONLY) 0 INTERRUPT VECTOR NUMBER ($0F) $3 INTERRUPT VECTOR REGISTER (IVR) (READ/WRITE) RECEIVE BYTE REGISTERS (RXH:RXM:RXL) (READ ONLY) 31 $4 24 23 $5 16 15 $6 8 7 $7 00000000 RXH RECEIVE HIGH BYTE RXM RECEIVE MIDDLE BYTE RXL RECEIVE LOW BYTE NOT USED TXH TRANSMIT HIGH BYTE TXM TRANSMIT MIDDLE BYTE TXL TRANSMIT LOW BYTE 7 0 7 0 7 0 7 0 0 TRANSMIT BYTE REGISTERS (TXH:TXM:TXL) (WRITE ONLY) NOTE: The numbers in parentheses are reset values. Figure 5-12 Host Processor Programming Model – Host Side ter, which allows the use of bit manipulation instructions on control register bits. The MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 21 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... HOST ADDRESS HA0 - HA2 $0 ICR INTERRUPT CONTROL $1 CVR COMMAND VECTOR $2 ISR INTERRUPT STATUS $3 IVR INTERRUPT VECTOR $4 00000000 $5 RXH/TXH $6 RXM/TXM $7 RXL/TXL UNUSED RECEIVE/TRANSMIT BYTES HOST DATA BUS H0 - H7 Figure 5-13 HI Register Map control bits are described in the following paragraphs. 5.3.3.2.1 ICR Receive Request Enable (RREQ) Bit 0 The RREQ bit is used to control the HREQ pin for host receive data transfers. In interrupt mode (DMA off), RREQ is used to enable interrupt requests via the external host request (HREQ) pin when the receive data register full (RXDF) status bit in the ISR is set. When RREQ is cleared, RXDF interrupts are disabled. When RREQ is set, the external HREQ pin will be asserted if RXDF is set. In DMA modes, RREQ must be set or cleared by software to select the direction of DMA transfers. Setting RREQ sets the direction of DMA transfer to be DSP to host and enables the HREQ pin to request data transfer. Hardware, software, individual, and STOP resets clear RREQ. 5.3.3.2.2 ICR Transmit Request Enable (TREQ) Bit 1 The TREQ bit is used to control the HREQ pin for host transmit data transfers. In interrupt mode (DMA off), TREQ is used to enable interrupt requests via the external HREQ pin when the transmit data register empty (TXDE) status bit in the ISR is set. When TREQ is cleared, TXDE interrupts are disabled. When TREQ is set, the external HREQ pin will be asserted if TXDE is set. In DMA modes, TREQ must be set or cleared by software to select the direction of DMA transfers. Setting TREQ sets the direction of DMA transfer to be host to DSP and enables the HREQ pin to request data transfer. Hardware, software, individual, and STOP resets clear TREQ. 5 - 22 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Table 5-2 HREQ Pin Definition TREQ RREQ HREQ Pin Freescale Semiconductor, Inc... Interrupt Mode 0 0 No Interrupts (Polling) 0 1 RXDF Request (Interrupt) 1 0 TXDE Request (Interrupt) 1 1 RXDF and TXDE Request (Interrupts) DMA Mode 0 0 No DMA 0 1 DSP to Host Request (RX) 1 0 Host to DSP Request (TX) 1 1 Undefined (Illegal) Table 5-2 summarizes the effect of RREQ and TREQ on the HREQ pin. 5.3.3.2.3 ICR Reserved Bit (Bit 2) This bit, which is reserved and unused, reads as a logic zero. 5.3.3.2.4 ICR Host Flag 0 (HF0) Bit 3 The HF0 bit is used as a general-purpose flag for host-to-DSP communication. HF0 may be set or cleared by the host processor and cannot be changed by the DSP. HF0 is visible in the HSR on the DSP CPU side of the HI (see Figure 5-10). Hardware, software, individual, and STOP resets clear HF0. 5.3.3.2.5 ICR Host Flag 1 (HF1) Bit 4 The HF1 bit is used as a general-purpose flag for host-to-DSP communication. HF1 may be set or cleared by the host processor and cannot be changed by the DSP. Hardware, software, individual, and STOP resets clear HF1. 5.3.3.2.6 ICR Host Mode Control (HM1 and HM0 bits) Bits 5 and 6 The HM0 and HM1 bits select the transfer mode of the HI (see Table 5-3). HM1 and HM0 enable the DMA mode of operation or interrupt (non-DMA) mode of operation. When both HM1 and HM0 are cleared, the DMA mode is disabled, and the TREQ and RREQ control bits are used for host processor interrupt control via the external HREQ out- MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 23 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... Table 5-3 Host Mode Bit Definition HM1 HM0 Mode 0 0 Interrupt Mode (DMA Off) 0 1 DMA Mode (24 Bit) 1 0 DMA Mode (16 Bit) 1 1 DMA Mode (8 Bit) put pin. Also, in the non-DMA mode, the HACK input pin is used for the MC68000 Family vectored interrupt acknowledge input. When HM1 or HM0 are set, the DMA mode is enabled, and the HREQ pin is used to request DMA transfers. When the DMA mode is enabled, the TREQ and RREQ bits select the direction of DMA transfers. The HACK input pin is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted. The size of the DMA word to be transferred is determined by the DMA control bits, HM0 and HM1. The HI register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with the value in HM1 and HM0. The address counter substitutes for the HA1 and HA0 bits of the HI during a DMA transfer. The host address bit (HA2) is forced to one during each DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the host data bus, the address counter is incremented to the next register. When the address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in HM1 and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 pins. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. Hardware, software, individual, and STOP resets clear HM1 and HM0. 5.3.3.2.7 ICR Initialize Bit (INIT) Bit 7 The INIT bit is used by the host processor to force initialization of the HI hardware. Initialization consists of configuring the HI transmit and receive control bits and loading HM1 and HM0 into the internal DMA address counter. Loading HM1 and HM0 into the DMA address counter causes the HI to begin transferring data on a word boundary rather than 5 - 24 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... transferring only part of the first data word. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 25 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Table 5-4 HREQ Pin Definition TREQ RREQ Transfer Direction Initialized After INIT Execution Freescale Semiconductor, Inc... Interrupt Mode (HM1 = 0, HM0 = 0) INIT Execution 0 0 INIT = 0; Address Counter = 00 None 0 1 INIT = 0; RXDF = 0; HTDE = 1; Address Counter = 00 DSP to Host 1 0 INIT = 0; TXDE = 1; HRDF = 0; Address Counter = 00 Host to DSP 1 1 INIT = 0; RXDF = 0; HTDE = 1; TXDE = 1; HRDF = 0; Address Counter = 00 Host to/from DSP DMA Mode (HM1 or HM0 = 1) INIT Execution 0 0 INIT = 0; Address Counter = HM1, HM0 None 0 1 INIT = 0; RXDF = 0; HTDE = 1; Address Counter = HM1, HM0 DSP to Host 1 0 INIT = 0; TXDE = 1; HRDF = 0; Address Counter = HM1, HM0 Host to DSP 1 1 Undefined (Illegal) Undefined There are two methods of initialization: 1) allowing the DMA address counter to be automatically set after transferring a word, and 2) setting the INIT bit, which sets the DMA address counter. Using the INIT bit to initialize the HI hardware may or may not be necessary, depending on the software design of the interface. The type of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the HI. The INIT command, which is local to the HI, is designed to conveniently configure the HI into the desired data transfer mode. The commands are described in the following paragraphs and in Table 5-4. The host sets the INIT bit, which causes the HI hardware to execute the INIT command. The interface hardware clears the INIT bit when the command has been executed. Hardware, software, individual, and STOP resets clear INIT. INIT execution always loads the DMA address counter and clears the channel according to TREQ and RREQ. INIT execution is not affected by HM1 and HM0. The internal DMA counter is incremented with each DMA transfer (each HACK pulse) until it reaches the last data register (RXL or TXL). When the DMA transfer is completed, the counter is loaded with the value of the HM1 and HM0 bits. When changing the size of the 5 - 26 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... DMA word (changing HM0 and HM1 in the ICR), the DMA counter is not automatically updated, and, as a result, the DMA counter will point to the wrong data register immediately after HM1 and HM0 are changed. The INIT function must be used to preset the internal DMA counter correctly. Always set INIT after changing HM0 and HM1. However, the DMA counter can not be initialized in the middle of a DMA transfer. Even though the INIT bit is set, the internal DMA controller will wait until after completing the data transfer in progress before executing the initialization. 5.3.3.3 Command Vector Register (CVR) The host processor uses the CVR to cause the DSP to execute a vectored interrupt. The host command feature is independent of the data transfer mechanisms in the HI. It can be used to cause any of the 64 possible interrupt routines in the DSP CPU to be executed. The command vector register is shown in Figure 5-14. 5.3.3.3.1 CVR Host Vector (HV) Bits 0–5 The six HV bits select the host command exception address to be used by the host command exception logic. When the host command exception is recognized by the DSP interrupt control logic, the starting address of the exception taken is 2×HV. The host can write HC and HV in the same write cycle, if desired. 7 6 5 4 3 2 1 0 HC * HV5 HV4 HV3 HV2 HV1 HV0 HOST VECTOR RESERVED HOST COMMAND Figure 5-14 Command Vector Register The host processor can select any of the 64 possible exception routine starting addresses in the DSP by writing the exception routine starting address divided by 2 into HV. This means that the host processor can force any of the existing exception handlers (SSI, SCI, IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused starting addresses provided they have been preprogrammed in the DSP. HV is set to $12 (vector location $0024) by hardware, software, individual, and STOP resets. Vector location $0024 is the first of 45 special host command vectors. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 27 Freescale Semiconductor, Inc. HOST INTERFACE (HI) CAUTION The HV should not be used with a value of zero because the reset location is normally programmed with a JMP instruction. Doing so will cause an improper fast interrupt. Freescale Semiconductor, Inc... 5.3.3.3.2 CVR Reserved Bit (Bit 6) Reserved bit which is unused and read by the host processor as zero. 5.3.3.3.3 CVR Host Command Bit (HC) Bit 7 The HC bit is used by the host processor to handshake the execution of host command exceptions. Normally, the host processor sets HC=1 to request the host command exception from the DSP. When the host command exception is acknowledged by the DSP, the HC bit is cleared by the HI hardware. The host processor can read the state of HC to determine when the host command has been accepted. The host processor may elect to clear the HC bit, canceling the host command exception request at any time before it is accepted by the DSP CPU. CAUTION The command exception might be recognized by the DSP and executed before it can be canceled by the host, even if the host clears the HC bit. Setting HC causes host command pending (HCP) to be set in the HSR. The host can write HC and HV in the same write cycle if desired. Hardware, software, individual, and STOP resets clear HC. 5.3.3.4 Interrupt Status Register (ISR) The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the HI. The host processor can write this address without affecting the internal state of the HI, which is useful if the user desires to access all of the HI registers by stepping through the HI addresses. The ISR can not be accessed by the DSP. The status bits are described in the following paragraphs. 5.3.3.4.1 ISR Receive Data Register Full (RXDF) Bit 0 The RXDF bit indicates that the receive byte registers (RXH, RXM, and RXL) contain data from the DSP CPU and may be read by the host processor. RXDF is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the receive data low (RXL) register is read by the host processor. RXL is normally the last byte of the receive byte registers to be read by the host processor. RXDF can be cleared by the host processor using the initialize function. RXDF may be used to assert the external HREQ pin if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF 5 - 28 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... provides valid status so that polling techniques may be used by the host processor. Hardware, software, individual, and STOP resets clear RXDF. 5.3.3.4.2 ISR Transmit Data Register Empty (TXDE) Bit 1 The TXDE bit indicates that the transmit byte registers (TXH, TXM, and TXL) are empty and can be written by the host processor. TXDE is set when the transmit byte registers are transferred to the HRX register. TXDE is cleared when the transmit byte low (TXL) register is written by the host processor. TXL is normally the last byte of the transmit byte registers to be written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HREQ pin if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE provides valid status so that polling techniques may be used by the host processor. Hardware, software, individual, and STOP resets set TXDE. 5.3.3.4.3 ISR Transmitter Ready (TRDY) Bit 2 The TRDY status bit indicates that both the TXH,TXM,TXL and the HRX registers are empty. TRDY=TXDE • HRDF When TRDY is set to one, the data that the host processor writes to TXH,TXM, and TXL will be immediately transferred to the DSP CPU side of the HI. This has many applications. For example, if the host processor issues a host command which causes the DSP CPU to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI is what is being received by the DSP CPU. Hardware, software, individual, and STOP resets set TRDY. 5.3.3.4.4 ISR Host Flag 2 (HF2) Bit 3 The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the CPU side. HF2 can only be changed by the DSP (see Figure 5-10). HF2 is cleared by a hardware or software reset. 5.3.3.4.5 ISR Host Flag 3 (HF3) Bit 4 The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the CPU side. HF3 can only be changed by the DSP (see Figure 5-10). HF3 is cleared by a hardware or software reset. 5.3.3.4.6 ISR Reserved Bit (Bit 5) This status bit is reserved for future expansion and will read as zero during host processor read operations. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 29 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.3.4.7 ISR DMA Status (DMA) Bit 6 The DMA status bit indicates that the host processor has enabled the DMA mode of the HI (HM1 or HM0=1). When the DMA status bit is clear, it indicates that the DMA mode is disabled (HM0=HM1=0) and no DMA operations are pending. When DMA is set, it indicates that the DMA mode is enabled and the host processor should not use the active DMA channel (RXH, RXM, RXL or TXH, TXM, TXL depending on DMA direction) to avoid conflicts with the DMA data transfers. The channel not in use can be used for polled operation by the host and operates in the interrupt mode for internal DSP exceptions or polling. Hardware, software, individual, and STOP resets clear the DMA status bit. 5.3.3.4.8 ISR Host Request (HREQ) Bit 7 The HREQ bit indicates the status of the external host request output pin (HREQ). When the HREQ status bit is cleared, it indicates that the external HREQ pin is deasserted and no host processor interrupts or DMA transfers are being requested. When the HREQ status bit is set, it indicates that the external HREQ pin is asserted, indicating that the DSP is interrupting the host processor or that a DMA transfer request is occurring. The HREQ interrupt request may originate from either or both of two sources – the receive byte registers are full or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ will be set if one or more of the two enabled interrupt sources is set. Hardware, software, individual, and STOP resets clear HREQ. 5.3.3.5 Interrupt Vector Register (IVR) The IVR is an 8-bit read/write register which typically contains the exception vector number used with MC68000 Family processor vectored interrupts. Only the host processor can read and write this register. The contents of IVR are placed on the host data bus (H0–H7) when both the HREQ and HACK pins are asserted and the DMA mode is disabled. The contents of this register are initialized to $0F by a hardware or software reset, which corresponds to the uninitialized exception vector in the MC68000 Family. 5.3.3.6 Receive Byte Registers (RXH, RXM, RXL) The receive byte registers are viewed as three 8-bit read-only registers by the host processor. These registers are called receive high (RXH), receive middle (RXM), and receive low (RXL). These three registers receive data from the high byte, middle byte, and low byte, respectively, of the HTX register and are selected by three external host address inputs (HA2, HA1, and HA0) during a host processor read operation or by an on-chip address counter in DMA operations. The receive byte registers (at least RXL) contain valid data when the receive data register full (RXDF) bit is set. The host processor may 5 - 30 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... program the RREQ bit to assert the external HREQ pin when RXDF is set. This informs the host processor or DMA controller that the receive byte registers are full. These registers may be read in any order to transfer 8-, 16-, or 24-bit data. However, reading RXL clears the receive data full RXDF bit. Because reading RXL clears the RXDF status bit, it is normally the last register read during a 16- or 24-bit data transfer. Reset does not affect RXH, RXM, or RXL. 5.3.3.7 Transmit Byte Registers (TXH, TXM, TXL) The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These registers are called transmit high (TXH), transmit middle (TXM), and transmit low (TXL). These three registers send data to the high byte, middle byte and low byte, respectively, of the HRX register and are selected by three external host address inputs (HA2, HA1, and HA0) during a host processor write operation. Data may be written into the transmit byte registers when the transmit data register empty (TXDE) bit is set. The host processor may program the TREQ bit to assert the external HREQ pin when TXDE is set. This informs the host processor or DMA controller that the transmit byte registers are empty. These registers may be written in any order to transfer 8-, 16-, or 24-bit data. However, writing TXL clears the TXDE bit. Because writing the TXL register clears the TXDE status bit, TXL is normally the last register written during a 16- or 24-bit data transfer. The transmit byte registers are transferred as 24-bit data to the HRX register when both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF. Reset does not affect TXH, TXM, or TXL. 5.3.3.8 Registers After Reset Table 5-5 shows the result of four kinds of reset on bits in each of the HI registers seen by the host processor. The hardware reset is caused by asserting the RESET pin; the software reset is caused by executing the RESET instruction; the individual reset is caused by clearing the PBC register bit 0; and the stop reset is caused by executing the STOP instruction. 5.3.4 Host Interface Pins The 15 HI pins are described here for convenience. Additional information, including timing, is given in the DSP56002 Technical Data Sheet (DSP56002/D). 5.3.4.1 Host Data Bus(H0-H7) This bidirectional data bus transfers data between the host processor and the DSP56002. It acts as an input unless HEN is asserted and HR/W is high, making H0–H7 become outputs and allowing the host processor to read DSP56002 data. It is high impedance when HEN is deasserted. H0–H7 can be programmed as general-purpose I/O pins (PB0–PB7) MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 31 Freescale Semiconductor, Inc. HOST INTERFACE (HI) when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset. 5.3.4.2 Host Address (HA0–HA2) These inputs provide the address selection for each host interface register. HA0–HA2 can be programmed as general-purpose I/O pins (PB8–PB10) when the host interface is not being used. These pins are configured as GPIO input pins during hardware reset. Freescale Semiconductor, Inc... Table 5-5 Host Registers after Reset (Host Side) Reset Type Register Name ICR Register Data HW Reset SW Reset IR Reset ST Reset INIT 0 0 0 0 HM (1 - 0) 0 0 0 0 TREQ 0 0 0 0 RREQ 0 0 0 0 HF (1 - 0) 0 0 0 0 HC 0 0 0 0 $12 $12 $12 $12 HREQ 0 0 0 0 DMA 0 0 0 0 HF (3 - 2) 0 0 — — TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 $0F $0F — — RXH (23 - 16) — — — — RXM (15 - 8) — — — — RXL (7 - 0) — — — — TXH (23 - 21) — — — — TXM (15 - 8) — — — — TXL (7 - 0) — — — — CVR HV (5 - 0) ISR IVR RX TX 5 - 32 IV (7 - 0) PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.4.3 Host Read/Write (HR/W) This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W is stable when HEN is asserted. It can be programmed as a general-purpose I/O pin (PB11) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset. 5.3.4.4 Host Enable (HEN) This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56002 data. When HEN is asserted and HR/W is low, H0–H7 become inputs. When HEN is deasserted, host data is latched inside the DSP. Normally, a chip select signal derived from host address decoding and an enable clock are used to generate HEN. HEN can be programmed as a general-purpose I/O pin (PB12) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset. 5.3.4.5 Host Request (HREQ) This open-drain output signal is used by the DSP56002 HI to request service from the host processor, DMA controller, or a simple external controller. HREQ may be connected to an interrupt request pin of a host processor, a transfer request of a DMA controller or a control input of external circuitry. HREQ is asserted when an enabled request occurs in the host interface. HREQ is deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used. 5.3.4.6 Host Acknowledge (HACK) The Port B Control register allows the user to program this input independently of the other Host Interface pins. When the port is defined for general purpose I/O, this input acts Table 5-6 Port B Pin Definitions MOTOROLA BC0 BC1 Function 0 0 Parallel I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (HACK is defined as general purpose I/O) 1 1 Reserved PORT B For More Information On This Product, Go to: www.freescale.com 5 - 33 Freescale Semiconductor, Inc. HOST INTERFACE (HI) as a general purpose I/O pin called PB14. When the port is defined as the host interface, the user may manipulate the Port B Control register to program this input as either PB14, or as the HACK pin. The table below shows the Port B Control register bit configurations. HACK may act as a data strobe for HI DMA data transfers (See Figure 5-18). Or, if HACK is used as an MC68000 host interrupt acknowledge, it enables the HI interrupt vector register (IVR) on the host data bus H0-H7 if HREQ is asserted (See Figure 5-16). In this case, all other HI control pins are ignored and the state of the HI is not affected. Freescale Semiconductor, Inc... Note: HACK should always be pulled high when it is not in use. 5.3.5 Servicing the Host Interface The HI can be serviced by using one of the following protocols: 1. Polling 2. Interrupts, which can be either a. non-DMA b. DMA From the host processor viewpoint, the service consists of making a data transfer since this is the only way to reset the appropriate status bits. DSP56002 3 HA0 - HA2 HA0 - HA2 HR/W HR/W HEN HEN 8 H0 - H7 H0 - H7 +5 V WRITE DATA LATCHED IN HI READ HREQ +5 V HACK Figure 5-15 Host Processor Transfer Timing 5 - 34 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) 5.3.5.1 HI Host Processor Data Transfer The HI looks like static RAM to the host processor. Accordingly, in order to transfer data with the HI, the host processor: Freescale Semiconductor, Inc... 1. asserts the HI address (HA0, HA1, HA2) to select the register to be read or written 2. asserts HR/W to select the direction of the data transfer 3. strobes the data transfer using HEN. When data is being written to the HI by the host processor, the positive-going edge of HEN latches the data in the HI register selected. When data is being read by the host processor, the negative-going edge of HEN strobes the data onto the data bus H0-H7 Figure 5-15 illustrates this process. The specified timing relationships are given in the DSP56002 Technical Data Sheet. 5.3.5.2 HI Interrupts Host Request (HREQ) The host processor interrupts are external and use the HREQ pin. HREQ is normally connected to the host processor maskable interrupt (IPL0, IPL1 or IPL2 in Figure 5-16) input. 7 0 $3 MC68000 INTERRUPT VECTOR NUMBER INTERRUPT VECTOR REGISTER (IVR) (READ/WRITE) 1. THE DSP56002 ASERTS HREQ TO INTERRUPT THE HOST PROCESSOR. +5 V IPL2 IPL1 IPL0 DSP56002 1K HREQ 2. THE HOST PROCESSOR ASSERTS HACK WITH ITS INTERRUPT ACKNOWLEDGE CYCLE. HACK IACK A1 - A31 FC0 - FC2 IACK LOGIC AS $0F 3. WHEN HREQ AND HACK ARE SIMULTANEOUSLY ASSERTED, THE CONTENTS OF THE IVR ARE PLACED ON THE HOST DATA BUS. INTERRUPT VECTOR REGISTER (IVR) H0 - H7 D0 - D7 Figure 5-16 Interrupt Vector Register Read Timing The host processor acknowledges host interrupts by executing an interrupt service rou- MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 35 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... tine. The most significant bit (HREQ) of the ISR may be tested by the host processor to determine if the DSP is the interrupting device and the two least significant bits (RXDF and TXDE) may be tested to determine the interrupt source (see Figure 5-17). The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt. HREQ is deasserted when1) the enabled request is cleared or masked, 2) DMA HACK is asserted, or 3) the DSP is reset. 5.3.5.3 Polling In the polling mode of operation, the HREQ pin is not connected to the host processor and HACK must be deasserted to insure DMA data or IVR data is not being output on H0-H7 when other registers are being polled. The host processor first performs a data read transfer to read the ISR (see Figure 5-17) to determine, whether: 1. RXDF=1, signifying the receive data register is full and therefore a data read should be performed 2. TXDE=1, signifying the transmit data register is empty so that a data write can be performed 3. TRDY=1, signifying the transmit data register is empty and that the receive data register on the DSP CPU side is also empty so that the data written by the host processor will be transferred directly to the DSP side 4. HF2 • HF3 ≠ 0, signifying an application-specific state within the DSP CPU has been reached, which requires action on the part of the host processor 5. DMA=1, signifying the HI is currently being used for DMA transfers. If DMA transfers are possible in the system, deactivate HACK prior to reading the ISR so both DMA data and the contents of ISR are not simultaneously output on H0- H7 6. If HREQ=1, the HREQ pin has been asserted, and one of the previous five conditions exists Generally, after the appropriate data transfer has been made, the corresponding status bit will toggle. If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit, it can read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP’s central processing module. When the command has been accepted for execution, the interrupt controller will reset the HC bit. 5 - 36 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) STATUS 7 $2 0 HREQ DMA 0 HF3 HF2 TRDY TXDE ISR RXDF EXCEPTION SOURCE HREQ ASSERTED Freescale Semiconductor, Inc... HREQ 7 $3 0 INIT HM1 HM0 HF1 HF0 0 TREQ RREQ ICR MASK Figure 5-17 HI Interrupt Structure 5.3.5.4 Servicing Non-DMA Interrupts When HM0=HM1=0 (non-DMA) and HREQ is connected to the host processor interrupt input, the HI can request service from the host processor by asserting HREQ. In the nonDMA mode, HREQ will be asserted when TXDE=1 and/or RXDF=1 and the corresponding mask bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 5-17. Generally, servicing the interrupt starts with reading the ISR, as described in the previous section on polling, to determine which DSP has generated the interrupt and why. When multiple DSPs occur in a system, the HREQ bit in the ISR will normally be read first to determine the interrupting device. The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt. HREQ is deasserted when the enabled request is cleared or masked. In the case where the host processor is a member of the MC680XX Family, servicing the interrupt will start by asserting HREQ to interrupt the processor (see Figure 5-17). The host processor then acknowledges the interrupt by asserting HACK. While HREQ and HACK are simultaneously asserted, the contents of the IVR are placed on the host data bus. This vector will tell the host processor which routine to use to service the HREQ interrupt. The HREQ pin is an open-drain output pin so that it can be wire-ORed with the HREQ pins from other DSP56002 processors in the system. When the DSP56002 generates an interrupt request, the host processor can poll the HREQ bit in each of the ISRs to determine which device generated the interrupt. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 37 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.5.5 Servicing DMA Interrupts When HM0≠0 and/or HM1≠0, HREQ will be asserted to request a DMA transfer. Generally the HREQ pin will be connected to the REQ input of a DMA controller. The HA0-2, HEN, and HR/W pins are not used during DMA transfers; DMA transfers only use the HREQ and HACK pins after the DMA channel has been initialized. HACK is used to strobe the data transfer as shown in Figure 5-18 where an MC68440 is used as the DMA controller. DMA transfers to and from the HI are considered in more detail in Section 5.3.6 HI Application Examples. 5.3.6 HI Application Examples The following paragraphs describe examples of initializing the HI, transferring data with the HI, bootstrapping via the HI, and performing DMA transfers through the HI. 5.3.6.1 HI Initialization Initializing the HI takes two steps (see Figure 5-19). The first step is to initialize the DSP TO IRQB DSP56002 MC68440 IRQ +5 V +5 V CI D Q REQ0 HREQ +5 V ACK0 HACK A0 A1 AS OWN BURST REQ0 FAST INTERRUPT TO TRANSFER 24-BIT WORD 8T HACK HIGH BYTE MIDDLE BYTE LOW BYTE HIGH BYTE DMA ACK GATED OFF 1 DMA CYCLE = 8T = 4 DMA CLOCK CYCLES MAX. MC68440 CLOCK = 10 MHz = > T = 50 ns Figure 5-18 DMA Transfer Logic and Timing 5 - 38 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... STEP 1 THE DSP CPU INITIALIZES THE DSP SIDE OF THE HI BY WRITING: 1) HCR AT X:$FFE8 AND 2) PBC AT X:$FFE0 STEP 2 THE HOST PROCESOR INITIALIZES THE HOST SIDE OF THE HI BY WRITING: 1) ICR AT $0 AND/OR 2) CVR AT $1 AND/OR 3) IVR AT $3 Figure 5-19 HI Initialization Flowchart side of the HI, which requires that the options for interrupts and flags be selected and then the HI be selected (see Figure 5-20). The second step is for the host processor to clear the HC bit by writing the CVR, select the data transfer method - polling, interrupts, or DMA (see Figure 5-21 (d) and Figure 5-23), and write the IVR in the case of a MC680XX Family host processor. Figure 5-19 through Figure 5-22 provide a general description of how to initialize the HI. Later paragraphs in this section provide more detailed descriptions for specific examples.These subsections include some code fragments illustrating how to initialize and transfer data using the HI. 5.3.6.2 Polling/Interrupt Controlled Data Transfer Handshake flags are provided for polled or interrupt-driven data transfers. Because the DSP interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed I/O (non-DMA) instruction rate without testing the handshake flags for each transfer. If the full handshake is not needed, the host processor can treat the DSP as fast memory, and data can be transferred between the host and DSP at the fastest host processor rate. DMA hardware may be used with the external host request and host acknowledge pins to transfer data at the maximum DSP interrupt rate. The basic data transfer process from the host processor’s view (see Figure 5-15) is for the host to: 1. 2. 3. 4. Assert HREQ when the HI is ready to transfer data Assert HACK If the interface is using HACK Assert HR/W to select whether this operation will read or write a register Assert the HI address (HA2, HA1, and HA0) to select the register to be read or written MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 39 Freescale Semiconductor, Inc. HOST INTERFACE (HI) 5. Assert HEN to enable the HI 6. When HEN is deasserted, the data can be latched or read as appropriate if the timing requirements have been observed 7. HREQ will be deasserted if the operation is complete STEP 1 OF HOST PORT CONFIGURATION Freescale Semiconductor, Inc... 1. ENABLE/DISABLE HOST RECEIVE DATA FULL INTERRUPT ENABLE INTERRUPT: BIT 0 = 1 DISABLE INTERRUPT: BIT 0 = 0 2, ENABLE/DISABLE HOST TRANSMIT DATA EMPTY INTERRUPT ENABLE INTERRUPT: BIT 1 = 1 DISABLE INTERRUPT: BIT 1 = 0 3. ENABLE/DISABLE HOST COMMAND PENDING INTERRUPT ENABLE INTERRUPT: BIT 2 = 1 DISABLE INTERRUPT: BIT 2 = 0 4. SET/CLEAR HOST FLAG 2 (OPTIONAL) ENABLE FLAG: BIT 3 = 1 DISABLE FLAG: BIT 3 = 0 5. SET/CLEAR HOST FLAG 3 (OPTIONAL) ENABLE FLAG: BIT 4 = 1 DISABLE FLAG: BIT 4 = 0 7 X:$FFE8 * 6 * 5 4 3 * HF3 HF2 2 1 0 HCIE HTIE HRIE HOST CONTROL REGISTER (HCR) (READ/WRITE) 6. SELECT PORT B FOR HOST PORT OPERATION: 15 X:$FFE0 * * * * 0 * * * * * * * * * * BC BC 1 0 * Reserved; write as zero. NOTE: The host flags are general-purpose semaphores. They are not required for host port operation but may be used in some applications. Figure 5-20 HI Initialization–DSP Side 5 - 40 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) STEP 2 OF HOST PORT CONFIGURATION 1. CLEAR HOST COMMAND BIT (HC): BIT 7 = 0 7 $1 6 HC 5 0 COMMAND VECTOR REGISTER (CVR) (READ/WRITE) HV * Freescale Semiconductor, Inc... *Reserved; write as zero. 2. OPTION 1: SELECT HOST VECTOR (HV) (OPTIONAL SINCE HV CAN BE SET ANY TIME BEFORE THE HOST COMMAND IS EXECUTED. DSP INTERRUPT VECTOR = THE HOST VECTOR MULTIPLIED BY 2. DEFAULT (UPON DSP RESET): HV = $12 ➞ DSP INTERRUPT VECTOR $0024 Figure 5-21 (a) HI Configuration–Host Side STEP 2 OF HOST PORT CONFIGURATION 2. OPTION 2: SELECT POLLING MODE FOR HOST TO DSP COMMUNICATION INITIALIZE DSP AND HOST PORT DMA OFF BIT 5 = 0 BIT 6 = 0 7 $0 INIT 6 HM1 DISABLE INTERRUPTS BIT 0 = 0 BIT 1 = 0 OPTIONAL 5 4 HM0 HF1 3 2 HF0 * 1 0 TREQ RREQ INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) *Reserved; write as zero. Figure 5-21 (b) HI Initialization–Host Side, Polling Mode The previous transfer description is an overview. Specific and exact information for the HI data transfers and their timing can be found in Section 5.3.6.3 DMA Data Transfer and in the DSP56002 Advance Information Data Sheet (DSP56002/D). 5.3.6.2.1 Host to DSP - Data Transfer Figure 5-23 shows the bits in the ISR and ICR registers used by the host processor and the bits in the HSR and HCR registers used by the DSP to transfer data from the host processor to the DSP. The registers shown are the status register and control register as they are seen by the host processor, and the status register and control register as they are seen by the DSP. Only the registers used to transmit data from the host processor to the DSP are MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 41 Freescale Semiconductor, Inc. HOST INTERFACE (HI) STEP 2 OF HOST PORT CONFIGURATION 2. OPTION 3: SELECT INTERRUPT MODE FOR DSP TO HOST OR HOST TO DSP INITIALIZE DSP INITIALIZE HI** BIT 7 = 1 DSP TO HOST AND HOST TO DSP OPTIONAL Freescale Semiconductor, Inc... ENABLE TRANSMIT DATA EMPTY INTERRUPT BIT 0 = 0 BIT 1 = 1 OR DMA OFF BIT 5 = 0 BIT 6 = 0 $0 ENABLE RECEIVE DATA FULL INTERRUPT BIT 0 = 1 BIT 1 = 0 7 6 5 4 3 2 INIT HM1 HM0 HF1 HF0 * 1 ENABLE RECEIVE DATA FULL INTERRUPT AND TRANSMIT DATA EMPTY INTERRUPT BIT 0 = 1 BIT 1 = 1 0 TREQ RREQ INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) 2. OPTION 4: LOAD HOST INTERRUPT VECTOR IF USING THE INTERRUPT MODE AND THE HOST PROCESSOR REQUIRES AN INTERRUPT VECTOR. $3 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 INTERRUPT VECTOR REGISTER (IVR) (READ/WRITE) *Reserved; write as zero. **See Figure 10 - 23. Figure 5-21 (c) HI Initialization–Host Side, Interrupt Mode described. Figure 5-24 illustrates the process of that data transfer. The steps in Figure 524 can be summarized as follows: 1. 2. 3. 4. 5. 6. 5 - 42 When the TXDE bit in the ISR is set, it indicates that the HI is ready to receive a data byte from the host processor because the transmit byte registers (TXH, TXM, TXL) are empty. The host processor can poll as shown in this step. Alternatively, the host processor can use interrupts to determine the status of this bit. Setting the TREQ bit in the ICR causes the HREQ pin to interrupt the host processor when TXDE is set. Once the TXDE bit is set, the host can write data to the HI. It does this by writing three bytes to TXH, TXM, and TXL, respectively, or two bytes to TXM and TXL, respectively, or one byte to TXL. Writing data to TXL clears TXDE in the ISR. From the DSP’s viewpoint, the HRDF bit (when set) in the HSR indicates that data is waiting in the HI for the DSP. PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) 7. When the DSP reads the HRX, the HRDF bit is automatically cleared and TXDE in the ISR is set. When TXDE=0 and HRDF=0, data is automatically transferred from TBR to HRX which sets HRDF. The DSP can poll HRDF to see when data has arrived, or it can use interrupts. If HRIE (in the HCR) and HRDF are set, exception processing is started using interrupt vector P:$0020. 8. Freescale Semiconductor, Inc... 9. 10. The code shown in Figure 5-25 is an excerpt from the Host I/O Port Technical Bulletin (inhouse document). The MAIN PROGRAM initializes the HI and then hangs in a wait loop while it allows interrupts to transfer data from the host processor to the DSP. The first three MOVEP instructions enable the HI and configure the interrupts. The following MOVE enables the interrupts (this should always be done after the interrupt programs and hardware are completely initialized) and prepares the DSP CPU to look for the host flag, HF0=1. The JCLR instruction is a polling loop that looks for HF0=1, which indicates that the host processor is ready. When the host processor is ready to transfer data to the DSP, the DSP enables HRIE in the HCR, which allows the interrupt routine to receive data from the host processor. The jump-to-self instruction that follows is for test purposes only, it can be replaced by any other code in normal operation. STEP 2 OF HOST PORT CONFIGURATION 2. OPTION 5: SELECT DMA MODE FOR INITIALIZE DSP INITIALIZE HI** BIT 7 = 1 24-BIT DMA BIT 5 = 1 BIT 6 = 0 DSP TO HOST OR 16-BIT DMA BIT 5 = 0 BIT 6 = 1 OR OR HOST TO DSP DMA OFF BIT 5 = 1 BIT 6 = 1 7 $0 INIT ENABLE RECEIVE DATA FULL INTERRUPT BIT 0 = 1 BIT 1 = 0 ENABLE TRANSMIT DATA EMPTY INTERRUPT BIT 0 = 0 BIT 1 = 1 OPTIONAL 6 5 4 HM1 HM0 HF1 3 HF0 2 * 1 0 TREQ RREQ INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) *Reserved; write as zero. **See Figure 5-23. Figure 5-21 (d) HI Initialization–Host Side, DMA Mode MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 43 Freescale Semiconductor, Inc. HOST INTERFACE (HI) MODES 7 Freescale Semiconductor, Inc... HOST SETS INIT BIT INIT 0 HM1 HM0 HF1 HF0 0 TREQ 0 0 Interrupt Mode (DMA Off) 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) RREQ RESET CONDITION INTERRUPT MODE (DMA OFF) DMA MODE TREQ RREQ INIT Execution 0 0 INIT = 0; Address Counter = HM1, HM0 0 1 INIT = 0; RXDF = 0; HTDE = 1; Address Counter = HM1, HM0 TREQ RREQ 0 0 INIT = 0; Address Counter = 00 1 0 0 1 INIT = 0; RXDF = 0; HTDE = 1; Address Counter = 00 INIT = 0; TXDE = 1; HRDF = 0; Address Counter = HM1, HM0 1 1 Undefined (Illegal) 1 0 INIT Execution INIT = 0; TXDE = 1; HRDF = 0; Address Counter = 00 INIT is used by the HOST to force initialization of the HI hardware. The HI hardware automatically clears INIT when the command is executed. INIT is cleared by DSP RESET. Figure 5-22 Host Mode and INIT Bits The receive routine in Figure 5-26 was implemented as a long interrupt (the instruction at the interrupt vector location, which is not shown, is a JSR). Since there is only one instruction, this could have been implemented as a fast interrupt. The MOVEP instruction moves data from the HI to a buffer area in memory and increments the buffer pointer so that the next word received will be put in the next sequential location. 5.3.6.2.2 Host to DSP – Command Vector The host processor can cause three types of interrupts in the DSP (see Figure 5-27). These are host receive data (P:$0020), host transmit data (P:$0022), and host command (P:$0024 - P:$007E). The host command (HC) can be used to control the DSP by forcing it to execute any of 45 subroutines that can be used to run tests, transfer data, process data, etc. In addition, the HC can cause any of the other 19 interrupt routines in the DSP to be executed. The process to execute a HC (see Figure 5-28) is as follows: 5 - 44 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA HF3 HF2 TRDY TXDE RXDF DMA 0 0 HF1 HF0 HCP For More Information On This Product, Go to: www.freescale.com PORT B INIT HM0 0 1 0 1 HM1 0 0 1 1 HF0 0 TREQ RREQ 8 Bit DMA Mode 16 Bit DMA Mode 24 Bit DMA Mode Interrupt Mode (DMA Off) HF1 0 7 0 0 0 HF3 Figure 5-23 Bits Used for Host-to-DSP Transfer HRIE — HOST RECEIVE INTERRUPT ENABLE ENABLES INTERRUPT AT P:$0020 DSP INTERRUPT IS CAUSED BY HRDF = 1 1 = INTERRUPT P:$0020 ENABLED. 0 = INTERRUPT P:$0020 DISABLED. INTERRUPT CONTROL REGISTER (ICR) X:$FFE8 (READ/WRITE) TREQ — TRANSMIT REQUEST ENABLE USED TO ENABLE INTERRUPTS THAT COME FROM TXDE TO THE HOST VIA THE HREQ PIN. 1 = TXDE INTERRUPTS PASS TO HREQ. 0 = TXDE INTERRUPTS ARE MASKED. $0 7 MODES HF2 HCIE 0 HTDE HRDF HTIE 0 HRIE DMA —INDICATES THE HOST PROCESSOR HAS ENABLED THE DMA MODE 1 = DMA ON. 0 = HOST MODE. 0 7 TRDY — TRANSMITTER READY = TXDE • HRDF 1 = BOTH THE TRANSMIT BYTE REGISTERS AND THE HOST RECEIVE DATA REGISTERS ARE EMPTY. 0 = ONE OR BOTH REGISTERS ARE FULL. DMA INTERRUPT STATUS REGISTER (ISR) X:$FFE9 (READ ONLY) HRDF — HOST RECEIVE DATA FULL 1 = THE HOST RECEIVE REGISTER (HRX) CONTAINS DATA FROM THE HOST PROCESSOR. 0 = HRX IS EMPTY. HREQ 0 DSP56002 TXDE — TRANSMIT DATA REGISTER EMPTY 1 = INDICATES THE TRANSMIT BYTE REGISTERS (TXH, TXM, TXL) ARE EMPTY. 0 = CLEARED BY WRITING TO TXL; TXDE CAN BE USED TO ASSERT THE HREQ PIN. $2 7 HOST Freescale Semiconductor, Inc... HOST CONTROL REGISTER (HCR) (READ/WRITE) HOST STATUS REGISTER (HSR) (READ ONLY) Freescale Semiconductor, Inc. HOST INTERFACE (HI) 5 - 45 5 - 46 0 INIT 7 HF3 HF2 TRDY HM0 HM1 HF0 0 TREQ TRANSMIT REQUEST ENABLE 0 0 HF1 TXDE TRANSMIT DATA REGISTER EMPTY DMA HOST MAY POLL TXDE. HREQ 1 1 For More Information On This Product, Go to: www.freescale.com PORT B LAST WRITE RREQ 0 0 TRANSFER X:$FFE9 0 DMA 7 0 0 HF0 HCP HIGH BYTE MIDDLE BYTE 0 0 HF3 HF2 HCIE HTIE HRIE HOST RECEIVE INTERRUPT ENABLE 0 P:$0020 FAST INTERRUPT OR LONG INTERRUPT HOST RECEIVE DATA VECTOR 0 1 LOW BYTE 10. IF HRDF = 1 AND INTERRUPTS ARE ENABLED, THEN EXCEPTION PROCESSING BEGINS. X:$FFE8 7 9. THE TRANSFER SETS HRDF FOR THE DSP56002 TO POLL. X:$FFEB 23 HTDE HRDF HOST RECEIVE DATA FULL HF1 8. WHEN TXDE = 0 AND HRDF = 0, THEN TRANSFER OCCURS. INTERRUPT CONTROL REGISTER (ICR) INTERRUPT STATUS REGISTER (ISR) 0 0 0 VIEW FROM DSP56002 6. IF DSP560022 HAS OLD DATA IN HRX, THEN HRDF = 1. 7. WHEN DSP56002 READS HRX, THEN HRDF = 0. Figure 5-24 Data Transfer from Host to DSP TRANSMIT BYTE REGISTERS (TBR) TXL TXM $6 $7 TXH $5 7 WRITE TO TXL CLEARS TXDE IN ISR. HOST WRITES DATA TO TRANSMIT BYTE REGISTERS. HREQ PIN 0 RXDF IF TREQ = 1, THEN HREQ PIN IS ASSERTED TO INTERRUPT HOST. 0 2 7 WHEN TXDE = 1, TDR IS EMPTY. VIEW FROM HOST Freescale Semiconductor, Inc... HOST CONTROL REGISTER (HCR) HOST RECEIVE DATA REGISTER (HRX) HOST STATUS REGISTER (HSR) Freescale Semiconductor, Inc. HOST INTERFACE (HI) MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) EXCEPTION STARTING ADDRESS PROGRAM MEMORY SPACE Freescale Semiconductor, Inc... EXCEPTION SOURCE TWO WORDS PER VECTOR $0000 HARDWARE RESET $0002 STACK ERROR $0004 TRACE $0006 SWI (SOFTWARE INTERRUPT) $0008 IRQA EXTERNAL HARDWARE INTERRUPT $000A IRQB EXTERNAL HARDWARE INTERRUPT $000C SSI RECEIVE DATA $000E SSI RECEIVE DATA WITH EXCEPTION STATUS $0010 SSI TRANSMIT DATA $0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS $0014 SCI RECEIVE DATA $0016 SCI RECEIVE DATA WITH EXCEPTION STATUS $0018 SCI TRANSMIT DATA $001A SCI IDLE LINE $001C SCI TIMER $001E RESERVED $0020 HOST RECEIVE DATA $0022 HOST TRANSMIT DATA $0024 HOST COMMAND (DEFAULT) $0026 AVAILABLE FOR HOST COMMAND $0028 AVAILABLE FOR HOST COMMAND EXTERNAL INTERRUPTS INTERNAL INTERRUPTS EXTERNAL INTERRUPTS SYNCHRONOUS SERIAL INTERFACE INTERNAL INTERRUPTS • • • $003C AVAILABLE FOR HOST COMMAND $003E ILLEGAL INSTRUCTION $0040 AVAILABLE FOR HOST COMMAND $0042 AVAILABLE FOR HOST COMMAND $007E AVAILABLE FOR HOST COMMAND SERIAL COMMUNICATIONS INTERFACE HOST INTERFACE INTERNAL INTERRUPTS • • • Figure 5-27 HI Exception Vector Locations MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 47 5 - 48 For More Information On This Product, Go to: www.freescale.com PORT B 0 HC HOST COMMAND 1 5 EXCEPTION VECTOR ADDRESS = HV x 2 $12 — DEFAULT HOST VECTOR (HV) 0 $1 7 0 HOST VECTOR (HV) HC — HOST COMMAND (STATUS) 0 5 COMMAND VECTOR REGISTER (CVR) P:$007E P:$0024 P:$0000 X:$FFE8 HF1 HF0 0 0 0 HF3 HF2 FAST INTERRUPT OR LONG INTERRUPT AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND HOST COMMAND DEFAULT VECTOR EXCEPTION VECTOR TABLE HCIE HOST COMMAND INTERRUPT ENABLE 7 Figure 5-28 Host Command 0 0 HCP HOST COMMAND PENDING 0 4. HOST COMMAND IS MASKED UNTIL HCIE = 1. DMA 7 1 1 HTIE HRIE 0 HTDE HRDF 0 VIEW FROM DSP56002 3. HCP IS SET UNTIL EXCEPTION IS ACKNOWLEDGED. COMMAND VECTOR X:$FFE9 REGISTER (CVR) 5. WHEN THE HOST COMMAND EXCEPTION IS ACKNOWLEDGED, THE HC BIT IS CLEARED BY THE HOST COMMAND LOGIC. HC CAN BE READ AS A STATUS BIT. $1 7 2. SET HC = 1. 1. WRITE CVR WITH DESIRED HV. VIEW FROM HOST Freescale Semiconductor, Inc... HOST CONTROL REGISTER (HCR) HOST STATUS REGISTER (HSR) Freescale Semiconductor, Inc. HOST INTERFACE (HI) 1. The host processor writes the CVR with the desired HV (the HV is the DSP’s MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) 2. 3. 4. Freescale Semiconductor, Inc... 5. interrupt vector (IV) location divided by two - i.e. if HV=$12, IV=$24). The HC is then set. The HCP bit in the HSR is set when HC is set. If the HCIE bit in the HCR has been set by the DSP, the HC exception processing will start. The HV is multiplied by 2 and the result is used by the DSP as the interrupt vector. When the HC exception is acknowledged, the HC bit (and therefore the HCP bit) is cleared by the HC logic. HC can be read by the host processor as a status bit to determine when the command is accepted. Similarly, the HCP bit can be read by the DSP CPU to determine if an HC is pending. To guarantee a stable interrupt vector, write HV only when HC is clear. The HC bit and HV can be written simultaneously. The host processor can clear the HC bit to cancel a host command at any time before the DSP exception is accepted. Although the HV can be programmed to any exception vector, it is not recommended that HV=0 (RESET) be used because it does not reset the DSP hardware. DMA must be disabled to use the host exception. 5.3.6.2.3 Host to DSP - Bootstrap Loading Using the HI The circuit shown in Figure 5-29 will cause the DSP to boot through the HI on power up. During the bootstrap program, the DSP looks at the MODC, MODB, and MODA bits. If ;**************************************** ; MAIN PROGRAM... receive data from host ;**************************************** ORG P:$40 MOVE #0,R0 MOVE #3,M0 MOVEP #1,X:PBC ;Turn on Host Port MOVEP #0,X:HCR ;Turn off XMT and RCV interrupts MOVEP #$0C00,X:IPR ;Turn on host interrupt MOVE #0,SR ;Unmask interrupts JCLR #3,X:HSR,* ;Wait for HF0 (from host) set to 1 MOVEP #$1,X:HGR ;Enable host receive interrupt JMP * ;Now wait for interrupt Figure 5-25 Receive Data from Host–Main Program ;************************************ ; Receive from Host Interrupt Routine ;************************************ RCV MOVEP X:HRX,X:(R0)+ ;Receive data. RTI END Figure 5-26 Receive Data from Host Interrupt Routine MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 49 Freescale Semiconductor, Inc. HOST INTERFACE (HI) +5 V Freescale Semiconductor, Inc... DSP56002 DR HEN BR HACK WT MODA/IRQA FROM OPEN COLLECTOR BUFFER LDS F32 AS F32 ADDRESS DECODE MODC/NMI A4-A23 MC68000 +5 V (12.5MHz) 1K LS09 FROM RESET FUNCTION DTACK RESET MDB301* F32 HR/W 8 H0-H7 3 HA0-HA2 MODB/IRQB FROM OPEN COLLECTOR BUFFER F32 R/W D0-D7 A1-A3 Notes: 1. *This diode must be a Schottky diode. 2. All resistors are 15KΩ unless noted otherwise. 3. When in RESET, IRQA, IRQB and NMI must be deasserted by external peripherals. HOST 7 $0 INIT HM1 HM0 HF1 0 HF0 0 TREQ RREQ INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) SETTING HF0 TERMINATES BOOTSTRAP LOADING AND STARTS EXECUTION AT LOCATION P:$0000. SET HF0 FOR EARLY TERMINATION HOST ADDRESS WRITTEN 4 (DUMMY) 5 6 7 • • • 4 (DUMMY) 5 6 7 CONTENTS LOADED TO INTERNAL P: RAM AT: P:$0000 HIGH BYTE P:$0000 MID BYTE P:$0000 LOW BYTE • • • • P:$01FF HIGH BYTE P:$01FF MID BYTE P:$01FF LOW BYTE • Because the DSP56002 is so fast, host handshaking is generally not required. Figure 5-29 Bootstrap Using the HI 5 - 50 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... HOST INTERFACE (HI) the bits are set at 101 respectively, the DSP will load from the HI. Data is written by the host processor in a pattern of four bytes, with the high byte being a dummy and the low byte being the low byte of the DSP word (see Figure 5-29 and Figure 5-30). Figure 5-30 shows how an 8-,16-, 24-, or 32-bit word in the host processor maps into the HI registers. The HI register at address $4 is not used and will read as zero. It is not necessary to use address $4, but since many host processors are 16- or 32-bit processors, address $4 will often be used as part of the 16- or 32-bit word. The low order byte (at $7) should always be written last since writing to it causes the HI to initiate the transfer of the word to the HRX. Data is then transferred from the HRX to the DSP program memory. If the host processor needs to terminate the bootstrap loading before 512 words have been down loaded, it can set the HF0 bit in the ICR. The DSP will then terminate the down load and start executing at location P:$0000. Since the DSP56002 is typically faster than the host processor, hand shaking during the data transfer is normally not required. The actual code used in the bootstrap program is given in APPENDIX A. The portion of the code that loads from the HI is shown in Figure 5-31. The BSET instruction configures HOST TRANSMIT/RECEIVE BYTE REGISTERS 7 31 HOST DATA 24 23 READ - 00000000 WRITE - XXXXXXXX 16 15 HIGH HOST BYTE ADDRESS 0 00000000 4 TXH/RXH HIGH BYTE 5 TXM/RXM MIDDLE BYTE 6 TXL/RXL LOW BYTE 7 8 7 ACCESS TO LOW BYTE INITIATES TRANSFER 0 MIDDLE LOW 8-BIT TRANSFER 16-BIT TRANSFER 24-BIT TRANSFER 32-BIT TRANSFER, LS 24 BITS ARE SIGNIFICANT NOTE: Access low byte last Figure 5-30 Transmit/Receive Byte Registers MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 51 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... ;************************************************** ; This routine loads from the Host Interface. ; MC:MB:MA=100 - reserved ; MC:MB:MA=101 - Host ;************************************************* HOSTLD BSET #0,X:PBC DO #512,_LOOP3 _LBLA JCLR #3,X:HSR,_LBLB ENDDO JMP <_LOOP3 _LBLB JCLR #0,X:HSR,_LBLA MOVEP X:HRX,P:(R0)+ JMP <FINISH _LOOP3 ;Configure Port B as Host ;Load 512 instruction words ;If HF0=1, stop loading data. ;Must terminate the DO loop ; ;Wait for HRDF to go high ;(meaning data is present). ;Store 24-bit data in P memory ;and go get another 24-bit word. ;finish bootstrap Figure 5-31 Bootstrap Code Fragment Port B as the HI and the first JCLR looks for a flag (HF0) to indicate an early termination of the download. The second JCLR instruction causes the DSP to wait for a complete word to be received and then a MOVEP moves the data from the HI to memory. 5.3.6.2.4 DSP to Host Data Transfer Data is transferred from the DSP to the host processor in a similar manner as from the host processor to the DSP. Figure 5-32 shows the bits in the status registers (ISR and HSR) and control registers (ICR and HCR) used by the host processor and DSP CPU, respectively. The DSP CPU (see Figure 5-33) can poll the HTDE bit in the HSR (1) to see when it can send data to the host, or it can use interrupts enabled by the HTIE bit in the HCR (2). If HTIE=1 and interrupts are enabled, exception processing begins at interrupt vector P:$0022 (3). The interrupt routine should write data to the HTX (4), which will clear HTDE in the HSR. From the host’s viewpoint, (5) reading the RXL clears RXDF in the ISR. When RXDF=0 and HTDE=0 (6) the contents of the HTX will be transferred to the receive byte registers (RXH:RXM:RXL). This transfer sets RXDF in the ISR (7), which the host processor can poll to see if data is available or, if the RREQ bit in the ICR is set, the HI will interrupt the host processor with HREQ (8). The code shown in Figure 5-34 is essentially the same as the MAIN PROGRAM in Figure 5-25 except that, since this code will transmit instead of receive data, the HTIE bit is set in the HCR instead of the HRIE bit. The transmit routine used by the code in Figure 5-34 is shown in Figure 5-35. The interrupt vector contains a JSR, which makes it a long interrupt. The code sends a fixed test pattern 5 - 52 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA HREQ DMA 0 HF3 HF2 TRDY TXDE RXDF 0 For More Information On This Product, Go to: www.freescale.com PORT B INIT HM1 HM0 HF1 HF0 0 TREQ RREQ 0 INTERRUPT CONTROL REGISTER (HCR) (READ/WRITE) DMA 7 0 0 HF1 HF0 HCP 0 0 0 HF3 HF2 Figure 5-32 Bits Used for DSP to Host Transfer HTIE — HOST TRANSMIT INTERRUPT ENABLE 1 = ENABLE THE DSP INTERRUPT TO P:$0022. 0 = DISABLE THE DSP INTERRUPT TO P:$0022. DSP INTERRUPT IS CAUSED BY HTDE = 1 X:$FFE8 7 HCIE 0 HTIE HRIE 0 HTDE HRDF DSP56002 HTDE — HOST TRANSMIT DATA EMPTY 1 = HTX IS EMPTY AND CAN BE WRITTEN BY DSP. 0 = HTX IS FULL. INTERRUPT STATUS REGISTER (ISR) X:$FFE9 (READ ONLY) RREQ —RECEIVE REQUEST ENABLE (USED TO CONTROL THE HREQ PIN) 1 = ENABLE INTERRUPT REQUESTS CREATED BY RXDF. 0 = DISABLE INTERRUPT REQUESTS. $0 7 MODES RXDF — RECEIVE DATA REGISTER FULL 1 = INDICATES THE RECIEVE BYTE REGISTERS (RXH, RXM, RXL) CONTAIN DATA FROM THE DSP. 0 = CLEARED BY READING RXL. $2 7 HOST Freescale Semiconductor, Inc... HOST CONTROL REGISTER (HCR) (READ/WRITE) HOST STATUS REGISTER (HSR) (READ ONLY) Freescale Semiconductor, Inc. HOST INTERFACE (HI) ($123456) and then resets the HI for the next interrupt. 5 - 53 5 - 54 $7 RECEIVE BYTE REGISTERS (RBR) RXL $6 0 For More Information On This Product, Go to: www.freescale.com PORT B INIT 7 HREQ HM1 DMA HM0 0 HF1 HF3 TXDE 0 TREQ RXDF RECEIVE DATA FULL TRDY RREQ RECEIVE REQUEST ENABLE HF0 HF2 1 1 HREQ PIN 0 0 INTERRUPT CONTROL REGISTER (ICR) INTERRUPT STATUS REGISTER (ISR) DMA 0 0 HCP 0 HF3 HF2 HCIE HTIE HOST TRANSMIT INTERRUPT ENABLE 0 HF0 1 1 AVAILABLE FOR HOST COMMAND P:$007E X:$FFEB 23 HIGH BYTE MIDDLE BYTE 0 HRIE 0 0 HRDF LOW BYTE 4. DSP56002 WRITES DATA TO HTX, WHICH CLEARS HTDE IN HSR. FAST INTERRUPT OR LONG INTERRUPT HOST TRANSMIT DATA VECTOR P:$0022 P:$0000 3. IF HTIE = 1, AND INTERRUPTS ARE ENABLED, THEN EXCEPTION PROCESSING BEGINS. X:$FFE8 7 HF1 VIEW FROM HOST HTDE HOST TRANSMIT DATA EMPTY 0 2. DSP56002 MAY POLL HTDE. X:$FFE9 7 1. WHEN HTDE = 1, THEN HTX IS EMPTY. Figure 5-33 Data Transfer from DSP to Host 8. IF RREQ = 1, THEN HREQ PIN IS ASSERTED TO INTERRUPT HOST. $0 $2 7 7. THE TRANSFER SETS RXDF FOR THE HOST TO POLL. LAST READ RXH RXM $5 7 6. WHEN RXDF = 0 AND HTDE = 0, THEN TRANSFER OCCURS. 5. READ OF RXL BY HOST CLEARS RXDF IN ISR. VIEW FROM HOST Freescale Semiconductor, Inc... HOST RECEIVE DATA REGISTER (HSR) HOST CONTROL REGISTER (HCR) HOST STATUS REGISTER (HSR) Freescale Semiconductor, Inc. HOST INTERFACE (HI) MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) ;**************************************** ; MAIN PROGRAM... transmit 24-bit data to host Freescale Semiconductor, Inc... ;**************************************** ORG P:$40 MOVEP MOVEP MOVEP #1,X:PBC #$0C00,X:IPR #0,X:HCR ;Turn on Host Port ;Turn on host interrupt ;Turn off XMT and RCV interrupts MOVE JCLR #0,SR #3,X:HSR,* ;Unmask interrupts ;Wait for HF0 (from host) set to 1 AND X0,A JEQ LOOP MOVEP #$2,X:HCR ;Enable host transmit interrupt JMP * ;Now wait for interrupt Figure 5-34 Main Program - Transmit 24-Bit Data to Host ;*********************************** ;TRANSMIT to Host Interrupt Routine ;************************************ XMT MOVEP MOVEP RTI #$123456,X:HTX #0,X:HCR ;Test value to transmit ;Turn off XMT Interrupt END Figure 5-35 Transmit to HI Routine 5.3.6.3 DMA Data Transfer The DMA mode allows the transfer of 8-, 16- or 24-bit data through the DSP HI under the control of an external DMA controller. The HI provides the pipeline data registers and the synchronization logic between the two asynchronous processor systems. The DSP host exceptions provide cycle-stealing data transfers with the DSP internal or external memory. This technique allows the DSP memory address to be generated using any of the MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 55 Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... DSP addressing modes and modifiers. Queues and circular sample buffers are easily created for DMA transfer regions. The host exceptions can be programmed as high priority fast or long exception service routines. The external DMA controller provides the transfers between the DSP HI registers and the external DMA memory. The external DMA controller must provide the address to the external DMA memory; however, the address of the selected HI register is provided by a DMA address counter in the HI. DMA transfers can only be in one direction at a time; however, the host processor can access any of the registers not in use during the DMA transfer by deasserting HACK and using HEN and HA0-HA2 to transfer data. The host can therefore transfer data in the other direction during the DMA operation using polling techniques. +5 V DMA CONTROLLER DSP56002 HOST INTERFACE 1K HREQ TRANSFER REQUEST INTERNAL ADDRESS COUNTER TRANSFER ACKNOWLEDGE HACK H0 - H7 MEMORY R/W CONTROL ADDRESS DATA Characteristics of Host DMA Mode • The HREQ pin is NOT available for host processor interrupts. • TREQ and RREQ select the direction of DMA transfer. — DMA to DSP56002 — DSP56002 to DMA — Simultaneous bidirectional DMA transfers are not permitted. • Host processor software polled transfers are permitted in the opposite direction of the DMA transfer. • 8-, 16-, or 24-bit transfers are supported. • 16-, or 24-bit transfers reduce the DSP interrupt rate by a factor of 2 or 3, respectively. Figure 5-36 HI Hardware–DMA Mode 5 - 56 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) XFEREQ HREQ DMA CONTROLLER DSP560021 Freescale Semiconductor, Inc... XFERACK HACK 24-BIT TRANSFER (INTERNAL COUNTER) H (01) M (10) L (11) H (01) M (10) L (11) 16-BIT TRANSFER (INTERNAL COUNTER) M (10) L (11) M (10) L (11) M (10) L (11) 8-BIT TRANSFER (INTERNAL COUNTER) L (11) HOST RECEIVE INTERRUPT L (11) L (11) FAST INTERRUPT ROUTINE P:$0020 MOVE X:$FFE8,A P:$0021 MOVE A, Y:(R7)+ L (11) L (11) L (11) READ HRX ;AND PUT INTO Y MEMORY Figure 5-37 DMA Transfer and Host Interrupts 5.3.6.3.1 Host To DSP Internal Processing The following procedure outlines the steps that the HI hardware takes to transfer DMA data from the host data bus to DSP memory (see Figure 5-36 and Figure 5-37). 1. 2. 3. 4. HI asserts the HREQ pin when TXDE=1. DMA controller enables data on H0-H7 and asserts HACK. When HACK is asserted, the HI deasserts HREQ. When the DMA controller deasserts HACK, the data on H0-H7 is latched into the TXH, TXM, TXL registers. 5. If the byte register written was not TXL (i.e., not $7) the DMA address counter internal to the HI increments and HREQ is again asserted. Steps 2-5 are then repeated. 6. If TXL ($7) was written, TXDE will be set to zero and the address counter in the HI will be loaded with the contents of HM1 and HM0. When TXDE=0, the contents of TXH:TXM:TXL are transferred to HRX provided HRDF=0. After the transfer to HRX, TXDE will be set to one, and HREQ will be asserted to start the transfer of another word from external memory to the HI. 7. When the transfer to HRX occurs within the HI, HRDF is set to one. Assuming HRIE=1, a host receive exception will be generated. The exception routine must read the HRX to clear HRDF. Note: The transfer of data from the TXH, TXM, TXL registers to the HRX register auto- MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 57 Freescale Semiconductor, Inc. HOST INTERFACE (HI) MODES 7 Freescale Semiconductor, Inc... $0 0 INIT HM1 HM0 HF1 HF0 0 TREQ RREQ 0 0 Interrupt Mode (DMA Off) 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode RESET CONDITION DMA MODE INTERRUPT MODE (DMA OFF) TREQ RREQ 0 0 0 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) HREQ PIN TREQ RREQ HREQ PIN No Interrupts (Polling) 0 0 No DMA 1 RXDF Request (Interrupt) 0 1 DSP to Host Request (RX) 1 0 XDE Request (Interrupt) 1 0 Host to DSP Request (TX) 1 1 XDF and TXDE Request (Interrupts) 1 1 Undefined (Illegal) 7 $2 HREQ 0 DMA 0 HF3 HF2 TRDY TXDE RXDF 7 X:$FFE9 DMA 0 0 0 HF1 HF0 HCP HTDE HRDF INTERRUPT STATUS REGISTER (ISR) (READ ONLY) HOST STATUS REGISTER (HSR) (READ ONLY) Figure 5-38 Host Bits with TREQ and RREQ matically loads the DMA address counter from the HM1 and HM0 bits in the DMA host to DSP mode. This DMA address is used with the HI to place the received byte in the correct register (TXH, TXM, or TXL). Figure 5-37 shows the differences between 24-, 16-, and 8-bit DMA data transfers. The interrupt rate is three times faster for 8-bit data transfers than for 24-bit transfers. TXL is always loaded last. 5.3.6.3.2 Host to DSP DMA Procedure The following procedure outlines the typical steps that the host processor must take to setup and terminate a host-to-DSP DMA transfer (see Figure 5-39). 5 - 58 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT B 9. TERMINATE DSP DMA MODE BY CLEARING HM1, HM0, AND TREQ. 8. TERMINATE DMA CHANNEL. 5. HOST IS FREE TO PERFORM OTHER TASKS (i.e., DSP TO HOST TRANSFER ON A POLLED BASIS). 3. TELL DSP56002 — WHERE TO STORE DATA (i.e., PROGRAM ADDRESS REGISTER R7). — ENABLE INTERRUPT HRIE (CAN BE DONE WITH A HOST COMMAND). 2. INITIALIZE DSP56002 HOST INTERFACE. — MODE 24 BIT DMA — HOST TO DSP — USE INIT BIT TO: SET TXDE CLEAR HRDF LOAD DMA COUNTER 1. PROGRAM DMA CONTROLLER. — START ADDRESS — BYTE COUNT — TRANSFER DIRECTION — START DMA CHANNEL HOST PROCESSOR TXM TXL 11 TXM TXL 10 11 0 0 HM0 1 HF3 HF1 HF2 HF0 FAST INTERRUPT OR LONG INTERRUPT AVAILABLE FOR HOST COMMAND HOST RECEIVE DATA VECTOR EXCEPTION VECTOR TABLE 7. DMA CONTROLLER INTERRUPTS HOST WHEN TRANSFERS ARE DONE. P:$007E P:$0020 P:$0000 HREQ PIN 0 HCIE DSP56002 4. ASSERT HREQ TO START DMA TRANSFER. 0 HM1 INIT 7 0 1 7 Figure 5-39 Host-to-DSP DMA Procedure TXH 01 • • • TXH 11 10 TXL 10 01 TXH TXM 01 $0 X:$FFE8 6. DMA CONTROLLER PERFORMS WRITES. WRITE ICR DMA CONTROLLER Freescale Semiconductor, Inc... 0 HTIE HRIE 1 0 TREQ RREQ 1 0 HOST CONTROL REGISTER (HCR) INTERRUPT CONTROL REGISTER (ICR) Freescale Semiconductor, Inc. HOST INTERFACE (HI) 5 - 59 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... HOST INTERFACE (HI) 1. Set up the external DMA controller (1) source address, byte count, direction, and other control registers. Enable the DMA controller channel. 2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1), to select the direction (TREQ=1, RREQ=0), and to initialize the channel setting INIT=1 (see Figure 5-38). 3. Initialize the DSP’s destination pointer (3) used in the DMA exception handler (an address register, for example) and set HRIE to enable the HRDF interrupt to the DSP CPU. This procedure can be done with a separate host command exception routine in the DSP. HREQ will be asserted (4) immediately by the HI to begin the DMA transfer. 4. Perform other tasks (5) while the DMA controller transfers data (6) until interrupted by the DMA controller DMA transfer complete interrupt (7). The DSP interrupt control register (ICR), the interrupt status register (ISR), and RXH, RXM, and RXL registers may be accessed at any time by the host processor but the TXH, TXM and TXL registers may not be accessed until the DMA mode is disabled. 5. Terminate the DMA controller channel (8) to disable DMA transfers. 6. Terminate the DSP HI DMA mode (9) in the ICR by clearing the HM1 and HM0 bits and clearing TREQ. The HREQ will be active immediately after initialization is completed (depending on hardware) because the data direction is host to DSP and TXH, TXM, and TXL registers are empty. When the host writes data to TXH, TXM, and TXL, this data will be immediately transferred to HRX. If the DSP is due to work in interrupt mode, HRIE must be enabled. 5.3.6.3.3 DSP to Host Internal Processing The following procedure outlines the steps that the HI hardware takes to transfer DMA data from DSP memory to the host data bus. 1. On the DSP side of the HI, a host transmit exception will be generated when HTDE=1 and HTIE=1. The exception routine must write HTX, thereby setting HTDE=0. 2. If RXDF=0 and HTDE=0, the contents of HTX will be automatically transferred to RXH:RXM:RXL, thereby setting RXDF=1 and HTDE=1. Since HTDE=1 again on the initial transfer, a second host transmit exception will be generated immediately, and HTX will be written, which will clear HTDE again. 3. When RXDF is set to one, the HI’s internal DMA address counter is loaded (from HM1 and HM0) and HREQ is asserted. 4. The DMA controller enables the data from the appropriate byte register onto H0-H7 by asserting HACK. When HACK is asserted, HREQ is deasserted by 5 - 60 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) the HI. 5. The DMA controller latches the data presented on H0-H7 and deasserts HACK. If the byte register read was not RXL (i.e., not $7), the HI’s internal DMA counter increments, and HREQ is again asserted. Steps 3, 4, and 5 are repeated until RXL is read. 6. If RXL was read, RXDF will be set to zero and, since HTDE=0, the contents of HTX will be automatically transferred to RXH:RXM:RXL, and RXFD will be set to one. Steps 3, 4, and 5 are repeated until RXL is read again. Freescale Semiconductor, Inc... Note: The transfer of data from the HTX register to the RXH:RXM:RXL registers automatically loads the DMA address counter from the HM1 and HM0 bits when in the DMA DSP–HOST mode. This DMA address is used within the HI to place the appropriate byte on H0-H7. 5.3.6.3.4 DSP to Host DMA Procedure The following procedure outlines the typical steps that the host processor must take to setup and terminate a DSP-to-host DMA transfer (see Figure 5-40). 1. Set up the DMA controller (1) destination address, byte count, direction, and other control registers. Enable the DMA controller channel. 2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1), the direction (TREQ=0, RREQ=1), and setting INIT=1 (see Figure 5-40 for additional information on these bits). 3. Initialize the DSP’s source pointer (3) used in the DMA exception handler (an address register, for example), and set HTIE to enable the DSP host transmit interrupt. This could be done by the host processor with a host command exception routine. The DSP host transmit exception will be activated immediately after HTIE is set. The DSP CPU will move data to HTX. The HI circuitry will transfer the contents of HTX to RXH:RXM:RXL, setting RXDF which asserts HREQ. Asserting HREQ (4) starts the DMA transfer from RXH, RXM, and RXL to the host processor. 4. Perform other tasks (5) while the DMA controller transfers data (6) until interrupted by the DMA controller DMA complete interrupt (7). The DSP interrupt control register (ICR), the interrupt status register (ISR), and TXH, TXM, and TXL may be accessed at any time by the host processor but the RXH, RXM and RXL registers may not be accessed until the DMA mode is disabled. 5. Terminate the DMA controller channel (8) to disable DMA transfers. 6. Terminate the DSP HI DMA mode (9) in the Interrupt Control Register (ICR) by clearing the HM1 and HM0 bits and clearing RREQ. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 61 5 - 62 For More Information On This Product, Go to: www.freescale.com PORT B 9. TERMINATE DSP DMA MODE BY CLEARING HM1, HM0, AND TREQ. 8. TERMINATE DMA CHANNEL. 5. HOST IS FREE TO PERFORM OTHER TASKS (i.e., DSP TO HOST TRANSFER ON A POLLED BASIS). 3. TELL DSP56002. — SOURCE POINTER ADDRESS — ENABLE HTIE (CAN BE DONE WITH A HOST COMMAND). 2. INITIALIZE DSP56002 HOST INTERFACE. — MODE 24 BIT DMA — HOST TO DSP — USE INIT BIT TO: CLEAR TXDE SET HRDF LOAD DMA COUNTER 1. PROGRAM DMA CONTROLLER. — START ADDRESS — BYTE COUNT — TRANSFER DIRECTION — START DMA CHANNEL HOST PROCESSOR RXL RXH RXM RXL 10 11 01 10 11 RXM RXL 10 11 0 0 HM0 1 HF3 HF1 HF2 HF0 FAST INTERRUPT OR LONG INTERRUPT AVAILABLE FOR HOST COMMAND HOST TRANSMIT DATA VECTOR EXCEPTION VECTOR TABLE 7. DMA CONTROLLER INTERRUPTS HOST WHEN TRANSFERS ARE DONE. P:$007E P:$0022 P:$0000 HREQ 0 HCIE DSP56002 4. ASSERT HREQ TO START DMA TRANSFER. 0 HM1 INIT 7 0 1 7 Figure 5-40 DSP to Host DMA Procedure RXH 01 • • • RXH RXM 01 $0 X:$FFE8 6. DMA CONTROLLER PERFORMS READS. WRITE ICR DMA CONTROLLER Freescale Semiconductor, Inc... 1 HRIE 1 HTIE 0 TREQ RREQ 0 0 HOST CONTROL REGISTER (HCR) INTERRUPT CONTROL REGISTER (ICR) Freescale Semiconductor, Inc. HOST INTERFACE (HI) MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) Freescale Semiconductor, Inc... 5.3.6.4 Example Circuits Figure 5-41, Figure 5-42, and Figure 5-43 illustrate the simplicity of the HI. The MC68HC11 in Figure 5-42 has a multiplexed address and data bus which requires that the address be latched. Although the HACK is not used in this circuit, it is pulled up. All unused input pins should be terminated to prevent erroneous signals. When determining whether a pin is an input, keep in mind that it may change during reset or while changing Port B between general purpose I/O and HI functions. The MC68000 (see Figure 5-42) can use a MOVEP instruction with word and long-word data size to transfer multiple bytes. If an MC68020 or MC68030 is used, dynamic bus sizing can be used to transfer multiple bytes with any instruction. Figure 5-43 is a high level block diagram of a system using a single host to control multiple DSPs. In addition, the DSPs use the SSI to network together the DSPs and multiple codecs. This system, as shown with four DSPs, can process 80 million instructions per +5 V MC68HC11 +5 V IRQ DSP56002 HACK (HOST ACKNOWLEDGE) HREQ (HOST REQUEST) ADDRESS DECODE A8 - A15 HEN E (HOST ENABLE) HR/W (HOST READ/WRITE) R/W A3 - A7 LE ADDRESS LATCH AS A0 - A2 A0/D0 - A7/D7 HA0 - HA2 (HOST ADDRESS) H0 - H7 (HOST DATA) Use LDA and STA for 8-Bit Transfers. Use LDD and STD for 16-Bit Transfers. Figure 5-41 MC68HC11 to DSP56002 Host Interface MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 63 Freescale Semiconductor, Inc. HOST INTERFACE (HI) +5 V MC68000 IPL0 - IPL2 A4 - A23 INTERRUPT ENCODER DSP56002 HREQ ADDRESS DECODE FC0 - FC2 HEN Freescale Semiconductor, Inc... LDS AS INTERRUPT VECTOR DECODE DTACK BERR HACK DTACK TIMING GENERATOR R/W HR/W A1 - A3 HA0 - HA2 D0 - D7 H0 - H7 MC68000 — USE MOVEP for multiple byte transfers. MC68020 or MC68030 — Any Memory references will work due to dynamic bus sizing. Figure 5-42 MC68000 to DSP56002 Host Interface second at 40 MHz and can be easily expanded if more processing power is needed. 5 - 64 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL DATA FRAME SYNC CLOCK FLAG 1 FLAG 0 DATA BUS ADDRESS BUS RD/WR REQ HOST INTERFACE (HI) RX HOST SSI ANALOG INPUT Freescale Semiconductor, Inc... SELECT CODEC DSP56002 ANALOG OUTPUT TX RX HOST SSI SELECT DATA DSP56002 ADDRESS HOST RD/WR REQ TX RX HOST SSI ANALOG INPUT SELECT CODEC DSP56002 ANALOG OUTPUT TX RX HOST SSI SELECT DSP56002 Figure 5-43 Multi-DSP Network Example MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 65 Freescale Semiconductor, Inc. HOST INTERFACE (HI) 5.3.6.5 Host Port Usage Considerations – Host Side Synchronization is a common problem when two asynchronous systems are connected, and careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. The considerations for proper operation are discussed below. Freescale Semiconductor, Inc... 1. Unsynchronized Reading of Receive Byte Registers: When reading receive byte registers, RXH, RXM, or RXL, the host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This guarantees that the data in the receive byte registers will be stable. 2. Overwriting Transmit Byte Registers: The host programmer should not write to the transmit byte registers, TXH, TXM, or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the DSP will read stable data when it reads the HRX register. 3. Synchronization of Status Bits from DSP to Host: HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the HI and read by the host processor. The host can read these status bits very quickly without regard to the clock rate used by the DSP, but there is a chance that the state of the bit could be changing during the read operation. This possible change is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine. However, if the host holds HEN for the minimum assertion time plus x clock cycles (see “Host Port Usage Considerations” in the DSP56002 Technical Data Sheet (DSP56002/D) for the minimum number of cycles), the status data is guaranteed to be stable. The x clock cycles are used to synchronize the HEN signal and block internal updates of the status bits. There is no other minimum HEN assertion time relationship to DSP clocks. There is a minimum HEN deassertion time so that the blocking latch can be updated if the host is in a tight polling loop. This minimum time only applies to reading status bits. The only potential problem with the host processor’s reading of status bits would be its reading HF3 and HF2 as an encoded pair. For example, if the DSP changes HF3 and HF2 from “00” to “11”, there is a small possibility that the host could read the bits during the transition and receive “01” or “10” instead of “11”. If the combination of HF3 and HF2 has significance, the host processor could 5 - 66 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOST INTERFACE (HI) potentially read the wrong combination. Two solutions would be to 1) read the bits twice and check for consensus, or 2) hold HEN access for HEN + x clock cycles so that status bit transitions are stabilized. Freescale Semiconductor, Inc... 4. Overwriting the Host Vector: The host programmer should change the host vector register only when the HC bit is clear. This will guarantee that the DSP interrupt control logic will receive a stable vector. 5. Cancelling a Pending Host Command Exception: The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. The DSP CPU may execute the host exception after the HC bit is cleared because the host processor does not know exactly when the exception will be recognized. This uncertainty in timing is due to differences in synchronization between the host processor and DSP CPU and the uncertainties of pipelined exception processing. For this reason, the HV should not be changed at the same time the HC bit is cleared. However, the HV can be changed when the HC bit is set. 6. When using the HREQ pin for handshaking, wait until HREQ is asserted and then start writing/reading data using the HEN pin or the HACK pin. When not using HREQ for handshaking, poll the INIT bit in the ICR to make sure it is cleared by the hardware (which means the INIT execution is completed). Then, start writing/reading data. If using neither HREQ for handshaking, nor polling the INIT bit, wait at least 6T after negation of HEN that wrote ICR, before writing/reading data. This wait ensures that the INIT is completed, because it needs 3T for synchronization (worst case) plus 3T for executing the INIT. 7. All unused input pins should be terminated. Also, any pin that is temporarily not driven by an output during reset, when reprogramming a port or pin, when a bus is not driven, or at any other time, should be pulled up or down with a resistor. For example, the HEN is capable of reacting to 2-ns noise spikes when it is not terminated. Allowing HACK to float may cause problems even though it is not needed in the circuit. MOTOROLA PORT B For More Information On This Product, Go to: www.freescale.com 5 - 67 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... HOST INTERFACE (HI) 5 - 68 PORT B For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 6 Freescale Semiconductor, Inc... PORT C MOTOROLA For More Information On This Product, Go to: www.freescale.com 6-1 Freescale Semiconductor, Inc. SECTION CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 GENERAL-PURPOSE I/O (PORT C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . 6-11 6.4 SYNCHRONOUS SERIAL INTERFACE (SSI) . . . . . . . . . . . . . . . . . . . . . . 6-76 Freescale Semiconductor, Inc... 6.1 6-2 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION 6.1 INTRODUCTION Freescale Semiconductor, Inc... Port C is a triple-function I/O port with nine pins (see Figure 6-1). Three of the nine pins can be configured as general-purpose I/O or as the serial communication interface (SCI) pins. The other six pins can also be configured as GPIO, or they can be configured as the synchronous serial interface (SSI) pins. When configured as general-purpose I/O, port C can be used for device control. When the pins are configured as serial interfaces, port C provides a convenient connection to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters, and any of several transducers. This section describes all three port C functions as well as examples of how to configure and use each function. DEFAULT FUNCTION ALTERNATE FUNCTION 16 EXTERNAL ADDRESS SWITCH A0 - A15 — D0 - D23 — 24 EXTERNAL DATA SWITCH PS DS X/Y RD WR BN BR BG WT BS PORT A I/0 (47) BUS CONTROL 8 HOST/DMA PARALLEL INTERFACE PORT B I/0 (15) SCI INTERFACE PORT C I/0 (9) SSI INTERFACE — — — — — — — — — — 8 PB0 - PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 H0 - H7 HA0 HA1 HA2 HR/W HEN HREQ HACK or PB14 PC0 RXD PC1 TXD PC2 SCLK PC3 SC0 PC4 SC1 PC5 SC2 PC6 SCK PC7 SRD PC8 STD Figure 6-1 Port C Interface MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6-3 Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) 6.2 GENERAL-PURPOSE I/O (PORT C) When it is configured as GPIO, Port C can be viewed as nine I/O pins (see Figure 6-2), which are controlled by three memory-mapped registers. These registers are the Port C control register (PCC), Port C data direction register (PCDDR), and Port C data register (PCD) (see Figure 6-3). Freescale Semiconductor, Inc... ENABLED BY BITS IN X:$FFE1 P O R T C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 DIRECTION SELECTED BY X:$FFE3 CD0 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 INPUT/OUTPUT DATA REGISTER X:$FFE5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 Figure 6-2 Port C GPIO Control Reset clears PCC and PCDDR to configure Port C as general-purpose I/O with all nine pins as inputs. (External circuitry connected to these pins may need pullups until the pins are configured for operation.) Each Port C pin may be individually programmed as a general-purpose I/O pin or as a dedicated on-chip peripheral pin under software control. Pin selection between general-purpose I/O and SCI or SSI is made by setting the appropriate PCC bit (memory location X:$FFE1) to zero for general-purpose I/O or to one for serial interface. The PCDDR (memory location X:$FFE3) programs each pin corresponding to a bit in the PCD (memory location X:$FFE5) as an input pin (if PCDDR=0) or as an output pin (if PCDDR=1). If a pin is configured as a GPIO input (as shown in Figure 6-4) and the processor reads the PCD, the processor sees the logic level on the pin. If the processor writes to the PCD, the data is latched there, but does not appear on the pin because the buffer is in the high-impedance state. 6-4 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) 23 X:$FFE1 0 0 0 Freescale Semiconductor, Inc... CCx 0 0 0 0 0 0 0 0 0 0 GPIO 1 Serial Interface 0 SSI STD SRD SCK SC2 SC1 SC0 SCI SCLK TXD RXD Function 0 0 0 CC CC CC CC CC CC CC CC CC PORT C CONTROL 8 7 6 5 4 3 2 1 0 REGISTER (PCC) 23 0 PORT C DATA X:$FFE3 0 0 0 0 0 0 0 0 0 0 0 0 CDx 0 0 0 CD CD CD CD CD CD CD CD CD DIRECTION 8 7 6 5 4 3 0 1 0 REGISTER (PCDDR) Data Direction 0 Input 1 Output 23 X:$FFE5 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT C DATA PD PD PD PD PD PD PD PD PD REGISTER (PCD) 8 7 6 5 4 3 2 1 0 NOTE: Hardware and software reset clears PCC and PCDDR. Figure 6-3 Port C GPIO Registers If a pin is configured as a GPIO output and the processor reads the PCD, the processor sees the contents of the PCD rather the logic level on the pin, which allows the PCD to be used as a general purpose 15-bit register. If the processor writes to the PCD, the data is latched there and appears on the pin during the following instruction cycle (see 6.2.2). If a pin is configured as a serial interface (SCI or SSI) pin, the Port C GPIO registers can be used to help in debugging the serial interface. If the PCDDR bit for a given pin is cleared (configured as an input), the PCD will show the logic level on the pin, regardless of whether the serial interface function is using the pin as an input or an output. If the PCDDR is set (configured as an output) for a given serial interface pin, when the processor reads the PCD, it sees the contents of the PCD rather than the logic level on the pin — another case which allows the PCD to act as a general purpose register. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6-5 Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) Port Control Register Bit Data Direction Register Bit 0 0 Pin Function Port Input Pin PIN Freescale Semiconductor, Inc... PORT C DATA (PCD) REGISTER BIT (GPIO POSITION) PORT REGISTERS DATA DIRECTION REGISTER (PCDDR) PORT C CONTROL (PCC) REGISTER BIT (INPUT POSITION) PORT INPUT DATA BIT OUTPUT DATA BIT PERIPHERAL LOGIC DATA DIRECTION BIT INPUT DATA BIT Figure 6-4 Port C I/O Pin Control Logic 6.2.1 Programming General Purpose I/O Port C and all the DSP56002 peripherals are memory mapped (see Figure 6-5). The standard MOVE instruction transfers data between Port C and a register; as a result, performing a memory-to-memory data transfer takes two MOVE instructions and a register. The MOVEP instruction is specifically designed for I/O data transfer as shown in Figure 6-6. Although the MOVEP instruction may take twice as long to execute as a MOVE instruction, only one MOVEP is required for a memory-to-memory data transfer, and MOVEP does not use a temporary register. Using the MOVEP instruction allows a fast interrupt to move data to/from a peripheral to memory and execute one other instruction or to move the data to an absolute address. MOVEP is the only memory-to-memory move instruction; however, one of the operands must be in the top 64 locations of either X: or Y: memory. The bit-oriented instructions which use I/O short addressing (BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, and JSSET) can also be used to address individual bits for faster 6-6 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) : : MOVEP #$0,X:$FFE1 MOVEP #$01F0,X:$FFE3 : : MOVEP #data_out,X:$FFE5 Freescale Semiconductor, Inc... MOVEP X:$FFE0,#data_in ;Select Port C to be general-purpose I/O ;Select pins PC0–PC3 to be inputs ;and pins PC4–PC8 to be outputs ;Put bits 4–8 of “data_out” on pins ;PB4–PB8 bits 0–3 are ignored. ;Put PB0–PB3 in bits 0–3 of “data_in” Figure 6-6 Write/Read Parallel Data with Port C I/O processing. The DSP does not have a hardware data strobe to strobe data out of the GPIO port. If a data strobe is needed, it can be implemented using software to toggle one of the GPIO pins. Figure 6-7 shows the process of programming Port C as general-purpose I/O. Normally, it is not good programming practice to activate a peripheral before programming it. However, reset activates the Port C general-purpose I/O as all inputs, and the alternative is to configure the port as an SCI and/or SSI, which may not be desirable. In this case, it is probably better to insure that Port C is initially configured for general-purpose I/O and then configure the data direction and data registers. It may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal. The order of steps 1, 2, and 3 in Figure 6-7 is optional and can be changed as needed. 6.2.2 Port C General Purpose I/O Timing Parallel data written to Port C is delayed by one instruction cycle. For example, the following instruction: MOVE DATA9,X:PORTC DATA24,Y:EXTERN 1. writes nine bits of data to the Port C register, but the output pins do not change until the following instruction cycle 2. writes 24 bits of data to the external Y memory, which appears on Port A during T2 and T3 of the current instruction As a result, if it is necessary to synchronize the Port A and Port C outputs, two instructions must be used: MOVE NOP MOTOROLA DATA9,X:PORTC DATA24,Y:EXTERN PORT C For More Information On This Product, Go to: www.freescale.com 6-7 Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) Freescale Semiconductor, Inc... 23 16 15 8 7 0 X:$FFFF INTERRUPT PRIORITY REGISTER (IPR) X:$FFFE PORT A — BUS CONTROL REGISTER (BCR) X:$FFFD PLL CONTROL REGISTER X:$FFFC OnCE GDB REGISTER X:$FFFB RESERVED X:$FFFA RESERVED X:$FFF9 RESERVED X:$FFF8 RESERVED X:$FFF7 RESERVED X:$FFF6 SCI HI - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF5 SCI MID - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF4 SCI LOW - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF3 SCI TRANSMIT DATA ADDRESS REGISTER (STXA) X:$FFF2 SCI CONTROL REGISTER (SCCR) X:$FFF1 SCI INTERFACE STATUS REGISTER (SSR) X:$FFF0 SCI INTERFACE CONTROL REGISTER (SCR) X:$FFEF SSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX) X:$FFEE SSI STATUS/TIME SLOT REGISTER (SSISR/TSR) X:$FFED SSI CONTROL REGISTER B (CRB) X:$FFEC SSI CONTROL REGISTER A (CRA) X:$FFEB HOST RECEIVE/TRANSMIT REGISTER (HRX/HTX) X:$FFEA RESERVED X:$FFE9 HOST STATUS REGISTER (HSR) 6-8 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) STEP 1. SELECT EACH PIN TO BE GENERAL-PURPOSE I/O OR AN ON-CHIP PERIPHERAL PIN: CCx = 0 GENERAL- PURPOSE I/O CCx = 1 ON-CHIP PERIPHERAL 8 Freescale Semiconductor, Inc... X:$FFE1 0 CC CC CC CC CC CC CC CC CC 8 7 6 5 4 3 2 1 0 PORT C CONTROL REGISTER (PCC) STEP 2. SET EACH GENERAL - PURPOSE I/O PIN (SELECTED ABOVE) AS INPUT OR OUTPUT: CDx = 0 INPUT PIN OR CDx = 1 OUTPUT PIN 8 0 CD CD CD CD CD CD CD CD CD X:$FFE3 8 7 6 5 4 3 2 1 0 PORT C DATA DIRECTION REGISTER (PCDDR) STEP 3. READ/WRITE GENERAL - PURPOSE I/O PINS: PCx = OUTPUT DATA IF SELECTED FOR GENERAL - PURPOSE I/O AND OUTPUT IN STEPS 1 AND 2. OR PCx = INPUT DATA IF SELECTED FOR GENERAL - PURPOSE I/O AND INPUT IN STEPS 1 AND 2. 8 0 PC PC PC PC PC PC PC PC PC X:$FFE5 8 7 6 5 4 3 2 1 0 PORT C DATA REGISTER (PCD) Figure 6-7 I/O Port C Configuration The NOP can be replaced by any instruction that allows parallel moves. Inserting one or more “MOVE DATA15,X:PORTC DATA24,Y:EXTERN” instructions between the first and second instruction produces an external 33-bit write each instruction cycle with only one instruction cycle lost in setup time: MOVE MOVE MOVE : : MOVE NOP DATA9,X:PORTC DATA9,X:PORTC DATA9,X:PORTC DATA9,X:PORTC DATA24,Y:EXTERN DATA24,Y:EXTERN DATA24,Y:EXTERN DATA24,Y:EXTERN One application of this technique is to create an extended address for Port A by concatenating the Port A address bits (instead of data bits) to the Port C general-purpose output bits. The Port C general-purpose I/O register would then work as a base address register, allowing the address space to be extended from 64K words (16 bits) to 33.5 million words MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6-9 Freescale Semiconductor, Inc. GENERAL-PURPOSE I/O (PORT C) (16 bits+ 9 bits=25 bits). Freescale Semiconductor, Inc... Port C uses the DSP central processing unit (CPU) four-phase clock for its operation. Therefore, if wait states are inserted in the DSP CPU timing, they also affect Port C timing. As a result, Port A and Port C in the previous synchronization example will always stay synchronized, regardless of how many wait states are used. 6 - 10 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6.3 SERIAL COMMUNICATION INTERFACE (SCI) The SCI provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. The communication can be TTL-level signals or, with additional logic, RS232C, RS422, etc. Freescale Semiconductor, Inc... This interface uses three dedicated pins: transmit data (TXD), receive data (RXD), and SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and protocols as well as high-speed (up to 5 Mbps for a 40-MHz clock) synchronous data transmission. The asynchronous protocols include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. The SCI consists of separate transmit and receive sections whose operations can be asynchronous with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks. An enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general-purpose timer when it is not being used by the SCI peripheral or when the interrupt timing is the same as that used by the SCI. The following is a short list of SCI features: • Three-Pin Interface: TXD – Transmit Data RXD – Receive Data SCLK – Serial Clock • 625 Kbps NRZ Asynchronous Communications Interface (40-MHz System Clock) • 5.0 Mbps Synchronous Serial Mode (40-MHz System Clock) • Multidrop Mode for Multiprocessor Systems: Two Wakeup Modes: Idle Line and Address Bit Wired-OR Mode • On-Chip or External Baud Rate Generation/Interrupt Timer • Four Interrupt Priority Levels • Fast or Long Interrupts 6.3.1 SCI I/O Pins The three SCI pins can be configured as either general-purpose I/O or as a specific SCI pin. Each pin is independent of the other two, so that if only TXD is needed, RXD and SCLK can be programmed for general-purpose I/O. However, at least one of the three pins must be selected as an SCI pin to release the SCI from reset. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 11 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) SCI interrupts may be enabled by programming the SCI control registers before any of the SCI pins are programmed as SCI functions. In this case, only one transmit interrupt can be generated because the transmit data register is empty. The timer and timer interrupt will operate as they do when one or more of the SCI pins is programmed as an SCI function. Freescale Semiconductor, Inc... 6.3.1.1 Receive Data (RXD) This input receives byte-oriented serial data and transfers the data to the SCI receive shift register. Asynchronous input data is sampled on the positive edge of the receive clock (1 × SCLK) if SCKP equals zero. See the DSP56002 Technical Data Sheet for detailed timing information. RXD may be programmed as a general-purpose I/O pin (PC0) when the SCI RXD function is not being used. 6.3.1.2 Transmit Data (TXD) This output transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the asynchronous transmit clock (SCLK) if SCKP equals zero. This output is stable on the positive edge of the transmit clock. See the DSP56002 Technical Data Sheet for detailed timing information. TXD may be programmed as a general-purpose I/O pin (PC1) when the SCI TXD function is not being used. 6.3.1.3 SCI Serial Clock (SCLK) This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode and from which data is transferred in the synchronous mode. SCLK may be programmed as a general-purpose I/O pin (PC2) when the SCI SCLK function is not being used. This pin may be programmed as PC2 when data is being transmitted on TXD since, in the asynchronous mode, the clock need not be transmitted. There is no connection between programming the PC2 pin as SCLK and data coming out the TXD pin because SCLK is independent of SCI data I/O. 6.3.2 SCI Programming Model The resources available in the SCI are described before discussing specific examples of how the SCI is used. The registers comprising the SCI are shown in Figure 6-8 and Figure 6-9. These registers are the SCI control register (SCR), SCI status register (SSR), SCI clock control register (SCCR), SCI receive data registers (SRX), SCI transmit data registers (STX), and the SCI transmit data address register (STXA). The SCI programming model can be viewed as three types of registers: 1) control – SCR and SCCR in Figure 6-8; 2) status – SSR in Figure 6-8; and 3) data transfer – SRX, STX, and STXA in Figure 6-9. The following paragraphs describe each bit in the programming model. 6 - 12 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA 0 16 14 STIR (0) 15 SCKP (0) For More Information On This Product, Go to: www.freescale.com PORT C 0 16 14 RCM (0) 15 TCM (0) SCP (0) 13 COD (0) 12 TIE (0) TMIE (0) 0 12 13 CD11 (0) 11 RIE (0) 11 CD10 (0) 10 ILIE (0) 10 CD9 (0) 9 TE (0) 9 CD8 (0) 8 RE (0) 8 8 CD6 (0) CD5 (0) 5 PE (0) 5 WAKE (0) 5 4 CD4 (0) 4 OR (0) 4 SBK (0) CLOCK DIVIDER BITS CD7 (0) 6 FE (0) R8 (0) 7 6 RWU (0) 6 7 WOMS (0) 7 2 CD3 (0) 3 IDLE (0) 3 CD2 (0) 2 RDRF (0) 2 SSFTD WDS2 (0) (0) 3 0 CD1 (0) 1 TRNE (1) 0 SCI STATUS REGISTER (SSR) (READ ONLY) WORD SELECT BITS SCI SHIFT DIRECTION SEND BREAK WAKEUP MODE SELECT RECEIVER WAKEUP ENABLE WIRED - OR MODE SELECT RECEIVER ENABLE SCI CONTROL REGISTER (SCR) (READ/WRITE) CD0 (0) 0 SCI CLOCK CONTROL REGISTER (SCCR) (READ/WRITE) TRANSMITTER EMPTY TRANSMITTER DATA REGISTER EMPTY RECEIVE DATA REGISTER FULL IDLE LINE FLAG TDRE (1) 1 WDS1 WDS0 (0) (0) 1 Figure 6-8 SCI Programming Model – Control and Status Registers NOTE: The number in parentheses is the condition of the bit after hardware reset. TRANSMIT CLOCK SOURCE BIT RECEIVE CLOCK SOURCE BIT CLOCK PRESCALER CLOCK OUTPUT DIVIDER X:$FFF2 23 RECEIVED BIT 8 FRAMING ERROR FLAG PARITY ERROR FLAG OVERRUN ERROR FLAG X:$FFF1 23 SCI CLOCK POLARITY TIMER INTERRUPT RATE TIMER INTERRUPT ENABLE TRANSMIT INTERRUPT ENABLE RECEIVE INTERRUPT ENABLE IDLE LINE INTERRUPT ENABLE TRANSMITTER ENABLE X:$FFF0 23 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6 - 13 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 23 16 15 8 7 0 SRX X:$FFF6 SCI RECIEVE DATA REGISTER HIGH (READ ONLY) SRX X:$FFF5 SCI RECIEVE DATA REGISTER MID (READ ONLY) SRX X:$FFF4 SCI RECEIVE DATA REGISTER LOW (READ ONLY) SCI RECEIVE DATA SHIFT REGISTER RXD Freescale Semiconductor, Inc... NOTE: SRX is the same register decoded at three different addresses. (a) Receive Data Register 23 16 15 8 7 0 STX X:$FFF6 SCI TRANSMIT DATA REGISTER HIG (WRITE ONLY) STX X:$FFF5 SCI TRANSMIT DATA REGISTER MID (WRITE ONLY) STX X:$FFF4 SCI TRANSMIT DATA REGISTER LOW (WRITE ONLY) SCI TRANSMITDATA SHIFT REGISTER 23 16 15 TXD 8 7 0 X:$FFF3 STXA SCI TRANSMITDATA ADDRESS REGISTER (WRITE ONLY) NOTES: 1. Bytes are masked on the fly. 2. STX is the same register decoded at three different addresses. (b) Transmit Data Register Figure 6-9 SCI Programming Model 6.3.2.1 SCI Control Register (SCR) The SCR is a 16-bit read/write register that controls the serial interface operation. Each bit is described in the following paragraphs. 6.3.2.1.1 SCR Word Select (WDS0, WDS1, WDS2) Bits 0, 1, and 2 The three word-select bits (WDS0, WDS1, WDS2) select the format of the transmit and receive data. The formats include three asynchronous, one multidrop asynchronous mode, and an 8-bit synchronous (shift register) mode. The asynchronous modes are compatible with most UART-type serial devices and support standard RS232C communication links. 6 - 14 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) The multidrop asynchronous modes are compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. The synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. A gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0 accomplishes data synchronization. The word formats are shown in Table 6-1 (also see Figure 6-10 (a) and (b)). Freescale Semiconductor, Inc... Table 6-1 Word Formats WDS2 WDS1 WDS0 Word Formats 0 0 0 8-Bit Synchronous Data (shift register mode) 0 0 1 Reserved 0 1 0 10-Bit Asynchronous (1 start, 8 data, 1 stop) 0 1 1 Reserved 1 0 0 11-Bit Asynchronous (1 start, 8 data, 1 even parity, 1 stop) 1 0 1 11-Bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 1 1 0 11-Bit Multidrop (1 start, 8 data, 1 data type, 1 stop) 1 1 1 Reserved When odd parity is selected, the transmitter will count the number of bits in the data word. If the total is not an odd number, the parity bit is made equal to one and thus produces an odd number. If the receiver counts an even number of ones, an error in transmission has occurred. When even parity is selected, an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred. The word-select bits are cleared by hardware and software reset. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 15 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MODE 0 X:$FFF0 2 1 0 0 0 0 WDS2 WDS1 WDS0 8-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE) TX (SSFTD = 0) D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 OR DATA TYPE ONE BYTE FROM SHIFT REGISTER MODE 2 Freescale Semiconductor, Inc... X:$FFF0 2 1 0 0 1 0 WDS2 WDS1 WDS0 TX (SSFTD = 0) 10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP) START BIT D0 D1 D2 D3 D4 D5 STOP BIT MODE 4 X:$FFF0 2 1 1 0 0 WDS2 WDS1 WDS0 TX (SSFTD = 0) 0 11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 EVEN PARITY, 1 STOP) START BIT D0 D1 D2 D3 D4 D5 D6 D7 OR DATA TYPE EVEN PARITY STOP BIT ODD PARITY STOP BIT MODE 5 2 X:$FFF0 1 0 1 0 1 WDS2 WDS1 WDS0 TX (SSFTD = 0) 11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 ODD PARITY, 1 STOP) START BIT D0 D1 D2 D3 D4 D5 D6 D7 OR DATA TYPE MODE 6 2 X:$FFF0 1 0 1 1 0 WDS2 WDS1 WDS0 TX (SSFTD = 0) START BIT 11-BIT ASYNCHRONOUS MULTIDROP (1 START, 8 DATA, 1 DATA TYPE, 1 STOP) D0 D1 D2 D3 D4 D5 D6 D7 DATA TYPE STOP BIT Data Type: 1 = Address Byte 0 = Data Byte NOTES: 1. Modes1, 3, and 7 are reserved. 2. D0 =LSB;D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0 or MSB first if SSFTD = 1. (a) SSFTD = 0 Figure 6-10 Serial Formats (Sheet 1 of 2) 6 - 16 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MODE 0 X:$FFF0 2 1 0 0 0 0 WDS2 WDS1 WDS0 8-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE) TX (SSFTD = 1) D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 ONE BYTE FROM SHIFT REGISTER MODE 2 Freescale Semiconductor, Inc... X:$FFF0 2 1 0 0 1 0 WDS2 WDS1 WDS0 TX (SSFTD = 1) START BIT 10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP) D7 OR DATA TYPE D6 D5 D4 D3 D2 STOP BIT MODE 4 X:$FFF0 2 1 1 0 0 WDS2 WDS1 WDS0 TX (SSFTD = 1) 0 START BIT 11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 EVEN PARITY, 1 STOP) D7 OR DATA TYPE D6 D5 D4 D3 D2 D1 D0 EVEN PARITY STOP BIT ODD PARITY STOP BIT MODE 5 2 X:$FFF0 1 0 1 0 1 WDS2 WDS1 WDS0 TX (SSFTD = 1) START BIT 11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 ODD PARITY, 1 STOP) D7 OR DATA TYPE D6 D5 D4 D3 D2 D1 D0 MODE 6 2 X:$FFF0 1 0 1 1 0 WDS2 WDS1 WDS0 TX (SSFTD = 1) START BIT 11-BIT ASYNCHRONOUS MULTIDROP (1 START, 8 DATA, 1 DATA TYPE, 1 STOP) DATA TYPE D7 D6 D5 D4 D3 D2 D1 D0 STOP BIT Data Type: 1 = Address Byte 0 = Data Byte NOTES: 1. Modes 1, 3, and 7 are reserved. 2. D0 = LSB;D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0 or MSB first if SSFTD = 1. (b) SSFTD = 1 Figure 6-10 Serial Formats (Sheet 2 of 2) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 17 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... 6.3.2.1.2 SCR SCI Shift Direction (SSFTD) Bit 3 The SCI data shift registers can be programmed to shift data in/out either LSB first if SSFTD equals zero, or MSB first if SSFTD equals one. The parity and data type bits do not change position and remain adjacent to the stop bit. SSFTD is cleared by hardware and software reset. 6.3.2.1.3 SCR Send Break (SBK) Bit 4 A break is an all-zero word frame – a start bit zero, a character of all zeros (including any parity), and a stop bit zero: i.e., 10 or 11 zeros depending on the WDS mode selected. If SBK is set and then cleared, the transmitter completes transmission of any data, sends 10 or 11 zeros, and reverts to idle or sending data. If SBK remains set, the transmitter will continually send whole frames of zeros (10 or 11 bits with no stop bit). At the completion of the break code, the transmitter sends at least one high bit before transmitting any data to guarantee recognition of a valid start bit. Break can be used to signal an unusual condition, message, etc. by forcing a frame error, which is caused by a missing stop bit. Hardware and software reset clear SBK. 6.3.2.1.4 SCR Wakeup Mode Select (WAKE) Bit 5 When WAKE equals zero, an idle line wakeup is selected. In the idle line wakeup mode, the SCI receiver is re-enabled by an idle string of at least 10 or 11 (depending on WDS mode) consecutive ones. The transmitter’s software must provide this idle string between consecutive messages. The idle string cannot occur within a valid message because each word frame contains a start bit that is a zero. When WAKE equals one, an address bit wakeup is selected. In the address bit wakeup mode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit received in a character (frame) is one. The ninth data bit is the address bit (R8) in the 11-bit multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asynchronous with parity modes. Thus, the received character is an address that has to be processed by all sleeping processors – i.e., each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. WAKE is cleared by hardware and software reset. 6.3.2.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6 When RWU equals one and the SCI is in an asynchronous mode, the wakeup function is enabled – i.e., the SCI is put to sleep waiting for a reason (defined by the WAKE bit) to wakeup. In the sleeping state, all receive flags, except IDLE, and interrupts are disabled. When the receiver wakes up, this bit is cleared by the wakeup hardware. The programmer may also clear the RWU bit to wake up the receiver. 6 - 18 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) RWU can be used by the programmer to ignore messages that are for other devices on a multidrop serial network. Wakeup on idle line (WAKE=0) or wakeup on address bit (WAKE=1) must be chosen. 1. When WAKE equals zero and RWU equals one, the receiver will not respond to data on the data line until an idle line is detected. Freescale Semiconductor, Inc... 2. When WAKE equals one and RWU equals one, the receiver will not respond to data on the data line until a data byte with bit 9 equal to one is detected. When the receiver wakes up, the RWU bit is cleared, and the first byte of data is received. If interrupts are enabled, the CPU will be interrupted, and the interrupt routine will read the message header to determine if the message is intended for this DSP. 1. If the message is for this DSP, the message will be received, and RWU will again be set to one to wait for the next message. 2. If the message is not for this DSP, the DSP will immediately set RWU to one. Setting RWU to one causes the DSP to ignore the remainder of the message and wait for the next message. RWU is cleared by hardware and software reset. RWU is a don’t care in the synchronous mode. 6.3.2.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7 When the WOMS bit is set, the SCI TXD driver is programmed to function as an opendrain output and may be wired together with other TXD pins in an appropriate bus configuration such as a master-slave multidrop configuration. An external pullup resistor is required on the bus. When the WOMS is cleared, the TXD pin uses an active internal pullup. This bit is cleared by hardware and software reset. 6.3.2.1.7 SCR Receiver Enable (RE) Bit 8 When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and data transfer is inhibited to the receive data register (SRX) from the receive shift register. If RE is cleared while a character is being received, the reception of the character will be completed before the receiver is disabled. RE does not inhibit RDRF or receive interrupts. RE is cleared by a hardware and software reset. 6.3.2.1.8 SCR Transmitter Enable (TE) Bit 9 When TE is set, the transmitter is enabled. When TE is cleared, the transmitter will complete transmission of data in the SCI transmit data shift register; then the serial output is MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 19 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) forced high (idle). Data present in the SCI transmit data register (STX) will not be transmitted. STX may be written and TDRE will be cleared, but the data will not be transferred into the shift register. TE does not inhibit TDRE or transmit interrupts. TE is cleared by a hardware and software reset. Freescale Semiconductor, Inc... Setting TE will cause the transmitter to send a preamble of 10 or 11 consecutive ones (depending on WDS). This procedure gives the programmer a convenient way to ensure that the line goes idle before starting a new message. To force this separation of messages by the minimum idle line time, the following sequence is recommended: 1. Write the last byte of the first message to STX 2. Wait for TDRE to go high, indicating the last byte has been transferred to the transmit shift register 3. Clear TE and set TE back to one. This queues an idle line preamble to immediately follow the transmission of the last character of the message (including the stop bit) 4. Write the first byte of the second message to STX In this sequence, if the first byte of the second message is not transferred to the STX prior to the finish of the preamble transmission, then the transmit data line will simply mark idle until STX is finally written. 6.3.2.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10 When ILIE is set, the SCI interrupt occurs when IDLE is set. When ILIE is clear, the IDLE interrupt is disabled. ILIE is cleared by hardware and software reset. An internal flag, the shift register idle interrupt (SRIINT) flag, is the interrupt request to the interrupt controller. SRIINT is not directly accessible to the user. When a valid start bit has been received, an idle interrupt will be generated if both IDLE (SCI Status Register bit 3) and ILIE equals one. The idle interrupt acknowledge from the interrupt controller clears this interrupt request. The idle interrupt will not be asserted again until at least one character has been received. The result is as follows: 1. The IDLE bit shows the real status of the receive line at all times. 2. Idle interrupt is generated once for each idle state, no matter how long the idle state lasts. 6 - 20 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6.3.2.1.10 SCR SCI Receive Interrupt Enable (RIE) Bit 11 The RIE bit is used to enable the SCI receive data interrupt. If RIE is cleared, receive interrupts are disabled, and the RDRF bit in the SCI status register must be polled to determine if the receive data register is full. If both RIE and RDRF are set, the SCI will request an SCI receive data interrupt from the interrupt controller. One of two possible receive data interrupts will be requested: Freescale Semiconductor, Inc... 1. Receive without exception will be requested if PE, FE, and OR are all clear (i.e., a normal received character). 2. Receive with exception will be requested if PE, FE, and OR are not all clear (i.e., a received character with an error condition). RIE is cleared by hardware and software reset. 6.3.2.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12 The TIE bit is used to enable the SCI transmit data interrupt. If TIE is cleared, transmit data interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI status register must be polled to determine if the transmit data register is empty. If both TIE and TDRE are set, the SCI will request an SCI transmit data interrupt from the interrupt controller. TIE is cleared by hardware and software reset. 6.3.2.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13 The TMIE bit is used to enable the SCI timer interrupt. If TMIE is set (enabled), the timer interrupt requests will be made to the interrupt controller at the rate set by the SCI clock register. The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller. This feature allows DSP programmers to use the SCI baud clock generator as a simple periodic interrupt generator if the SCI is not in use, if external clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The SCI internal clock is divided by 16 (to match the 1 × SCI baud rate) for timer interrupt generation. This timer does not require that any SCI pins be configured for SCI use to operate. TMIE is cleared by hardware and software reset. 6.3.2.1.13 SCR SCI Timer Interrupt Rate (STIR) Bit 14 This bit controls a divide by 32 in the SCI Timer interrupt generator. When this bit is cleared, the divide by 32 is inserted in the chain. When the bit is set, the divide by 32 is bypassed, thereby increasing the timer resolution by 32 times. This bit is cleared by hardware and software reset. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 21 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) 6.3.2.1.14 SCR SCI Clock Polarity (SCKP) Bit 15 The clock polarity, sourced or received on the clock pin (SCLK), can be inverted using this bit, eliminating the need for an external inverter. When bit 15 equals zero, the clock polarity is positive; when bit 15 equals one, the clock polarity is negative. In the synchronous mode, positive polarity means that the clock is normally positive and transitions negative during data valid; whereas, negative polarity means that the clock is normally negative and transitions positive during valid data. In the asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid; negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid. SCKP is cleared on hardware and software reset. 6.3.2.2 SCI Status Register (SSR) The SSR is an 8-bit read-only register used by the DSP CPU to determine the status of the SCI. When the SSR is read onto the internal data bus, the register contents occupy the low-order byte of the data bus and all high-order portions are zero filled. The status bits are described in the following paragraphs. 6.3.2.2.1 SSR Transmitter Empty (TRNE) Bit 0 The TRNE flag is set when both the transmit shift register and data register are empty to indicate that there is no data in the transmitter. When TRNE is set, data written to one of the three STX locations or to the STXA will be transferred to the transmit shift register and be the first data transmitted. TRNE is cleared when TDRE is cleared by writing data into the transmit data register (STX) or the transmit data address register (STXA), or when an idle, preamble, or break is transmitted. The purpose of this bit is to indicate that the transmitter is empty; therefore, the data written to STX or STXA will be transmitted next – i.e., there is not a word in the transmit shift register presently being transmitted. This procedure is useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set by the hardware, software, SCI individual, and stop reset. 6.3.2.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1 The TDRE bit is set when the SCI transmit data register is empty. When TDRE is set, new data may be written to one of the SCI transmit data registers (STX) or transmit data address register (STXA). TDRE is cleared when the SCI transmit data register is written. TDRE is set by the hardware, software, SCI individual, and stop reset. In the SCI synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5 serial clock cycles between the time that STX is written until TDRE is set, indicating the data has been transferred from the STX to the transmit shift register. There is a two to four serial clock cycle delay between writing STX and loading the transmit shift register; 6 - 22 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) in addition, TDRE is set in the middle of transmitting the second bit. When using an external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE will not be set until the middle of the second bit transmitted after the external clock starts. Gating the external clock off after the first bit has been transmitted will delay TDRE indefinitely. Freescale Semiconductor, Inc... In the SCI asynchronous mode, the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the transmit shift register nor when the word first begins to be shifted out. TDRE is set two cycles of the 16× clock after the start bit – i.e., two 16× clock cycles into to transmission time of the first data bit. 6.3.2.2.3 SSR Receive Data Register Full (RDRF) Bit 2 The RDRF bit is set when a valid character is transferred to the SCI receive data register from the SCI receive shift register. RDRF is cleared when the SCI receive data register is read or by the hardware, software, SCI individual, and stop reset. 6.3.2.2.4 SSR Idle Line Flag (IDLE) Bit 3 IDLE is set when 10 (or 11) consecutive ones are received. IDLE is cleared by a start-bit detection. The IDLE status bit represents the status of the receive line. The transition of IDLE from zero to one can cause an IDLE interrupt (ILIE). IDLE is cleared by the hardware, software, SCI individual, and stop reset. 6.3.2.2.5 SSR Overrun Error Flag (OR) Bit 4 The OR flag is set when a byte is ready to be transferred from the receive shift register to the receive data register (SRX) that is already full (RDRF=1). The receive shift register data is not transferred to the SRX. The OR flag indicates that character(s) in the receive data stream may have been lost. The only valid data is located in the SRX. OR is cleared when the SCI status register is read, followed by a read of SRX. The OR bit clears the FE and PE bits – i.e., overrun error has higher priority than FE or PE. OR is cleared by the hardware, software, SCI individual, and stop reset. 6.3.2.2.6 SSR Parity Error (PE) Bit 5 In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has been detected in the received character. It is set simultaneously with RDRF for the byte which contains the parity error – i.e., when the received word is transferred to the SRX. If PE is set, it does not inhibit further data transfer into the SRX. PE is cleared when the SCI status register is read, followed by a read of SRX. PE is also cleared by the hardware, software, SCI individual, or stop reset. In the 10-bit asynchronous mode, the 11-bit multidrop mode, MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 23 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... and the 8-bit synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver will only recognize the overrun error. 6.3.2.2.7 SSR Framing Error Flag (FE) Bit 6 The FE bit is set in the asynchronous modes when no stop bit is detected in the data string received. FE and RDRE are set simultaneously – i.e., when the received word is transferred to the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is cleared. FE is cleared when the SCI status register is read followed by reading the SRX. The hardware, software, SCI individual, and stop reset also clear FE. In the 8-bit synchronous mode, FE is always cleared. If the byte received causes both framing and overrun errors, the SCI receiver will only recognize the overrun error. 6.3.2.2.8 SSR Received Bit 8 Address (R8) Bit 7 In the 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the received byte is an address or data. R8 is not affected by reading the SRX or status register. The hardware, software, SCI individual, and stop reset clear R8. 6.3.2.3 SCI Clock Control Register (SCCR) The SCCR is a 16-bit read/write register which controls the selection of the clock modes and baud rates for the transmit and receive sections of the SCI interface. The control bits are described in the following paragraphs. The SCCR is cleared by hardware reset. The basic points of the clock generator are as follows: 1. The SCI core always uses a 16 × internal clock in the asynchronous modes and always uses a 2 × internal clock in the synchronous mode. The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4. With a 40-MHz crystal, this gives a maximum data rate of 625 Kbps for asynchonous data and 5 Mbps for synchronous data. These maximum rates are the same for internally or externally supplied clocks. 2. The 16 × clock is necessary for the asynchronous modes to synchronize the SCI to the incoming data (see Figure 6-11). 3. For the asynchronous modes, the user must provide a 16 × clock if he wishes to use an external baud rate generator (i.e., SCLK input). 4. For the asynchronous modes, the user may select either 1 × or 16 × for the output clock when using internal TX and RX clocks (TCM=0 and RCM=0). 6 - 24 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) 5. The transmit data on the TXD pin changes on the negative edge of the 1 × serial clock and is stable on the positive edge (SCKP=0). For SCKP equals one, the data changes on the positive edge and is stable on the negative edge. 6. The receive data on the RXD pin is sampled on the positive edge (if SCKP=0) or on the negative edge (if SCKP=1) of the 1 × serial clock. 7. For the asynchronous mode, the output clock is continuous. 8. For the synchronous mode, a 1 × clock is used for the output or input baud rate. The maximum 1 × clock is the crystal frequency divided by 8. 9. For the synchronous mode, the clock is gated. 10. For both the asynchronous and synchronous modes, the transmitter and receiver are synchronous with each other. 6.3.2.3.1 SCCR Clock Divider (CD11–CD0) Bits 11–0 The clock divider bits (CD11–CD0) are used to preset a 12-bit counter, which is decremented at the Icyc rate (crystal frequency divided by 2). The counter is not accessible to the user. When the counter reaches zero, it is reloaded from the clock divider bits. Thus, a value of 0000 0000 0000 in CD11–CD0 produces the maximum rate of Icyc, and a value of 0000 0000 0001 produces a rate of Icyc/2. The lowest rate available is Icyc/4096. Figure 6-12 and Figure 6-35 show the clock dividers. Bits CD11–CD0 are cleared by hardware and software reset. SELECT 8-OR 9-BIT WORDS 0 IDLE LINE RX, TX DATA (SSFTD = 0) 1 2 3 4 5 6 7 START 8 STOP START x1 CLOCK x16 CLOCK (SCKP = 0) Figure 6-11 16 x Serial Clock MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 25 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6.3.2.3.2 SCCR Clock Out Divider (COD) Bit 12 Figure 6-12 and Figure 6-35 show the clock divider circuit. The output divider is controlled by COD and the SCI mode. If the SCI mode is synchronous, the output divider is fixed at divide by 2; if the SCI mode is asynchronous, and Freescale Semiconductor, Inc... 1. If COD equals zero and SCLK is an output (i.e., TCM and RCM=0), the SCI clock is divided by 16 before being output to the SCLK pin; thus, the SCLK output is a 1 × clock 2. If COD equals one and SCLK is an output, the SCI clock is fed directly out to the SCLK pin; thus, the SCLK output is a 16 × baud clock The COD bit is cleared by hardware and software reset. 6.3.2.3.3 SCCR SCI Clock Prescaler (SCP) Bit 13 The SCI SCP bit selects a divide by 1 (SCP=0) or divide by 8 (SCP=1) prescaler for the clock divider. The output of the prescaler is further divided by 2 to form the SCI clock. Hardware and software reset clear SCP. Figure 6-12 and Figure 6-35 show the clock divider diagram. 6.3.2.3.4 SCCR Receive Clock Mode Source Bit (RCM) Bit 14 RCM selects internal or external clock for the receiver (see Figure 6-35). RCM equals zero selects the internal clock; RCM equals one selects the external clock from the SCLK pin. Hardware and software reset clear RCM. 6.3.2.3.5 SCCR Transmit Clock Source Bit (TCM) Bit 15 The TCM bit selects internal or external clock for the transmitter (see Figure 6-35). TCM equals zero selects the internal clock; TCM equals one selects the external clock from the SCLK pin. Hardware and software reset clear TCM. 6.3.2.4 SCI Data Registers The SCI data registers are divided into two groups: receive and transmit. There are two receive registers – a receive data register (SRX) and a serial-to-parallel receive shift register. There are also two transmit registers – a transmit data register (called either STX or STXA) and a parallel-to-serial transmit shift register. 6.3.2.4.1 SCI Receive Registers Data words received on the RXD pin are shifted into the SCI receive shift register. When the complete word has been received, the data portion of the word is transferred to the byte-wide SRX. This process converts the serial data to parallel data and provides double 6 - 26 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) buffering. Double buffering provides flexibility and increased throughput since the programmer can save the previous word while the current word is being received. Freescale Semiconductor, Inc... The SRX can be read at three locations: X:$FFF4, X:$FFF5, and X:$FFF6 (see Figure 6-13). When location X:$FFF4 is read, the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are written as zeros. Similarly, when X:$FFF5 is read, the contents of SRX are placed in the middle byte of the bus, and when X:$FFF6 is read, the contents of SRX are placed in the high byte with the remaining bits zeroed. Mapping SRX as described allows three bytes to be efficiently packed into TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous/Asynchronous 0 1 Internal External Input Asynchronous Only 1 0 External Internal Input Asynchronous Only 1 1 External External Input Synchronous/Asynchronous fosc DIVIDE BY 2 DIVIDE BY 2 PRESCALER: DIVIDE BY 1 or 8 12-BIT COUNTER CD11 - CD0 SCP INTERNAL CLOCK DIVIDE BY 16 SCI CORE LOGIC USES DIVIDE BY 16 FOR ASYNCHRONOUS USES DIVIDE BY 2 FOR SYNCHRONOUS STIR TIMER INTERRUPT (STMINT) COD IF ASYNCHRONOUS DIVIDE BY 1 OR 16 IF SYNCHRONOUS DIVIDE BY 2 fo BPS = 64 x (7(SCP) + 1) x CD + 1) SCKP where: SCP = 0 or 1 CD = 0 to $FFF SCKP = 0 SCKP = 1 + - TO SCLK Figure 6-12 SCI Baud Rate Generator MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 27 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... one 24-bit word by “OR”-ing three data bytes read from the three addresses. The following code fragment requires that R0 initially points to X:$FFF4, register A is initially cleared, and R3 points to a data buffer. The only programming trick is using BCLR to test bit 1 of the packing pointer to see if it is pointing to X:$FFF6 and clearing bit 1 to point to X:$FFF4 if it had been pointing to X:$FFF6. This procedure resets the packing pointer after receiving three bytes. FLAG MOVE BCLR X:(R0),X0 #$1,R0 OR MOVE JCS RTI MOVE CLR RTI X0,A (R0)+ FLAG A,(R3)+ A ;Copy received data to temporary register ;Test for last byte ;reset pointer if it is the last byte ;Pack the data into register A ;and increment the packing pointer ;Jump to clean up routine if last byte ;Else return until next byte is received ;Move the packed data to memory ;Prepare A for packing next three bytes ;Return until the next byte is received The length and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCI control register. In the synchronous modes, the start bit, the eight data bits with LSB first, the address/data indicator bit and/or the parity bit, and the stop bit are received in that order for SSFTD equals zero (see Figure 6-10 (a)). For SSFTD equals one, the data bits are transmitted MSB first (see Figure 6-10(b)). The clock source is defined by the receive clock mode (RCM) select bit in the SCR. In the synchronous mode, the synchronization is provided by gating the clock. In either mode, when a complete word has been clocked in, the contents of the shift register can be transferred to the SRX and the flags; RDRF, FE, PE, and OR are changed appropriately. Because the operation of the SCI receive shift register is transparent to the DSP, the contents of this register are not directly accessible to the programmer. 6.3.2.4.2 SCI Transmit Registers The transmit data register is one byte-wide register mapped into four addresses: X:$FFF3, X:$FFF4, X:$FFF5, and X:$FFF6. In the asynchronous mode, when data is to be transmitted, X:$FFF4, X:$FFF5, and X:$FFF6 are used, and the register is called STX. When X:$FFF4 is written, the low byte on the data bus is transferred to the STX; when X:$FFF5 is written, the middle byte is transferred to the STX; and when X:$FFF6 is written, the high byte is transferred to the STX. This structure (see Figure 6-9) makes it easy for the programmer to unpack the bytes in a 24-bit word for transmission. Location X:$FFF3 should be written in the 11-bit asynchronous multidrop mode when the data is 6 - 28 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... an address and it is desired that the ninth bit (the address bit) be set. When X:$FFF3 is written, the transmit data register is called STXA, and data from the low byte on the data bus is stored in STXA. The address data bit will be cleared in the 11-bit asynchronous multidrop mode when any of X:$FFF4, X:$FFF5, or X:$FFF6 is written. When either STX or STXA is written, TDRE is cleared. The transfer from either STX or STXA to the transmit shift register occurs automatically, but not immediately, when the last bit from the previous word has been shifted out – i.e., the transmit shift register is empty. Like the receiver, the transmitter is double buffered. However, there will be a two to four serial clock cycle delay between when the data is transferred from either STX or STXA to the transmit shift register and when the first bit appears on the TXD pin. (A serial clock cycle is the time required to transmit one data bit). “A” X0 23 “B” “C” 16 15 8 7 0 STX X:$FFF6 MOVE X0, X:$FFF6; TRANSMIT CHARACTER “A” STX X:$FFF5 MOVE X0, X:$FFF5; TRANSMIT CHARACTER “B” STX X:$FFF4 MOVE X0, X:$FFF4; TRANSMIT CHARACTER “C” NOTE: STX is the same register decoded at three different addresses. (a) Unpacking 23 X:$FFF6 16 15 8 7 SRX MOVE X0, X:$FFF6; RECEIVE CHARACTER “A” SRX X:$FFF5 MOVE X0, X:$FFF5; RECEIVE CHARACTER “B” SRX X:$FFF4 X0 0 “A” “B” MOVE X0, X:$FFF4; RECEIVE CHARACTER “C” “C” NOTE: SRX is the same register decoded at three different addresses. (b) Packing Figure 6-13 Data Packing and Unpacking MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 29 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... The transmit shift register is not directly addressable, and a dedicated flag for this register does not exist. Because of this fact and the two to four cycle delay, two bytes cannot be written consecutively to STX or STXA without polling. The second byte will overwrite the first byte. The TDRE flag should always be polled prior to writing STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either STX or STXA is usually written as part of the interrupt service routine. Of course, the interrupt will only be generated if TDRE equals one. The transmit shift register is indirectly visible via the TRNE bit in the SSR. In the synchronous modes, data is synchronized with the transmit clock, which may have either an internal or external source as defined by the TCM bit in the SCCR. The length and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR. In the asynchronous modes, the start bit, the eight data bits (with the LSB first if SSFTD=0 and the MSB first if SSFTD=1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order (see Figure 6-10). The data to be transmitted can be written to any one of the three STX addresses. If SCKP equals one and SSHTD equals one, the SCI synchronous mode is equivalent to the SSI operation in the 8-bit data on-demand mode. 6.3.2.5 Preamble, Break, and Data Transmission Priority It is possible that two or three transmission commands are set simultaneously: 1. A preamble (TE was toggled) 2. A break (SBK was set or was toggled) 3. There is data for transmission (TDRE=0) After the current character transmission, if two or more of these commands are set, the transmitter will execute them in the following priority: 1. Preamble 2. Break 3. Data 6 - 30 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... 6.3.3 Register Contents After Reset There are four methods to reset the SCI. Hardware or software reset clears the port control register bits, which configure all I/O as general-purpose input. The SCI will remain in the reset state while all SCI pins are programmed as general-purpose I/O (CC2, CC1, and CC0=0); the SCI will become active only when at least one of the SCI I/O pins is programmed as not general-purpose I/O. During program execution, the CC2, CC1, and CC0 bits may be cleared (individual reset), which will cause the SCI to stop serial activity and enter the reset state. All SCI status bits will be set to their reset state; however, the contents of the interface control register are not affected, allowing the DSP program to reset the SCI separately from the other internal peripherals. The STOP instruction halts operation of the SCI until the DSP is restarted, causing the SSR to be reset. No other SCI registers are affected by the STOP instruction. Table 6-2 illustrates how each type of reset affects each register in the SCI. 6.3.4 SCI Initialization The correct way to initialize the SCI is as follows: 1. Hardware or software reset 2. Program SCI control registers 3. Configure SCI pins (at least one) as not general-purpose I/O Figure 6-14 and Figure 6-15 show how to configure the bits in the SCI registers. Figure 6-14 is the basic initialization procedure showing which registers must be configured. (1) A hardware or software reset should be used to reset the SCI and prevent it from doing anything unexpected while it is being programmed. (2) Both the SCI interface control register and the clock control register must be configured for any operation using the SCI. (3) The pins to be used must then be selected to release the SCI from reset and (4) begin operation. If interrupts are to be used, the pins must be selected, and interrupts must be enabled and unmasked before the SCI will operate. The order does not matter; any one of these three requirements for interrupts can be used to finally enable the SCI. Figure 6-15 shows the meaning of the individual bits in the SCR and SCCR. The figures below do not assume that interrupts will be used; they recommend selecting the appropriate pins to enable the SCI. Programs shown in Figures Figure 6-20, Figure 6-21, Figure 6-28, Figure 6-34, and Figure 6-36 control the SCI by enabling and disabling interrupts. Either method is acceptable. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 31 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Table 6-2 SCI Registers after Reset Freescale Semiconductor, Inc... Register Bit SCR SSR SCCR SRX STX SRSH STSH Bit Mnemonic Bit Number SCKP STIR TMIE TIE RIE ILIE TE RE WOMS RWU WAKE SBK SSFTD WDS (2–0) R8 FE PE OR IDLE RDRF TDRE TRNE TCM RCM SCP COD CD (11–0) SRX (23–0) STX (23–0) SRS (8–0) STS (8–0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2–0 7 6 5 4 3 2 1 0 15 14 13 12 11–0 23–16, 15–8, 7–0 23–0 8–0 8–0 Reset Type HW Reset SW Reset IR Reset ST Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 – – – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 – – – – – – – – – – – – – – – – – – 0 0 0 0 0 0 1 1 – – – – – – – – – – – – – – – – – – – – – – – 0 0 0 0 0 0 1 1 – – – – – – – – – NOTES: SRSH – SCI receive shift register, STSH – SCI transmit shift register HW – Hardware reset is caused by asserting the external RESET pin. SW – Software reset is caused by executing the RESET instruction. IR – Individual reset is caused by clearing PCC (bits 0–2) (configured for general-purpose I/O). ST – Stop reset is caused by executing the STOP instruction. 1 – The bit is set during the xx reset. 0 – The bit is cleared during the xx reset. – – The bit is not changed during the xx reset. Table 6-3 (a) through Table 6-4 (b) provide the settings for common baud rates for 6 - 32 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 1. PERFORM HARDWARE OR SOFTWARE RESET. 2. PROGRAM SCI CONTROL REGISTERS: a) SCI INTERFACE CONTROL REGISTER — X:$FFF0 b) SCI CLOCK CONTROL REGISTER — X:$FFF2 3. CONFIGURE AT LEAST ONE PORT C CONTROL BIT AS SCI. 23 X:$FFE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC CC CC CC CC CC CC CC CC PORT C CONTROL 8 7 6 5 4 3 2 1 0 REGISTER (PCC) Freescale Semiconductor, Inc... SCI CCx SCLK TXD RXD Function 0 GPIO 1 Serial Interface 4. SCI IS NOW ACTIVE. Figure 6-14 SCI Initialization Procedure the SCI. The asynchronous SCI baud rates show a baud rate error for the fixed oscillator frequency (see Table 6-3 (a)). These small-percentage baud rate errors should allow most UARTs to synchronize. The synchronous applications usually require exact frequencies, which require that the crystal frequency be chosen carefully (see Table 6-4 (a) and Table 6-4 (b)). An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI. For example, a 2.048 MHz bit rate requires a CPU clock of 32.768 MHz. An application may need a 40 MHz CPU clock and an external clock for the SCI. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 33 6 - 34 X:$FFF0 For More Information On This Product, Go to: www.freescale.com PORT C SCKP 15 STIR 14 TMIE 13 RIE 11 ILIE 10 TE 9 WOMS 7 RWU 6 5 000 001 010 011 100 101 110 111 WAKE Step 2a MULTIDROP = 1 POINT TO POINT = 0 WIRED - OR MODE RE 8 2 SSFTD WDS2 3 0 WDS1 WDS0 1 SCI INTERFACE CONTROL REGISTER (SCR) (READ/WRITE) = 8-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE) = RESERVED = 10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP) = RESERVED = 11-BIT ASYNCHRONOUS (1 START, 8 DATA, EVEN PARITY, 1 STOP) = 11-BIT ASYNCHRONOUS (1 START, 8 DATA, ODD PARITY, 1 STOP) = 11-BIT MULTIDROP (1 START, 8 DATA, EVEN PARITY, 1 STOP) = RESERVED SBK 4 ENABLE/DISABLE RECEIVE DATA ENABLE = 1 DISABLE = 0 ENABLE/DISABLE TRANSMIT DATA ENABLE = 1 DISABLE = 0 ENABLE/DISABLE RECEIVE INTERRUPT ENABLE = 1 DISABLE = 0 ENABLE/DISABLE TRANSMIT INTERRUPT ENABLE = 1 DISABLE = 0 Figure 6-15 SCI General Initialization Detail – Step 2 (Sheet 1 of 2) TIE 12 BIT 15 = 0 BIT 14 = 0 BIT 13 = 0 BIT 10 = 0 BIT 6 = 0 BIT 5 = 0 BIT 4 = 0 BIT 3 = 0 SCKP STIR TMIE ILIE RWU WAKE SBK SSFTD — — — — — — — — SELECT SCI OPERATION: FOR A BASIC CONFIGURATION, SET: STEP 2a. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA MOTOROLA X:$FFF2 STEP 2b. For More Information On This Product, Go to: www.freescale.com PORT C 14 RCM 15 TCM COD 12 CD11 11 CD10 10 CD9 9 CD8 8 CD7 7 5 CD5 Step 2b CD6 6 CD4 4 CD3 3 CD2 2 CD1 1 CD0 0 Figure 6-15 SCI General Initialization Detail – Step 2 (Sheet 2 of 2) SCP 13 SET CLOCK OUT DIVIDER IF SCLK PIN IS AN OTUPUT AND COD = 1 SCLK OUTPUT = 16× COD = 0 SCLK OUTPUT = 1× SET SCI CLOCK PRESCALER DIVIDE BY 8 = 1 DIVIDE BY 1 = 0 SET RECEIVE CLOCK SOURCE EXTERNAL CLOCK = 1 INTERNAL CLOCK = 0 SET TRANSMIT CLOCK SOURCE EXTERNAL CLOCK = 1 INTERNAL CLOCK = 0 SELECT CLOCK AND DATA RATE: SET THE CLOCK DIVIDER BITS (CD0 - CD11) ACCORDING TO TABLES 11 - 2 OR 11 - 3. SET THE SCI CLOCK PRESCALER BIT (SCP, BIT 13) ACCORDING TO TABLES 11 - 2 OR 11 - 3. Freescale Semiconductor, Inc... SCI CLOCK CONTROL REGISTER (SCCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6 - 35 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... Table 6-3 (a) Asynchronous SCI Bit Rates for a 40-MHz Crystal Bit Rate (BPS) SCP Bit Divider Bits (CD0–CD11) Bit Rate Error, Percent 625.0K 0 $000 0 56.0K 0 $00A +1.46 38.4K 0 $00F +1.72 19.2K 0 $020 -1.36 9600 0 $040 +0.16 8000 0 $04D +0.15 4800 0 $081 +0.15 2400 1 $020 -1.38 1200 1 $040 +0.08 600 1 $081 0 300 1 $103 0 BPS= f0 ÷ ∏ (64X (7(SCP) + 1) X (CD + 1)); f0=40 MHz SCP=0 or 1 CD=0 to $FFF Table 6-3 (b) Frequencies for Exact Asynchronous SCI Bit Rates Bit Rate (BPS) SCP Bit Divider Bits (CD0–CD11) Crystal Frequency 9600 0 $040 39,936,000 4800 0 $081 39,936,000 2400 0 $103 39,936,000 1200 0 $207 39,936,000 300 0 $822 39,993,000 9600 1 $007 39,321,600 4800 1 $00F 39,321,600 2400 1 $01F 39,321,600 1200 1 $040 39,360,000 300 1 $103 39,936,000 f0=BPS X 64X (7(SCP) + 1)X(CD + 1)) SCP=0 or 1 CD=0 to $FFF 6 - 36 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... Table 6-4 (a) Synchronous SCI Bit Rates for a 32.768-MHz Crystal Baud Rate (BPS) SCP Bit Divider Bits (CD0–CD11) Baud Rate Error, Percent 4.096M 0 $000 0 128K 0 $01F 0 64K 0 $03F 0 56K 0 $048 -0.195 32K 0 $07F 0 16K 0 $0FF 0 8000 0 $1FF 0 4000 0 $3FF 0 2000 0 $7FF 0 1000 0 $FFF 0 BPS= f0 ÷ (8 × (7(SCP) + 1) × (CD + 1)); f0=32.768 MHz SCP=0 or 1 CD=0 to $FFF Table 6-4 (b) Frequencies for Exact Synchronous SCI Bit Rates Bit Rate (BPS) SCP Bit Divider Bits (CD0–CD11) Crystal Frequency 2.048M 0 $001 32.768 MHz 1.544M 0 $002 37.056 MHz 1.536M 0 $002 36.864 MHz f0=BPS × 8 × (7(SCP) + 1) × (CD + 1) SCP=0 or 1 CD=0 to $FFF 6.3.5 SCI Exceptions The SCI can cause five different exceptions in the DSP (see Figure 6-53). These exceptions are as follows: 1. SCI Receive Data – caused by receive data register full with no receive error conditions existing. This error-free interrupt may use a fast interrupt service MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 37 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) PROGRAM MEMORY SPACE EXCEPTION STARTING ADDRESS Freescale Semiconductor, Inc... EXCEPTION SOURCE TWO WORDS PER VECTOR $0000 HARDWARE RESET $0002 STACK ERROR $0004 TRACE $0006 SWI (SOFTWARE INTERRUPT) $0008 IRQA EXTERNAL HARDWARE INTERRUPT $000A IRQB EXTERNAL HARDWARE INTERRUPT $000C SSI RECEIVE DATA $000E SSI RECEIVE DATA WITH EXCEPTION STATUS $0010 SSI TRANSMIT DATA $0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS $0014 SCI RECEIVE DATA $0016 SCI RECEIVE DATA WITH EXCEPTION STATUS $0018 SCI TRANSMIT DATA $001A SCI IDLE LINE $001C SCI TIMER $001E RESERVED $0020 HOST RECEIVE DATA $0022 HOST TRANSMIT DATA $0024 HOST COMMAND (DEFAULT) $0026 AVAILABLE FOR HOST COMMAND $0028 AVAILABLE FOR HOST COMMAND EXTERNAL INTERRUPTS INTERNAL INTERRUPTS EXTERNAL INTERRUPTS SYNCHRONOUS SERIAL INTERFACE INTERNAL INTERRUPTS • • • SERIAL COMMUNICATIONS INTERFACE HOST INTERFACE $003A AVAILABLE FOR HOST COMMAND $003C TIMER $003E ILLEGAL INSTRUCTION $0040 AVAILABLE FOR HOST COMMAND $007E AVAILABLE FOR HOST COMMAND INTERNAL INTERRUPTS • • • Figure 6-16 SCI Exception Vector Locations 6 - 38 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) routine for minimum overhead. This interrupt is enabled by SCR bit 11 (RIE). Freescale Semiconductor, Inc... 2. SCI Receive Data with Exception Status – caused by receive data register full with a receiver error (parity, framing, or overrun error). The SCI status register must be read to clear the receiver error flag. A long interrupt service routine should be used to handle the error condition. This interrupt is enabled by SCR bit 11 (RIE). 3. SCI Transmit Data – caused by transmit data register empty. This error-free interrupt may use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR bit 12 (TIE). 4. SCI Idle Line – occurs when the receive line enters the idle state (10 or 11 bits of ones). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 10 (ILIE). 5. SCI Timer – caused by the baud rate counter underflowing. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 13 (TMIE). 6.3.6 Synchronous Data The synchronous mode (WDS=0, shift register mode) is designed to implement serial-to-parallel and parallel-to-serial conversions. This mode will directly interface to 8051/8096 synchronous (mode 0) buses as both a controller (master) or a peripheral (slave) and is compatible with the SSI mode if SCKP equals one. In synchronous mode, the clock is always common to the transmit and receive shift registers. As a controller (synchronous master) shown in Figure 6-17, the DSP puts out a clock on the SCLK pin when data is present in the transmit shift register (a gated clock mode). The master mode is selected by choosing internal transmit and receive clocks (setting TCM and RCM=0). The example shows a 74HC165 parallel-to-serial shift register and 74HC164 serial-to-parallel shift register being used to convert eight bits of serial I/O to eight bits of parallel I/O. The load pulse latches eight bits into the 74HC165 and then SCLK shifts the RXD data into the SCI (these data bits are sample bits 0-7 in the timing diagram). At the same time, TXD shifts data out (B0-B7) to the 74HC164. When using the internal clock, data is transmitted when the transmit shift register is full. Data is valid on both edges of the output clock, which is compatible with an 8051 microprocessor. Received data is sampled in the middle of the clock low time if SCKP equals zero or in the middle of the clock high time if SCKP equals one. There is a window during which STX must be written with the next byte to be transmitted to prevent a gap between words. This MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 39 6 - 40 X:$FFF2 X:$FFF0 STIR 14 0 RCM SCKP 15 0 TCM RECEIVE DATA TRANSMIT DATA (SSFTD = 0) COD 12 TIE 12 SAMPLE XXXXXX SCP 13 TMIE 13 CLOCK OUTPUT (SCP = 0) 14 15 For More Information On This Product, Go to: www.freescale.com PORT C XX 1 B1 CD10 10 ILIE 10 XX CD9 9 TE 9 2 B2 XX CD8 8 RE 8 TXD SCLK RXD DSP56002 3 CLK CLK Q L D XX 4 XX CD5 5 WAKE 5 5 B5 0 2 6 B6 CD3 3 XX CD2 2 SSFTD WDS2 0 3 B7 7 0 0 CD0 0 XXXXXXX CD1 1 8 PARALLEL OUTPUTS LOAD PULSE 0 1 WDS1 WDS0 8 PARALLEL INPUTS XX CD4 4 SBK 4 Figure 6-17 Synchronous Master 74HC164 S/P D Q B4 CD6 6 RWU 6 WRITE STX B3 CD7 7 WOMS 7 74HC165 EXAMPLE: SHIFT REGISTER I/O 0 B0 CD11 11 RIE 11 Freescale Semiconductor, Inc... SCI CLOCK CONTROL REGISTER (SCCR) (READ/WRITE) SCI CONTROL REGISTER (SCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... window is from the time TDRE goes high halfway into transmission of bit 1 until the middle of bit 6 (see Figure 6-19(a)). As a peripheral (synchronous slave) shown in Figure 6-18, the DSP accepts an input clock from the SCLK pin. If SCKP equals zero, data is clocked in on the rising edge of SCLK, and data is clocked out on the falling edge of SCLK. If SCKP equals one, data is clocked in on the falling edge of SCLK, and data is clocked out on the rising edge of SCLK. The slave mode is selected by choosing external transmit and receive clocks (TCM and RCM=1). Since there is no frame signal, if a clock is missed due to noise or any other reason, the receiver will lose synchronization with the data without any error signal being generated. Detecting an error of this type can be done with an error detecting protocol or with external circuitry such as a watchdog timer. The simplest way to recover synchronization is to reset the SCI. The timing diagram in Figure 6-18 shows transmit data in the normal driven mode. Bit B7 is essentially one-half SCI clock long (TSCI/2 + 1.5 TEXTAL) The last data bit is truncated so that the pin is guaranteed to go to its reset state before the start of the next data word, thereby delimiting data words. The 1.5 crystal clock cycles provide sufficient hold time to satisfy most external logic requirements. The example diagram requires that the WOMS bit be set in the SCR to wired-OR RXD and TXD, which causes TXD to be three-stated when not transmitting. Collisions (two devices transmitting simultaneously) must be avoided with this circuit by using a protocol such as alternating transmit and receive periods. In the example, the 8051 is the master device because it controls the clock. There is a window during which STX must be written with the next byte to be transmitted to prevent the current word from being retransmitted. This window is from the time TDRE goes high, which is halfway into the transmission of bit 1, until the middle of bit 6 (see Figure 6-19(b)). Of course, this assumes the clock remains continuous – i.e., there is a second word. If the clock stops, the SCI stops. The DSP is initially configured according to the protocol to either receive data or transmit data. If the protocol determines that the next data transfer will be a DSP transmit, the DSP will configure the SCI for transmit and load STX (or STXA). When the master starts SCLK, data will be ready and waiting. If the protocol determines that the next data transfer will be a DSP receive, the DSP will configure the SCI for receive and will either poll the SCI or enable interrupts. This methodology allows multiple slave processors to use the same data line. Selection of individual slave processors can be under protocol control or by multiplexing SCLK. Note: TCM=0, RCM=1 and TCM=1,RCM=0 are not allowed in the synchronous mode. The results are undefined. The assembly program shown in Figure 6-20 uses the SCI synchronous mode to transmit only the low byte of the Y data ROM contents. The program sets the reset vector to run the program after a hardware reset, puts the MOVEP instruction at the SCI transmit interMOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 41 6 - 42 X:$FFF2 X:$FFF0 STIR 14 1 RCM SCKP 15 1 TCM 13 RECEIVE DATA TRANSMIT DATA (SSFTD = 0) COD 12 TIE 12 For More Information On This Product, Go to: www.freescale.com PORT C 0 B0 XX CD11 11 RIE 11 1 B1 CD10 10 ILIE 10 XX CD9 9 TE 9 2 B2 XX CD8 8 RE 8 B4 CD6 6 RWU 6 3 XX 4 WRITE STX B3 CD7 7 WOMS 7 XX CD5 5 WAKE 5 XX CD4 4 0 2 P3.1 P3.0 6 B6 CD3 3 OR 8096 7 0 1 0 0 SCI CLOCK CONTROL REGISTER (SCCR) (READ/WRITE) SCI CONTROL REGISTER (SCR) (READ/WRITE) 1.5 tcyc CD0 0 XXXXXXX CD1 1 WDS1 WDS0 B7 8051 XX CD2 2 SSFTD WDS2 0 3 Figure 6-18 Synchronous Slave SCLK TXD RXD DSP56002 5 4 SBK B5 EXAMPLE: INTERFACE TO SYNCHRONOUS MICROCOMPUTER BUSES SAMPLE XXXXXX SCP 13 TMIE CLOCK INPUT (SKP = 0) 14 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA MOTOROLA STX WRITE RANGE BIT 0 MAX 5.5 SERIAL CLOCK CYCLES BIT 1 BIT 2 BIT 4 BIT 5 0 BY STX WRITE FIRST WORD BIT 3 TDRE STX WRITE RANGE FOR NO GAP BETWEEN WORDS 1 AND 2 For More Information On This Product, Go to: www.freescale.com PORT C STX WRITE RANGE BIT 0 BIT 1 BIT 2 BIT 4 BIT 5 0 BY STX WRITE FIRST WORD BIT 3 TDRE STX WRITE RANGE Figure 6-19 Synchronous Timing (b) Slave NOTE: In external clock mode, if data 2 is written after the middle of bit 6 of data 1, then the previous data is retransmitted and data 2 is transmitted after the retransmission of data 1. TXD (TRANSMIT DATA) TRDE STX WRITE RANGE SERIAL CLOCK (EXT) SYNCHRONOUS MODE, INTERNAL CLOCK (SLAVE) (a) Master NOTE: In internal clock mode, if data 2 is written after the middle of bit 6 of data 1, then a gap of at least two serial bits is inserted between word 1 and word 2. The gap is bigger as STX is written later. TXD (TRANSMIT DATA) TRDE STX WRITE RANGE SERIAL CLOCK (INT) SYNCHRONOUS MODE, INTERNAL CLOCK (MASTER) BIT 6 BIT 6 BIT 7 BIT 7 Freescale Semiconductor, Inc... BIT 0 BIT 0 BIT 2 BIT 2 SECOND WORD BIT 1 SECOND WORD BIT 1 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) rupt vector location, sets the memory wait states to zero, and configures the memory 6 - 43 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) ORG JMP ORG MOVEP P:0 $40 P:$18 Y:(R0)+,X:$FFF4 ;Reset vector ; ;SCI transmit interrupt vector ;Transmit low byte of data ORG MOVEP MOVE MOVE MOVEC MOVEP MOVEP MOVEP MOVEC LAB0 JMP P:$40 #0,X:$FFFE #$100,R0 #$FF,M0 #6,OMR #$C000,X:$FFFF #$1200,X:$FFF0 #7,X:$FFE1 #0,SR LAB0 ;Clear BCR ;Data ROM start address ;Size of data ROM - Wraps around at $200 ;Change operating mode to enable data ROM ;Interrupt priority register ;8-bit synchronous mode ;Port C control register – enable SCI ;Unmask interrupts ;Wait in loop for interrupts Figure 6-20 SCI Synchronous Transmit pointers, operating mode register, and the IPR. The SCI is then configured and the interrupts are unmasked, which starts the data transfer. The jump-to-self instruction (LAB0 JMP LAB0) is used to wait while interrupts transfer the data. The program shown in Figure 6-21 is the program for receiving data from the program presented in Figure 6-20. The program sets the reset vector to run the program after hardware reset, puts the MOVEP instruction to store the data in a circular buffer starting at $100 at the SCI receive interrupt vector location, puts another MOVEP instruction at the SCI receive interrupt vector location, sets the memory wait states to zero, and configures the memory pointers and IPR. The SCI is then configured and the interrupts are unmasked, which starts the data transfer. The jump-to-self instruction (LAB0 JMP LAB0) is used to wait while interrupts transfer the data. 6.3.7 Asynchronous Data Asynchronous data uses a data format with embedded word sync, which allows an unsynchronized data clock to be synchronized with the word if the clock rate and number of bits per word is known. Thus, the clock can be generated by the receiver rather than requiring a separate clock signal. The transmitter and receiver both use an internal clock that is 16 × the data rate to allow the SCI to synchronize the data. The data format requires that each data byte have an additional start bit and stop bit. In addition, two of the word formats have a parity bit. The multidrop mode used when SCIs are on a common 6 - 44 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) ORG JMP P:0 $40 ORG MOVEP NOP P:$14 ;SCI receive data vector X:$FFF4,Y:(R0)+ ;Receive low byte of data ;Fast interrupt response MOVEP MOVEP X:$FFF1,X0 ;Receive with exception. Read status register X:$FFF4,Y:(R0)+ ;Receive low byte of data ORG MOVEP MOVE MOVE MOVEP MOVEP MOVEP MOVEP MOVEC LAB0 JMP ;Reset vector ; P:$40 #0,X:$FFFE #$100,R0 #$FF,M0 #$C000,X:$FFFF #$900,X:$FFF0 #$C000,X:$FFF2 #7,X:$FFE1 #0,SR LAB0 ;Clear BCR ;Data ROM start address ; Size of data ROM – wraps around at $200 ;Interrupt priority register ; 8-bit synchronous mode receive only ;Clock control register external clock ;Port C control register – enable SCI ;Unmask interrupts ;Wait in loop for interrupts Figure 6-21 SCI Synchronous Receive bus has an additional data type bit. The SCI can operate in full-duplex or half-duplex modes since the transmitter and receiver are independent. The SCI transmitter and receiver can use either the internal clock (TCM=0 and/or RCM=0) or an external clock (TCM=1 and/or RCM=1) or a combination. If a combination is used, the transmitter and receiver can run at different data rates. 6.3.7.1 Asynchronous Data Reception Figure 6-22 illustrates initializing the SCI data receiver for asynchronous data. The first step (1) resets the SCI to prevent the SCI from transmitting or receiving data. Step two (2) selects the desired operation by programming the SCR. As a minimum, the word format (WDS2, WDS1, and WDS0) must be selected, and (3) the receiver must be enabled (RE=1). If (4) interrupts are to be used, set RIE equals one. Use Table 6-3 (a) through Table 6-4 (b) to set (5) the baud rate (SCP and CD0–CD11 in the SCCR). Once the SCI is completely configured, it is enabled by (6) setting the RXD bit in the PCC. The receiver is continually sampling RDX at the 16 × clock rate to find the idle-start-bit transition edge. When that edge is detected (1) the following eight or nine bits, depending on the mode, are clocked into the receive shift register (see Figure 6-23). Once a complete byte is received, (2) the character is latched into the SRX, and RDRF is set as well MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 45 6 - 46 For More Information On This Product, Go to: www.freescale.com PORT C TMIE TIE 12 RIE 1 11 ILIE 10 RCM TCM SCP 13 COD 12 CD11 11 PRESCALER IF SCP = 1, THEN DIVIDE BY 8 IF SCP = 0, THEN DIVIDE BY 1 14 15 CD10 10 CD9 9 TE 9 NOTE: 0 Serial Interface 1 9 7 CC7 8 CC8 CD7 7 WOMS 7 CC6 6 CD6 6 RWU 6 CC5 5 CD5 5 WAKE 5 CC4 4 CD4 4 SBK 4 2 CC3 3 CD3 3 RXD CC2 2 CD2 2 SSFTD WDS2 3 0 CD0 0 CC1 1 SCI Figure 6-22 Asynchronous SCI Receiver Initialization 1 0 DIVIDE BY 1 TO 4096 CD1 1 WDS1 WDS0 1 If RE is cleared while a valid character is being received, the reception of the character will be completed before the receiver is disabled. GPIO Function 0 CCx 23 8 RE 1 8 CD8 SET THE RXD BIT IN PCC TO ENABLE THE SCI RECEIVER SYSTEM. X:$FFE1 6. STIR SCKP 13 SET THE BAUD RATE BY PROGRAMMING THE SCCR. X:$FFF2 5. 14 15 HARDWARE OR SOFTWARE RESET PROGRAM SCR WITH DESIRED MODE AND FEATURES. TURN ON RECEIVER (RE = 1). OPTIONALLY ENABLE RECEIVER INTERRUPTS (RIE = 1). X:$FFF0 1. 2. 3. 4. Freescale Semiconductor, Inc... PORT C CONTROL REGISTER (PCC) SCI CONTROL REGISTER (SCCR) (READ/WRITE) SCI CONTROL REGISTER (SCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) as the error flags, OR, PE, and FE. If (3) interrupts are enabled, an interrupt is generated. MOTOROLA MOTOROLA FE R8 PE 5 OR 4 IDLE 3 For More Information On This Product, Go to: www.freescale.com PORT C SCI RECEIVE DATA INTERRUPT VECTOR TABLE X:$FFF4 X:$FFF5 5. 23 TRNE 0 X:$FFF6 TDRE 1 SRX 8 7 READING SRX CLEARS RDRF IN THE SSR. SRX 16 15 STATUS REGISTER (SSR) (READ ONLY) THE RECEIVE INTERRUPT SERVICE ROUTINE READS THE RECEIVED CHARACTER. RDRF 1 2 Figure 6-23 SCI Character Reception 4. RECEIVE INTERRUPT SERVICE ROUTINE IF RIE = 1 IN SCR, THEN AN INTERRUPT IS GENERATED. X:$FFF1 6 7 TRANSFERRING THE RECEIVED CHARACTER INTO SRX SETS RDRF IN THE SSR. RXD THE RECEIVER IS IDLE UNTIL A CHARACTER IS RECEIVED IN THE DATA SHIFT REGISTER. P:$0014 3. 2. 1. Freescale Semiconductor, Inc... SRX 0 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6 - 47 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... The interrupt service routine, which can be a fast interrupt or a long interrupt, (4) reads the received character. Reading the SRX (5) automatically clears RDFR in the SSR and makes the SRX ready to receive another byte. If (1) an FE, PE, or OR occurs while receiving data (see Figure 6-24), (2) RDRF is set because a character has been received; FE, PE, or OR is set in the SSR to indicate that an error was detected. Either (3) the SSR can be polled by software to look for errors, or (4) interrupts can be used to execute an interrupt service routine. This interrupt is different from the normal receive interrupt and is caused only by receive errors. The long interrupt service routine should (5) read the SSR to determine what error was detected and then (6) read the SRX to clear RDRF and all three error flags. 6.3.7.2 Asynchronous Data Transmission Figure 6-25 illustrates initializing the SCI data transmitter for asynchronous data. The first step (1) resets the SCI to prevent the SCI from transmitting or receiving data. Step two (2) selects the desired operation by programming the SCR. As a minimum, the word format (WDS2, WDS1, and WDS0) must be selected, and (3) the transmitter must be enabled (TE=1). If (4) interrupts are to be used, set TIE equals one. Use Table 6-3 (a) through Table 6-4 (b) to set (5) the baud rate (SCP and CD0–CD11 in the SCCR). Once the SCI is completely configured, it can be enabled by (6) setting the TXD bit in the PCC. Transmission begins with (7) a preamble of ones. If polling is used to transmit data (see Figure 6-26), the polling routine can look at either TDRE or TRNE to determine when to load another byte into STX. If TDRE is used (1), one byte may be loaded into STX. If TRNE is used (2), two bytes may be loaded into STX if enough time is allowed for the first byte to begin transmission (see 6.3.2.4.2). If interrupts are used (3), then an interrupt is generated when STX is empty. The interrupt routine, which can be a fast interrupt or a long interrupt, writes (4) one byte into STX. If multidrop mode is being used and this byte is an address, STXA should be used instead of STX. Writing STX or STXA (5) clears TDRE in the SSR. When the transmit data shift register is empty (6), the byte in STX (or STXA) is latched into the transmit data shift register, TRNE is cleared, and TDRE is set. There is a provision to send a break or preamble. A break (space) consists of a period of zeros with no start or stop bits that is as long or longer than a character frame. A preamble (mark) is an inverted break. A preamble of 10 or 11 ones (depending on the word length selected by WDS2, WDS1, and WDS0) can be sent with the following procedure (see Figure 6-27). (1) Write the last byte to STX and (2) wait for TDRE equals one. This is the byte that will be transmitted immediately before the preamble. (3) Clear TE and then again set it to one. Momentarily clearing TE causes the output to go high for one character frame. 6 - 48 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT C R8 PE OR 4 AT LEAST ONE BIT SET FE 5 IDLE 3 RDRF 1 2 0 X:$FFF1 5 RIE PE SCI RECEIVE DATA INTERRUPT VECTOR TABLE 6 FE 7 R8 4 OR 3 2 RDRF 1 1 0 TDRE TRNE RECEIVE WITH EXCEPTION INTERRUPT SERVICE ROUTINE SCI STATUS REGISTER (SSR) (READ ONLY) READ SRX. THIS CLEARS RDRF IN THE SSR AND CLEARS THE OR, PE, AND FE FLAGS. SRX 6. SRX 8 7 READ SSR SRX 16 15 5. X:$FFF4 X:$FFF5 X:$FFF6 23 Figure 6-24 SCI Character Reception with Exception INTERRUPT WITH EXCEPTION IDLE RXD SCI STATUS REGISTER (SSR) TDRE TRNE (READ ONLY) 1 IF RIE = 1 IN SCR, THEN AN INTERRUPT WITH ERROR IS GENERATED. P:$0016 4. X:$FFF1 6 SSR CAN BE POLLED BY SOFTWARE. 3. 7 THIS SETS RDRF AND SET OR, PE, OR FE IN SSR. XXXXXXXX SERIAL STRING OF BAD DATA A CHARACTER IS RECEIVED WITH AT LEAST ONE OF THE FOLLOWING ERRORS: — FRAMING ERROR (FE = BIT 6 IN SSR — PARITY ERROR (PE = BIT 5 IN SSR) — OVERRUN ERROR (OR = BIT 4 IN SSR) 2. 1. Freescale Semiconductor, Inc... 0 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) If TE remains cleared for a longer period, the output will remain high for an even number 6 - 49 6 - 50 For More Information On This Product, Go to: www.freescale.com PORT C TMIE TIE 1 12 RIE 11 ILIE 10 TE 1 9 RE 8 WOMS 7 Serial Interface 1 0 9 7 CC7 8 CC8 CC6 6 RWU 6 CC5 5 WAKE 5 CC4 4 SBK 4 2 CC3 3 1 0 TXD Figure 6-25 Asynchronous SCI Transmitter Initialization 1 1 SCI CC0 0 WDS1 WDS0 If TE is cleared while transmitting a character, the transmission of the character will be completed before the transmitter is disabled. CC2 2 SSFTD WDS2 3 THE TRANSMITTER WILL FIRST BROADCAST A PREAMBLE OF ONES BEFORE BEGINNING DATA TRANSMISSION: 10 ONES WILL BE TRANSMITTED FOR THE 10-BIT ASYNCHRONOUS MODE. 11 ONES WILL BE TRANSMITTED FOR THE 11-BIT ASYNCHRONOUS MODE. GPIO Function 23 0 CCx NOTE: 7. STIR SCKP 13 SET THE SCI CLOCK PRESCALER BIT AND THE CLOCK DIVIDER BITS IN THE SCCR. SET THE TXD BIT IN PCC TO ENABLE THE SCI TRANSMITTER SYSTEM. X:$FFE1 5. 6. 14 15 HARDWARE OR SOFTWARE RESET PROGRAM SCR WITH DESIRED MODE AND FEATURES. TURN ON TRANSMITTER (TE = 1). OPTIONALLY ENABLE TRANSMITTER INTERRUPTS (TIE = 1). X:$FFF0 1. 2. 3. 4. Freescale Semiconductor, Inc... PORT C CONTROL REGISTER (PCC) SCI CONTROL REGISTER (SCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT C 6. 0 0 0 13 0 12 0 11 0 10 0 9 0 8 R8 7 FE 6 PE 5 STORE ONE CHARACTER INTO STX (A) THIS CLEARS TDRE IN SSR. 4. 5. TRANSMIT INTERRUPT SERVICE ROUTINE X:$FFF3 X:$FFF4 X:$FFF5 X:$FFF6 23 OR 4 STX IDLE 3 16 15 RDRF 2 TRNE TDRE STX 1 0 1 1 Figure 6-26 Asynchronous SCI Character Transmission THE CHARACTER IN STX IS COPIED INTO TRANSMIT DATA SHIFT REGISTER. TRNE IS CLEARED. TDRE IS SET. GO TO STEP 2. AVAILABLE FOR HOST COMMAND SCI TRANSMIT DATA INTERRUPT VECTOR TABLE WHEN STX IS EMPTY, THEN TDRE = 1. WHEN STX IS EMPTY AND THE TRANSMIT DATA SHIFT REGISTER IS EMPTY THEN TRNE = 1. IF TIE = 1 IN SCR AND TDRE = 1 IN SSR, THEN AN INTERRUPT IS GENERATED. P:$0018 1. 2. 3. X:$FFF1 14 15 Freescale Semiconductor, Inc... 8 7 STXA STX SCI STATUS REGISTER (SSR) (READ/WRITE) 0 TXD Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) of character frames until TE is set. (4) Write the first byte to follow the preamble into SRX 6 - 51 6 - 52 ST • TMIE TIE 12 RIE 11 TOGGLE (1 - 0 - 1) TO SEND A CHARACTER TIME OF ALL ONES (MARKS) STIR SCKP 13 ILIE 10 TE 9 WOMS 7 RWU 6 5 WAKE TOGGLE (0 - 1 - 0) TO SEND A CHARACTER TIME OF ALL ZEROS (SPACES) RE 8 SBK 4 For More Information On This Product, Go to: www.freescale.com PORT C D1 D3 D4 D5 D6 D5 1 D6 START OF BREAK D7 STOP SBK = 1 D2 CHARACTER ENDS BEFORE BREAK BEGINS. D4 SBK = 0 D0 LAST CHARACTER 1. 2. 3. 4. 0 WDS1 WDS0 1 2 D7 3 5 6 7 9 10 1 2 9 10 1 2 SBK = 1 BREAK PERIOD IS AN EXACT MULTIPLE OF CHARACTER TIMES. 8 SBK = 1 SPACES (ZEROS) IDLE LINE 3 ST 4 1 2 3 4 5 FIRST CHARACTER 6 7 STOP ST SCI INTERFACE CONTROL REGISTER (SCR) (READ/WRITE) 5 6 7 8 SBK = 0 STOP START OF BREAK 9 10 D0 D1 FIRST CHARACTER AFTER BREAK ST A STOP BIT AT THE END OF THE BREAK WILL BE INSERTED BEFORE THE NEXT CHARACTER STARTS 0 Figure 6-27 Transmitting Marks and Spaces 4 STOP PREAMBLE OF 10 ONES WRITE THE LAST BYTE TO STX. WAIT FOR TRDE = 1. THE LAST BYTE IS NOW IN THE TRANSMIT SHIFT REGISTER. CLEAR TE AND SET BACK TO ONE. THIS QUEUES THE PREAMBLE TO FOLLOW THE LAST BYTE. WRITE THE FIRST BYTE TO FOLLOW THE PREAMBLE INTO SRX. MARKS (ONES) 2 SSFTD WDS2 3 10 OR 11 ONES/ZEROS WILL BE SENT DEPENDING ON THE WORD LENGTH SPECIFIED BY WDS2, WDS1, WDS0. X:$FFF0 14 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) before the preamble is complete and resume normal transmission. Sending a break follows the same procedure except that instead of clearing TE, SBK is set in the SCR to send breaks and then reset to resume normal data transmission. Freescale Semiconductor, Inc... The example presented in Figure 6-28 uses the SCI in the asynchronous mode to transfer data into buffers. Interrupts are used, allowing the DSP to perform other tasks while the data transfer is occurring. This program can be tested by connecting the SCI transmit and receive pins. Equates are used for convenience and readability. The program sets the reset vector to run the program after reset, puts a MOVEP instruction at the SCI receive interrupt vector location, and puts a MOVEP and BCLR at the SCI transmit interrupt vector location so that, after transmitting a byte, the transmitter is disabled until another byte is ready for transmission. The SCI is initialized by setting the interrupt level, which configures the SCR and SCCR, and then is enabled by writing the PCC. The main program begins by enabling interrupts, which allows data to be received. Data is transmitted by moving a byte of data to the transmit register and by enabling interrupts. The jump-to-self instruction (SEND JMP SEND) is used to wait while interrupts transfer the data. ;******************************************************************************************* ; SCI ASYNC WITH INTERRUPTS AND SINGLE BYTE BUFFERS* ;******************************************************************************************* ;************************************************* ; SCI and other EQUATES* ;************************************************* START EQU $0040 ;Start of program PCC EQU $FFE1 ;Port C control register SCR EQU $FFF0 ;SCI interface control register SCCR EQU $FFF2 ;SCI clock control register SRX EQU $FFF4 ;SCI receive register STX EQU $FFF4 ;SCI transmit register BCR EQU $FFFE ;Bus control register IPR EQU $FFFF ;Interrupt priority register RXBUF EQU $100 ;Receive buffer TXBUF EQU $200 ;Transmit buffer Figure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 1 of 3) ;************************************************* MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 53 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... ; RESET VECTOR* ;************************************************* ORG P:$0000 JMP START ;************************************************* ; SCI RECEIVE INTERRUPT VECTOR* ;************************************************* ORG P:$0014 ;Load the SCI RX interrupt vectors MOVEP X:SRX,Y:(R0)+ ;Put the received byte in the receive ;buffer. This receive routine is ;implemented as a fast interrupt. ;************************************************* ; SCI TRANSMIT INTERRUPT VECTOR* ;************************************************* ORG P:$0018 ;Load the SCI TX interrupt vectors MOVEP X:(R3)+,X:STX ;Transmit a byte and ;increment the pointer in the ;transmit buffer. BCLR #12,X:SCR ;Disable transmit interrupts ;******************************************************************************************* ; INITIALIZE THE SCI PORT AND RX, TX BUFFER POINTERS* ;******************************************************************************************* ORG P:START ;Start the program at location $40 ORI #$03,MR ;Mask interrupts temporarily MOVEP #$C000,X:IPR ;Set interrupt priority to 2 MOVEP #$0B02,X:SCR ;Disable TX, enable RX interrupts ;Enable transmitter, receiver ;Point to point ;10-bit asynchronous ;(1 start, 8 data, 1 stop) MOVEP #$0022,X:SCCR;Use internal TX, RX clocks ;9600 BPS MOVEP #>$03,X:PCC ;Select pins TXD and RXD for SCI MOVE RXBUF,R0 ;Initialize the receive buffer MOVE TXBUF,R3 ;Initialize the transmit buffer Figure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 2 of 3) ;************************************************* 6 - 54 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... ; MAIN PROGRAM* ;************************************************* ANDI #$FC,MR ;Re-enable interrupts MOVE #>$41,X:(R3) ;Move a byte to the transmit buffer MOVE R0,X:(R3) BSET #12,X:SCR ;and enable interrupts so it ;will be transmitted SEND JMP SEND ;Normally something more useful ;would be put here. END ;End of example. Figure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 3 of 3) 6.3.8 Multidrop Multidrop is a special case of asynchronous data transfer. The key difference is that a protocol is used to allow networking transmitters and receivers on a single data-transmission line. Interprocessor messages in a multidrop network typically begin with a destination address. All receivers check for an address match at the start of each message. Receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message. Receivers with an address match can receive the message and optionally transmit an acknowledgment to the sender. The particular message format and protocol used are determined by the user’s software. These message formats include point-to-point, bus, token-ring, and custom configurations. The SCI multidrop network is compatible with other leading microprocessors. Figure 6-29 shows a multidrop system with one master and N slaves. The multidrop mode is selected by setting WDS2 equals one, WDS1 equals one, and WDS0 equals zero. One possible protocol is to have a preamble or idle line between messages, followed by an address and then a message. The idle line causes the slaves to wake up and compare the address with their own address. If the addresses match, the slave receives the message. If the addresses do not match, the slave ignores the message and goes back to sleep. It is also possible to generate an interrupt when an address is received, eliminating the need for idle time between consecutive messages and addresses. It is also possible for each slave to look for more than one address, which allows each slave to respond to individual messages as well as broadcast messages (e.g., a global reset). MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 55 X:$FFF0 6 - 56 STIR SCKP TIE 12 IDLE LINE TMIE 13 For More Information On This Product, Go to: www.freescale.com PORT C TE 9 RE 8 EXIT RECEIVE REST OF MESSAGE; DO NOT MASK INTERRUPTS. SBK 4 NO Figure 6-29 11-Bit Multidrop Mode YES DOES HEADER EQUAL MY ADDRESS ? DOES HEADER EQUAL MY ADDRESS ? YES WAKE 5 SSFTD 3 WDS2 1 2 EXIT 0 0 WDS1 WDS0 1 1 IGNORE REST OF MESSAGE. DISABLE RECEIVER AND ITS INTERRUPTS BY SETTING RWU = 1. RXD OTHER SERIAL DEVICE ADDRESS N LONG MESSAGE FOR MPU 1 RWU 6 RXD MC68HC11 ADDRESS 3 WOMS 7 DEVICES IGNORING MESSAGES RXD DSP56002 ADDRESS 2 ADDRESS 1 HEADER ILIE 10 RECEIVER INTERRUPT NO RIE 11 RECEIVER INTERRUPT DEVICE RECEIVING MESSAGE RXD DSP56002 ADDRESS 1 14 15 Freescale Semiconductor, Inc... TXD DSP56002 IDLE LINE SCI CONTROL REGISTER (SCCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... 6.3.8.1 Transmitting Data and Address Characters Transmitting data and address when the multidrop mode is selected is shown in Figure 6-30. The output sequence shown is idle line, data/address, and the next character. In both cases, an “A” is being transmitted. To send data, TE must be toggled to send the idle line, and then “A” must be sent to STX. Sending the “A” to the STX sets the ninth bit in the frame to zero, which indicates that this frame contains data. If the “A” is sent to STXA instead, the ninth bit in the frame is set to a one, which indicates that this frame contains an address. 6.3.8.2 Wired-OR Mode Building a multidrop bus network requires connecting multiple transmitters to a common wire. The wired-OR mode allows this to be done without damaging the transmitters when the transmitters are not in use. A protocol is still needed to prevent two transmitters from simultaneously driving the bus. The SCI multidrop word format provides an address field to support this protocol. Figure 6-31 shows a multidrop configuration using wired-OR (set bit 7 of the SCR). The protocol shown consists of an idle line between messages; each message begins with an address character. The message can be any length, depending on the protocol. Each processor in this system has one address that it responds to although each processor can be programmed to respond to more than one address. 6.3.8.3 Idle Line Wakeup A wakeup mode frees a DSP from reading messages intended for other processors. The usual operational procedure is for each DSP to suspend SCI reception (the DSP can continue processing) until the beginning of a message. Each DSP compares the address in the message header with the DSPs address. If the addresses do not match, the SCI again suspends reception until the next address. If the address matches, the DSP will read and process the message and then suspend reception until the next address. The idle line wakeup mode wakes up the SCI to read a message before the first character arrives. This mode allows the message to be in any format. Figure 6-32 shows how to configure the SCI to detect and respond to an idle line. The word format chosen (WDS2, WDS1, and WDS0 in the SCR) must be asynchronous. The WAKE bit must be clear to select idle line wakeup, and RWU must be set to put the SCI to “sleep” and enable the wakeup function. RIE should be set if interrupts are to be used to receive data. If processing must occur when the idle line is first detected, ILIE should be set. The current message is followed by one or more data frames of ones (10 or 11 bits each, depending on which word format is used), which are detected as an idle line. If the word format is multidrop (an 11-bit code), after the 11 ones, the receiver determines the line is idle and (1) clears the RWU, enabling the receiver. The IDLE bit (2) and an internal flag SRIINT (3) are set, indicating the line is idle. The SCI is now ready to receive messages; however, nothing more will happen until the next start bit unless (4) ILIE is set. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 57 6 - 58 For More Information On This Product, Go to: www.freescale.com PORT C X:$FFF3 X:$FFF4 X:$FFF5 X:$FFF6 X:$FFF3 X:$FFF4 X:$FFF5 X:$FFF6 23 23 23 23 STX STX 16 15 8 7 8 7 8 7 8 7 “A” STXA STX STXA STX 0 0 0 0 IDLE LINE ADDRESS IDLE LINE ST ST 1 1 0 0 SCI TRANSMIT DATA REGISTER (WRITE ONLY) TXD TXD 0 0 SCI TRANSMIT DATA REGISTER LOW (WRITE ONLY) SCI TRANSMIT DATA REGISTER MID (WRITE ONY) SCI TRANSMIT DATA REGISTER HIGH (WRITE ONLY) DATA 0 0 Figure 6-30 Transmitting Data and Address Characters SCI TRANSMIT DATA SHIFT REGISTER STX 16 15 16 15 SCI TRANSMIT DATA SHIFT REGISTER STX 16 15 “A” $41 01000001 Freescale Semiconductor, Inc... 0 0 0 0 1 1 1 DATA 0 STOP ST NEXT CHARACTER STOP ST ADDRESS 0 0 NEXT CHARACTER Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA MOTOROLA REC A2 MESSAGE A XMIT DSP56002 SCI PORT ADDRESS 1 STIR SCKP For More Information On This Product, Go to: www.freescale.com PORT C IDLE 13 N0 RIE 11 IDLE N1 REC N4 ADDRESS N N3 N5 FIRST CHARACTER N6 WOMS 1 7 XMIT N7 1 RWU 6 D0 SBK 4 D2 D3 D4 XMIT D5 WDS0 0 0 D6 0 AN D1 SECOND CHARACTER OF MESSAGE D D0 THIRD CHARACTER MESSAGE D 1K SCI CONTROL REGISTER (SCR) (READ/WRITE) INDICATES A DATA CHARACTER D7 REC DSP56002 SCI PORT ADDRESS N WDS1 1 1 SECOND CHARACTER A1 MESSAGE B REC WDS2 1 2 FIRST CHARACTER OF MESSAGE D D1 XMIT 3 SSFTD DSP56002 SCI PORT ADDRESS N-1 WAKE 5 Figure 6-31 Wired-OR Mode REC OTHER SERIAL PORT ADDRESS 3 RE 8 A3 MESSAGE C TE 9 INDICATES AN ADDRESS CHARACTER N2 10 ILIE DSP56002 SCI PORT ADDRESS 2 XMIT TIE 12 IDLE LINE WAKEUP AND/OR INTERRUPT TMIE ADDRESS CHARACTER WAKEUP AND/OR INTERRUPT X:$FFF0 14 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) 6 - 59 6 - 60 STIR SCKP MESSAGE A A1 TE 9 RE 8 WOMS 7 RWU 1 6 WAKE 0 5 A2 SBK 4 For More Information On This Product, Go to: www.freescale.com PORT C FE R8 PE 5 OR 4 1 0 (READ ONLY) 1 Figure 6-32 Idle Line Wakeup SCI IDLE LINE INTERRUPT VECTOR TABLE MESSAGE B P:$001A RDRF TDRE TRNE SCI STATUS REGISTER (SSR) 2 IDLE (SRIINT) 1 3 4. IF ILIE = 1 IN SCR, THEN AN SCI IDLE LINE INTERRUPT IS PENDING. 5. WHEN IDLE LINE INTERRUPT IS ACCEPTED, SRIINT IS AUTOMATICALLY CLEARED. X:$FFF1 6 7 2 SSFTD WDS2 WDS1 3 1. RWU IS CLEARED; THE RECEIVER IS ENABLED. 2. IDLE IS SET IN SSR, INDICATING THE LINE IS IDLE. 3. AN INTERNAL FLAG SRIINT IS GENERATED ONCE EACH IDLE STATE, NO MATTER HOW LONG IT LASTS. ILIE RIE 10 1 11 1 TIE 12 TMIE 13 LINE IS IDLE FOR 10 OR 11 STOP BITS X:$FFF0 14 15 0 WDS0 Freescale Semiconductor, Inc... IDLE LINE INTERRUPT SERVICE ROUTINE (FAST OR LONG) SCI CONTROL REGISTER (SCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) If ILIE is set, an SCI idle line interrupt will be recognized as pending. When the idle line MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... interrupt is recognized (5), SRIINT is automatically cleared, and the SCI waits for the first start bit of the next character. Since RIE was set, when the first character is received, an SCI receive data interrupt (or SCI receive data with exception status interrupt if an error is detected) will be recognized as pending. When the receiver has processed the message and is ready to wait for another idle line, RWU must be set to one again. 6.3.8.4 Address Mode Wakeup The purpose and basic operational procedure for address mode wakeup is the same as idle line wakeup. The difference is that address mode wakeup re-enables the SCI when the ninth bit in a character is set to one (if cleared, this bit marks a character as data; if set, an address). As a result, an idle line is not needed, which eliminates the dead time between messages. If the protocol is such that the address byte is not needed or is not wanted in the first byte of the message, a data byte can be written to STXA at the beginning of each message. It is not essential that the first byte of the message contain an address; it is essential that the start of a new message is indicated by setting the ninth bit to one using STXA. Figure 6-33 shows how to configure the SCI to detect and respond to an address character. The word format chosen (WDS2, WDS1, and WDS0 in the SCR) must be an asynchronous word format. The WAKE bit must be set to select address mode wakeup and RWU must be set to put the SCI to “sleep” and enable the wakeup function. RIE should be set if interrupts are to be used to receive data. (1) When an address character (ninth bit=1) is received, then R8 is set to one in the SSR, and RWU is cleared. Clearing RWU re-enables the SCI receiver. Since (2) RIE was set in this example, when the first character is received, an SCI receive data interrupt (or SCI receive data with exception status interrupt if an error is detected) will be recognized as pending. When the receiver is ready to wait for another address character, RWU must be set to one again. 6.3.8.5 Multidrop Example The program shown in Figure 6-34 configures the SCI as a multidrop master transmitter and slave receiver (using wakeup on address bit) that uses interrupts to transmit data from a circular buffer and to receive data into a different circular buffer. This program can be run with the I/O pins (RXD and TXD) connected and with a pullup resistor for test purposes. The program starts by setting equates for convenience and clarity and then points the reset vector to the start of the program. The receive and transmit interrupt vector locations have JSRs forming long interrupts because the multidrop protocol and circular buffers require more than two instructions for maintenance. Byte packing and unpacking are not used in this example. The SRX and STX registers are equated to $FFF4, causing only the LSB of the 24-bit DSP word to be used for SCI data. The SCI is then initialized as wired-OR, multidrop, and using interrupts. The SCI MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 61 6 - 62 STIR SCKP A1 TMIE 13 1 11 A2 RIE MESSAGE A TIE 12 TE 9 MESSAGE B ILIE 10 A3 RE 8 MESSAGE C WOMS 7 A4 RWU 1 6 SBK 4 MESSAGE D WAKE 1 5 2 SSFTD WDS2 3 For More Information On This Product, Go to: www.freescale.com PORT C R8 1 FE PE OR 1 RDRF TDRE TRNE 0 Figure 6-33 Address Mode Wakeup P:$0014 SCI STATUS REGISTER (SSR) (READ ONLY) 2. IF RIE = 1 IN SCR, THEN AN SCI RECEIVE DATA INTERRUPT IS PROCESSED. 7 0 WDS1 WDS0 1 SCI RECEIVE DATA INTERRUPT VECTOR TABLE 1. WHEN ADDRESS CHARACTER IS RECEIVED, THEN R8 = 1 IN SSR AND RWU IS CLEARED. THE RECEIVER WAKES UP. X:$FFF1 X:$FFF0 14 15 Freescale Semiconductor, Inc... RECEIVE DATA INTERRUPT SERVICE ROUTINE (FAST OR LONG) SCI CONTROL REGISTER (SCR) (READ/WRITE) Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) is enabled but the interrupts are masked, which prevents the SCI from transmitting or receiving data at this time. Freescale Semiconductor, Inc... The circular buffers used have two pointers. The first points to the first data byte; the second points to the last data byte. This configuration allows the transmit buffer to act as a first-in first-out (FIFO) memory. The FIFO can be loaded by a program and emptied by the SCI in real time. As long as the number of data bytes never exceeds the buffer size, there will be no overflow or underflow of the buffer. Registers M0-M3 must be loaded with the buffer size minus one to make pointer registers R0-R3 work as circular pointers. Register N2 is used as a constant to clear the receive buffer empty flag. The main program starts by filling the transmit buffer with a data packet. When the transmit buffer is full, it calls the subroutine that transmits the slave’s address and then jumps to self (SEND jmp SEND), allowing interrupts to transmit and receive the data. The receive subroutine first checks each byte to see if it is address or data. If it is an address, it compares the address with its own. If the addresses do not match, the SCI is put back to sleep. If the addresses match, the SCI is left awake, and control is returned to the main program. If the byte is data, it is placed in the receive buffer, and the receive buffer empty flag is cleared. Although this flag is not used in this program, it can be used by another program as a simple test to see if data is available. Using N2 as the constant $0 allows the flag to be cleared with a single-word instruction, which can be part of a fast interrupt. The transmit subroutine transmits a byte and then checks to see if the transmit buffer is empty. If the buffer is not empty, control is returned to the main program, and interrupts are allowed to continue emptying the buffer. If the buffer is empty, the transmit buffer empty flag is set, the transmit interrupt is disabled, and control is returned to the main program. The wakeup subroutine transmits the slave’s address by writing the address to the STXA register and by enabling the transmit interrupt to allow interrupts to empty the transmit buffer. Control is then returned to the main program. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 63 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) ;******************************************************************************************* ; MULTIDROP MASTER/SLAVE WITH INTERRUPTS AND CIRCULAR BUFFERS* Freescale Semiconductor, Inc... ;******************************************************************************************* ;************************************************* ; SCI and other EQUATES* ;************************************************* START EQU $0040 ;Start of program TX_BUFF EQU $0010 ;Transmit buffer location RX_BUFF EQU $0020 ;Receive buffer location B_SIZE EQU $000E ;Transmit and receive buffer size ;(don’t allow the TX buffer and RX ;buffers to overlap). TX_MTY EQU $0000 ;Transmit buffer empty RX_MTY EQU $0001 ;Receive buffer empty PCC EQU $FFE1 ;Port C control register SCR EQU $FFF0 ;SCI interface control register SCCR EQU $FFF2 ;SCI clock control register STXA EQU $FFF3 ;SCI transmit address register SRX EQU $FFF4 ;SCI receive register STX EQU $FFF4 ;SCI transmit register BCR EQU $FFFE ;Bus control register IPR EQU $FFFF ;Interrupt priority register ;************************************************* ; RESET VECTOR* ;************************************************* ORG P:$0000 JMP START ;************************************************* ; SCI RECEIVE INTERRUPT VECTOR* ;************************************************* ORG P:$0014 ;Load the SCI RX interrupt vectors JSR RX ;Jump to the receive routine that puts ;data packet in a circular buffer if it is for ;this address. NOP ;Second word of fast interrupt not needed Figure 6-34 Multidrop Transmit Receive Example (Sheet 1 of 4) 6 - 64 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) ;This interrupt occurs when data is ;received with errors. This example NOP ;does not trap errors so this NOP ;interrupt is not used. ;************************************************* ; SCI TRANSMIT INTERRUPT VECTOR* Freescale Semiconductor, Inc... ORG P:$0016 ;************************************************* ORG P:$0018 ;Load the SCI TX interrupt vectors JSR TX ;Transmit next byte in buffer NOP ;************************************************* ; INITIALIZE THE SCI PORT* ;************************************************* ORG P:START ORI #$03,MR MOVEP #$C000,X:IPR MOVEP #$0BE6,X:SCR MOVEP #$0000,X:SCCR MOVEP #>$03,X:PCC ;Start the program at location $40 ;Mask interrupts temporarily ;Set interrupt priority to 2 ;Disable TX, enable RX interrupts ;Enable transmitter and receiver, ;Wired-OR mode, Rec. wakeup ;mode,11-bit multidrop (1 start, ;8 data,1 data type, 1 stop) ;Use internal TX, RX clocks ;625K BPS at 40 MHz ;Select pins TXD and RXD for SCI ;************************************************** ;INITIALIZE INTERRUPTS, REGISTERS, ETC.* ;************************************************** MOVEP #$0,X:BCR MOVE #TX_BUFF,R0 MOVE #TX_BUFF,R1 MOVE #RX_BUFF,R2 MOVE #RX_BUFF,R3 MOVE #>$41,R5 ;No wait states ;Load start pointer of transmit buffer ;Load end pointer of transmit buffer ;Load start pointer of receive buffer ;Load end pointer of receive buffer ;Init data register... R5 contains ;the data that will be sent in this ;example; it is initialized to an ASCII A. Figure 6-34 Multidrop Transmit Receive Example (Sheet 2 of 4) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 65 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... MOVE MOVE MOVE MOVE MOVE MOVE MOVE MOVEP #B_SIZE,M0 #B_SIZE,M1 #B_SIZE,M2 #B_SIZE,M3 #>$1,N0 #>$1,N1 #0,N2 X:SRX,X:(R0) ;Load transmit buffer size ;Load transmit buffer size ;Load receive buffer size ;Load receive buffer size ;Load receive address ;Load first slave address ;Load a constant (0) into N2 ;Clear receive register ;************************************************** ; MAIN PROGRAM* ;************************************************** ANDI #$FC,MR MOVE (R1)+ LOOP SND_BUF SEND MOVE MOVE MOVE CMP JEQ MOVE R1,A (R1)R0,B A,B SND_BUF R5,X:(R1)+ MOVE MOVE (R5)+ (R1)+ JMP JSR JMP LOOP WAKE_UP SEND ;Re-enable interrupts ;Temporarily increment the tail pointer ;Build a packet ;Check to see if the TX buffer is full ;(fix tail pointer now that we’ve used it) ;by comparing the head and tail pointers ;of the circular transmit buffer. ;if equal, transmit completed packet ;if not, put next character in ;transmit buffer and ;increment the pointers. ;Temporarily increment the tail ;pointer to test buffer again ;Wake up proper slave and send packet ;and allow interrupts to drain ;the transmit buffer. Figure 6-34 Multidrop Transmit Receive Example (Sheet 3 of 4) 6 - 66 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... ;******************************************************************************************* ; SUBROUTINE TO READ SCI AND STORE IN BUFFER USING A LONG INTERRUPT* ;******************************************************************************************* RX JCLR #7,X:$FFF1,RX_DATA ;Check if this is address or data. MOVEP X:SRX,A ;Compare the received address MOVE N1,B ;with the slave address. CMP A,B JEQ END_RX ;If address OK, use interrupts to Rx ;packet BSET #6,X:$FFF0 ;if not, go back to sleep JMP END_RX ;and return to previous program. RX_DATA MOVEP X:SRX,X:(R3)+ ;Put data in buffer, MOVE N2,X:RX_MTY ;and clear the Rx buffer empty flag END_RX RTI ;Return to previous program ;******************************************************************************************* ; SUBROUTINE TO WRITE BUFFER TO SCI USING A LONG INTERRUPT* ;******************************************************************************************* TX MOVEP X:(R0)+,X:STX ;Transmit a byte and increment the ;pointer MOVE R0,A ;Check to see if the TX buffer is ;empty MOVE R1,B CMP A,B JNE END_TX ;If not, return to main MOVE #$000001,X0 ;If it is, set the TX buffer empty flag MOVE X0,X:TX_MTY BCLR #12,X:SCR ;disable transmit interrupts, and END_TX RTI ;return to main ;******************************************************************************************* ; SUBROUTINE TO WAKE UP THE ADDRESSED SLAVE* ;******************************************************************************************* WAKE_UP MOVEP N1,X:STXA ;Transmit slave address using STXA ;not STX BSET #12,X:SCR ;Enable transmit interrupts to send ;packet AWAKE RTI END ;End of example. Figure 6-34 Multidrop Transmit/Receive Example (Sheet 4 of 4) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 67 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SERIAL COMMUNICATION INTERFACE (SCI) 6.3.9 SCI Timer The SCI clock determines the data transmission rate and can also be used to establish a periodic interrupt that can act as an event timer or be used in any other timing function. Figure 6-35 illustrates how the SCI timer is programmed. Bits CD11–CD0, SCP, and STIR in the SCCR work together to determine the time base. The crystal oscillator fosc is first divided by 2 and then divided by the number CD11–CD0 in the SCCR. The oscillator is then divided by 1 (if SCP=0) or eight (if SCP=1). This output is used as is if STIR = 1 or, if STIR = 0, it is divided by 2 and then by 16 before being used. If TMIE in the SCR = 1 when the periodic timeout occurs, the SCI timer interrupt is recognized and pending. The SCI timer interrupt is automatically cleared when the interrupt is serviced. This interrupt will occur every time the periodic timer times out. If only the timer function is being used (i.e., PC0, PC1, and PC2 pins have been programmed as GPIO pins), the transmit interrupts should be turned off (TIE=0). Under individual reset, TDRE will remain set and the timer will continuously generate interrupts. Figure 6-35 shows that an external clock can be used for SCI receive and/or transmit, which frees the SCI timer to be programmed for a different interrupt rate. In addition, both the SCI timer interrupt and the SCI can use the internal time base if the SCI receiver and/or transmitter require the same clock period as the SCI timer. The program in Figure 6-36 configures the SCI to interrupt the DSP at fixed intervals. The program starts by setting equates for convenience and clarity and then points the reset vector to the start of the program. The SCI timer interrupt vector location contains “move (R0)+”, incrementing the contents of R0, which serves as an elapsed time counter. The timer initialization consists of enabling the SCI timer interrupt, setting the SCI baud rate counters for the desired interrupt rate, setting the interrupt mask, enabling the interrupt, and then enabling the SCI state machine. 6 - 68 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) SCI CONTROL REGISTER (SCCR) (READ/WRITE) X:$FFF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCM RCM SCP COD CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 1 0 PRESCALER IF SCP = 1, THEN DIVIDE BY 8 IF SCP = 0, THEN DIVIDE BY 1 Freescale Semiconductor, Inc... DIVIDE BY 2 DIVIDE BY 1 TO 4096 DIVIDE BY 2 fosc SCKP OUTPUT DIVIDER IF SYNC, THEN DIVIDE BY 2 IF ASYNC THEN: COD = 1, DIVIDE BY 1 COD = 0, DIVIDE BY 16 COD I N T E R N A L SCLK SCKP E X T E R N A L RCM TCM TCM TRANSMIT CONTROL IF ASYNC, THEN DIVIDE BY 16 IF SYNC THEN: MASTER, DIVIDE BY 2 SLAVE, DIVIDE BY 1 C L O C K PERIODIC TIMER DIVIDE BY 16 1 TRANSMIT CLOCK C L O C K 0 RECEIVE CONTROL IF ASYNC, THEN DIVIDE BY 16 IF SYNC THEN: MASTER, DIVIDE BY 2 SLAVE, DIVIDE BY 1 1 RECEIVE CLOCK 0 SCI CONTROL REGISTER (SCR) (READ/WRITE) X:$FFF0 15 14 13 12 11 10 9 8 0 0 1 TIE RIE ILIE TE RE SCKP STIR TMIE 7 WOMS 6 5 4 3 RWU WAKE SBK 0 2 WDS2 WDS1 WDS0 SSFTD 1. WHEN PERIODIC TIMEOUT OCCURS AND TMIE = 1 IN SCR, THEN AN SCI TIMER EXCEPTION IS TAKEN. INTERRUPT VECTOR TABLE P:$001C SCI TIMER INTERRUPT SERVICE ROUTINE (FAST OR LONG) SCI TIMER 2. PENDING TIMER INTERRUPT IS AUTOMATICALLY CLEARED WHEN INTERRUPT IS SERVICED. Figure 6-35 SCI Timer Operation MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 69 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) ;******************************************************************************************* ; TIMER USING SCI TIMER INTERRUPT* ;******************************************************************************************* Freescale Semiconductor, Inc... ;************************************************* ; SCI and other EQUATES* ;************************************************* START EQU $0040 ;Start of program SCR EQU $FFF0 ;SCI control register SCCR EQU $FFF2 ;SCI clock control register IPR EQU $FFFF ;Interrupt priority register ;************************************************* ; RESET VECTOR* ;************************************************* ORG P:$0000 JMP START ;************************************************* ; SCI TIMER INTERRUPT VECTOR* ;************************************************* ORG P:$001C ;Load the SCI timer interrupt vectors MOVE (R0)+ ;Increment the timer interrupt counter NOP ;This timer routine is implemented ;as a fast interrupt ;************************************************* ; INITIALIZE THE SCI PORT* ;************************************************* ORG P:START ;Start the program at location $40 MOVE #0,R0 ;Initialize the timer interrupt counter MOVEP #$2000,X:SCR ;Select the timer interrupt MOVEP #$013F,X:SCCR;Set the interrupt rate at 1 ms ;(arbitrarily chosen) ;Interrupts/second = ;fosc/(64×(7(SCP)-+1)×(CD+1)) ;Note that this is the same equation ;as for SCI async baud rate Figure 6-36 SCI Timer Example (Sheet 1 of 2) 6 - 70 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) END MOVEP #$C000,X:IPR ANDI #$FC,MR JMP END Freescale Semiconductor, Inc... END ;For 1 ms, SCP=0, ;CD=0001 0011 1111. ;Set the interrupt priority level– ;application specific. ;Enable interrupts, set MR bits I1 and ;I0=0 ;Normally something more useful ;would be put here. ;End of example. Figure 6-36 SCI Timer Example (Sheet 2 of 2) 6.3.10 Bootstrap Loading Through the SCI (Operating Mode 6) When the DSP comes out of reset, it looks at the MODC, MODB, and MODA pins and sets the corresponding mode bits in the OMR. If the mode bits are set to 110 respectively, the DSP will load the program RAM from the SCI. Figure 6-37 shows how the SCI is configured for receiving this code and Figure 6-37 shows the segment of bootstrap code that is used to load from the SCI. The complete code used in the bootstrap program is given in APPENDIX A. This program (1) configures the SCI, (2) loads the program size, (3) loads the location where the program will begin loading in program memory, and (4) loads the program. First, the SCI Control Register is set to $0302 (see Figure 5-2) which enables the transmitter and receiver and configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit, and no parity. Next, the SCI Clock Control Register is set to $C000 which configures the SCI to use external receive and transmit clocks on the SCLK pin. This clock must be 16 times the serial data rate. The next step is to receive the program size and then the starting address to load the program. These two numbers are three bytes each loaded least significant byte first. Each byte will be echoed back as it is received. After both numbers are loaded, the program size is in A0 and the starting address is in A1. The program is then loaded one byte at a time, least significant byte first. After loading the program, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution with the first instruction that was loaded. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 71 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) +5 V DSP56002 DR BR HACK WT MODA/IRQA FROM OPEN COLLECTOR BUFFER MODC/NMI Freescale Semiconductor, Inc... MBD301* MBD301* FROM RESET FUNCTION Serial Bootstrap Loader (1 start, 8 data, 1 stop, no parity, LSB first) RXD TXD SCLK 16xCLK RESET MBD301* FROM OPEN COLLECTOR BUFFER MODB/IRQB Notes: 1. *These diodes must be Schottky diodes. 2. All resistors are 15KΩ unless noted otherwise. 3. When in RESET, IRQA, IRQB and NMI must be deasserted by external peripherals. Figure 6-37 DSP56002 Bootstrap Example - Mode 6 6 - 72 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... ; This routine loads from the SCI. ; MC:MB:MA=110 - external SCI clock ; MC:MB:MA=111 - reserved SCILD MOVEP #$0302,X:SCR JMP <EXTC NOP ; Configure SCI Control Reg ; go to next boot rom segment ; just to fill the last space ORG PL:$100,PL:$100 ; starting address of 2nd ROM EXTC MOVEP MOVEP #$C000,X:SCCR #7,X:PCC ; Configure SCI Clock Control Reg ; Configure SCLK, TXD and RXD _SCI1 DO #6,_LOOP6 JCLR MOVEP JCLR MOVEP REP ASR #2,X:SSR,* X:SRXL,A2 #1,X:SSR,* A2,X:STXL #8 A ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address ; Wait for RDRF to go high ; Put 8 bits in A2 ; Wait for TDRE to go high ; echo the received byte MOVE MOVE DO A1,R0 A1,R1 A0,_LOOP4 DO JCLR MOVEP JCLR MOVEP REP ASR #3,_LOOP5 #2,X:SSR,* X:SRXL,A2 #1,X:SSR,* A2,X:STXL #8 A MOVEM A1,P:(R0)+ _LOOP6 ; starting address for load ; save starting address ; Receive program words ; Wait for RDRF to go high ; Put 8 bits in A2 ; Wait for TDRE to go high ; echo the received byte _LOOP5 ; Store 24-bit result in P memory _LOOP4 Figure 6-38 Bootstrap Code Fragment MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 73 Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) Freescale Semiconductor, Inc... 6.3.11 Example Circuits The SCI can be used in a number of configurations to connect multiple processors. The synchronous mode shown in Figure 6-39 shows the DSP acting as a slave. The 8051 provides the clock that clocks data in and out of the SCI, which is possible because the SCI shift register mode timing is compatible with the timing for 8051/8096 processors. Transmit data is changed on the negative edge of the clock, and receive data is latched on the positive edge of the clock. A protocol must be used to prevent both processors from transmitting simultaneously. The DSP is also capable of being the master device. A multimaster system can be configured (see Figure 6-41) using a single transmit/receive line, multidrop word format, and wired-OR. The use of wired-OR requires a pullup resistor as shown. A protocol must be used to prevent collisions. This scheme is physically the simplest multiple DSP interconnection because it uses only one wire and one resistor. The master-slave system shown in Figure 6-40 is different in that it is full duplex. The clock pin is not required; thus, it is configured as a GPIO pin. Communication is asynchronous. The slave’s transmitters must be wire-ORed because more than one transmitter is on one line. The master’s transmitter does not need to be wire-ORed. CLOCK INPUT 1.5 Ccyc TRANSMIT DATA RECEIVE DATA B0 XXXXXX SAMPLE B1 XX 0 B2 XX 1 B3 XX 2 B4 XX 3 B5 XX 4 B6 XX 5 DSP56002 B7 XX 6 XXXXXXX 7 8051 P3.0 RXD TXD P3.1 SCLK Figure 6-39 Synchronous Mode Example 6 - 74 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SERIAL COMMUNICATION INTERFACE (SCI) MASTER RECEIVE MASTER TRANSMIT Freescale Semiconductor, Inc... MC68HC11 MASTER DSP56002 SLAVE DSP56002 SLAVE DSP56002 SLAVE RXD RXD RXD RXD TXD TXD TXD TXD PC2 PC2 PC2 PC2 Figure 6-40 Master-Slave System Example DSP56002 MASTER DSP56002 MASTER TXD TXD RXD RXD PC2 PC2 Figure 6-41 Multimaster System Example MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 75 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6.4 SYNCHRONOUS SERIAL INTERFACE (SSI) The synchronous serial interface (SSI) provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola SPI. Freescale Semiconductor, Inc... The user can independently define the following characteristics of the SSI: the number of bits per word, the protocol, the clock, and the transmit/receive synchronization. The user can select among three modes: normal, on-demand, and network. The normal mode is typically used to interface with devices on a regular or periodic basis. The data-driven on-demand mode is intended to be used to communicate with devices on a nonperiodic basis. The network mode provides time slots in addition to a bit clock and frame synchronization pulse. The SSI functions with a range of 2 to 32 words of I/O per frame in the network mode. This mode is typically used in star or ring time division multiplex networks with other DSP56K processors and/or codecs. The clock can be programmed to be continuous or gated. Since the transmitter and receiver sections of the SSI are independent, they can be programmed to be synchronous (using a common clock) or asynchronous with respect to each other. The SSI requires up to six pins, depending on its operating mode. The most common minimum configuration is three pins: transmit data (STD), receive data (SRD) and clock (SCK). The SSI consists of independent transmitter and receiver sections and a common SSI clock generator. Three to six pins are required for operation, depending on the operating mode selected. The following is a short list of SSI features: • Three-Pin Interface: TXD – Transmit Data RXD – Receive Data SCLK – Serial Clock • A 10 Mbps at 40 MHz (fosc/4) serial interface • Double Buffered • User Programmable • Separate Transmit and Receive Sections • Control and Status Bits 6 - 76 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SYNCHRONOUS SERIAL INTERFACE (SSI) • Interface to a Variety of Serial Devices, Including: Codecs (usually without additional logic) MC145502 MC145503 MC145505 MC145402 (13-bit linear codec) MC145554 Family of Codecs MC145532 Serial Peripherals (A/D, D/A) Most Industry-Standard A/D, D/A DSP56ADC16 (16-bit linear A/D) DSP56K to DSP56K Networks Motorola SPI Peripherals and Processors Shift Registers • Interface to Time Division Multiplexed Networks without Additional Logic • Six Pins: STD SSI Transmit Data SRD SSI Receive Data SCK SSI Serial Clock SC0 Serial Control 0 (defined by SSI mode) SC1 Serial Control 1 (defined by SSI mode) SC2 Serial Control 2 (defined by SSI mode) • On-chip Programmable Functions Include: Clock – Continuous, Gated, Internal, External Synchronization Signals – Bit Length and Word Length TX/RX Timing – Synchronous, Asynchronous Operating Modes – Normal, Network, On-Demand Word Length – 8, 12, 16, 24 Bits Serial Clock and Frame Sync Generator • Four Interrupt Vectors: Receive Receive with Exception Transmit Transmit with Exception MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 77 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... This interface is descriptively named “synchronous” because all serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, but only one word per period. The network mode is similar in that it is also intended for periodic transfers; however, it will support up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for nonperiodic transfers of data. This mode can be used to transfer data serially at high speed when the data becomes available. This mode offers a subset of the SPI protocol. 6.4.1 SSI Data and Control Pins The SSI has three dedicated I/O pins (see Figure 6-1), which are used for transmit data (STD), receive data (SRD), and serial clock (SCK), where SCK may be used by both the transmitter and the receiver for synchronous data transfers or by the transmitter only for asynchronous data transfers. Three other pins may also be used, depending on the mode selected; they are serial control pins SC0, SC1, and SC2. They may be programmed as SSI control pins in the Port C control register. Table 6-5 shows the definition of SC0, SC1, SC2, and SCK in the various configurations. The following paragraphs describe the uses of these pins for each of the SSI operating modes. Figure 6-42 and Figure 6-43 show the internal clock path connections in block diagram form. The receiver and transmitter clocks can be internal or external depending on the SYN, SCD0, and SCKD bits in CRB. 6.4.1.1 Serial Transmit Data Pin (STD) STD is used for transmitting data from the serial transmit shift register. STD is an output when data is being transmitted. Data changes on the positive edge of the bit clock. STD goes to high impedance on the negative edge of the bit clock of the last data bit of the word (i.e., during the second half of the last data bit period) with external gated clock, regardless of the mode. With an internally generated bit clock, the STD pin becomes high impedance after the last data bit has been transmitted for a full clock period, assuming another data word does not follow immediately. If a data word follows immediately, there will not be a high-impedance interval. Codecs label the MSB as bit 0; whereas, the DSP labels the LSB as bit 0. Therefore, when using a standard codec, the DSP MSB (or codec bit 0) is shifted out first when SHFD=0, and the DSP LSB (or codec bit 7) is shifted out first when SHFD=1. STD may be programmed as a general-purpose pin called PC8 when the SSI STD function is not being used. 6 - 78 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-5 Definition of SC0, SC1, SC2, and SCK Freescale Semiconductor, Inc... Asynchronous (SYN=0) SSI Pin Name (Control Bit Name) Continuous Clock Gated Clock (GCK=0) (GCK=1) Synchronous (SYN=1) Continuous Clock (GCK=0) Gated Clock (GCK=1) SC0=0 (in) RXC External RXC External Input F0 Input F0 SC0=1 (out) (SCD0) RXC Internal RXC Internal Output F0 Output F0 SC1=0 (in) FSR External Not Used Input F1 Input F1 SC1=1 (out) (SCD1) FSR Internal FSR Internal Output F1 Output F1 SC2=0 (in) FST External Not Used FS* External Not Used SC2=1 (out) (SCD2) FST Internal FST Internal FS* Internal FS* Internal SCK=0 (in) TXC External TXC External *XC External *XC External SCK=1 (out (SCKD) TXC Internal TXC Internal) *XC Internal *XC Internal TXC – Transmitter Clock RXC – Receiver Clock *XC – Transmitter/Receiver Clock (synchronous operation) FST – Transmitter Frame Sync FSR – Receiver Frame Sync FS* – Transmitter/Receiver Frame Sync (synchronous operation) F0 – Flag 0 F1 – Flag 1 Table 6-6 SSI Clock Sources, Inputs, and Outputs SYN SCKD SCD0 R Clock Source RX Clock Out T Clock Source TX Clock Out Asynchronous 0 0 0 EXT, SC0 – EXT, SCK – 0 0 1 INT SC0 EXT, SCK – 0 1 0 EXT, SC0 – INT SCK 0 1 1 INT SC0 INT SCK Synchronous 1 0 0 EXT, SCK – EXT, SCK – 1 0 1 EXT, SCK – EXT, SCK – 1 1 0 INT SCK INT SCK 1 1 1 INT SCK INT SCK EXT – External Pin Name INT – Internal Bit Clock MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 79 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) FLAG0 OUT (SYNC MODE) FLAG0 IN (SYNC MODE) WL1, WL0 RX WORD CLOCK RX WORD LENGTH DIVIDER SCD0 = 0 SYN = 1 SYN = 0 SC0 RX SHIFT REGISTER RCLOCK SYN = 0 SCD0 = 1 Freescale Semiconductor, Inc... SCD0 SYN = 1 INTERNAL BIT CLOCK SCK WL1, WL0 TCLOCK TX WORD LENGTH DIVIDER TX WORD CLOCK SCKD TX SHIFT REGISTER DIVIDE BY 2 FOSC PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 PSR PM0 - PM7 DIVIDE BY 2 Figure 6-42 SSI Clock Generator Functional Block Diagram 6.4.1.2 Serial Receive Data Pin (SRD) SRD receives serial data and transfers the data to the SSI receive shift register. SRD may be programmed as a general-purpose I/O pin called PC7 when the SSI SRD function is not being used. Data is sampled on the negative edge of the bit clock. 6.4.1.3 Serial Clock (SCK) SCK is a bidirectional pin providing the serial bit rate clock for the SSI interface. The SCK is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes (see Table 6-6). Note: Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 8T (i.e., the system clock frequency must be at least four times the external SSI clock frequency). The SSI needs at least four DSP phases (DSP phase=T) inside each half of the serial clock. 6 - 80 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) RX WORD CLOCK DC0 - DC4 FSL0, FSL1 RECEIVER FRAME RATE DIVIDER SYNC TYPE INTERNAL RX FRAME CLOCK SCD1 SCD1 = 1 SYN = 0 SYN = 0 RECEIVE CONTROL LOGIC SC1 RECEIVE FRAME SYNC SCD1 = 0 SYN = 1 Freescale Semiconductor, Inc... SYN = 1 DC0 - DC4 FSL0, FSL1 FLAG1 IN (SYNC MODE) FLAG1OUT (SYNC MODE) SCD2 TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC SYNC TYPE INTERNAL TX FRAME CLOCK SC2 TRANSMIT FRAME SYNC Figure 6-43 SSI Frame Sync Generator Functional Block Diagram MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 81 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.1.4 Serial Control Pin (SC0) The function of this pin is determined solely on the selection of either synchronous or asynchronous mode (see Table 6-5 and Table 6-6). For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used for serial flag I/O. A typical application of flag I/O would be multiple device selection for addressing in codec systems. The direction of this pin is determined by the SCD0 bit in the CRB as described in Table 6-7. When configured as an output, this pin will be either serial output flag 0, based on control bit OF0 in CRB, or a receive shift register clock output. When configured as an input, this pin may be used either as serial input flag 0, which will control status bit IF0 in the SSISR, or as a receive shift register clock input. Table 6-7 SSI Operation: Flag 0 and Rx Clock SYN GCK SCD0 Operation Synchronous Continuous Input Flag 0 Input Synchronous Continuous Output Flag 0 Output Synchronous Gated Input Flag 0 Input Synchronous Gated Output Flag 0 Output Asynchronous Continuous Input Rx Clock – External Asynchronous Continuous Output Rx Clock – Internal Asynchronous Gated Input Rx Clock – External Asynchronous Gated Output Rx Clock – Internal 6.4.1.5 Serial Control Pin (SC1) The function of this pin is determined solely on the selection of either synchronous or asynchronous mode (see Table 6-5 and Table 6-8). In asynchronous mode (such as a single codec with asynchronous transmit and receive), this pin is the receiver frame sync I/O. For synchronous mode with continuous clock, this pin is serial flag SC1 and operates like the previously described SC0. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC0 and SC1 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs. The direction of this pin is determined by the SCD1 bit in the CRB. When configured as an output, this pin will be either a serial output flag, based on control bit OF1, or it will make the receive frame sync signal available. When configured as an input, this pin may be used as a serial input flag, which will control status bit IF1 in the SSI status register, or as a receive frame sync from an external source for continuous clock mode. In the gated clock mode, external frame sync signals are not used. 6 - 82 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... Table 6-8 SSI Operation: Flag 1 and Rx Frame Sync SYN GCK SCD1 Operation Synchronous Continuous Input Flag 1 Input Synchronous Continuous Output Flag 1 Output Synchronous Gated Input Flag 1 Input Synchronous Gated Output Flag 1 Output Asynchronous Continuous Input RX Frame Sync – External Asynchronous Continuous Output RX Frame Sync – Internal Asynchronous Gated Input – Asynchronous Gated Output RX Frame Sync – Internal 6.4.1.6 Serial Control Pin (SC2) This pin is used for frame sync I/O (see Table 6-5 and Table 6-9). SC2 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. The direction of this pin is determined by the SCD2 bit in CRB. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). In the gated clock mode, external frame sync signals are not used. Table 6-9 SSI Operation: Tx and Rx Frame Sync SYN GCK SCD2 Operation Synchronous Continuous Input TX and RX Frame Sync Synchronous Continuous Output TX and RX Frame Sync Synchronous Gated Input – Synchronous Gated Output TX and RX Frame Sync Asynchronous Continuous Input TX Frame Sync – External Asynchronous Continuous Output TX Frame Sync – Internal Asynchronous Gated Input – Asynchronous Gated Output TX Frame Sync – Internal 6.4.2 SSI Programming Model The SSI can be viewed as two control registers, one status register, a transmit register, a receive register, and special-purpose time slot register. These registers are illustrated in Figure 6-44 and Figure 6-45. The following paragraphs give detailed descriptions and operations of each of the bits in the SSI registers. The SSI registers are not prefaced with an “S” (for serial) as are the SCI registers. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 83 6 - 84 13 WL0 (0) 14 TIE (0) 15 RIE (0) For More Information On This Product, Go to: www.freescale.com PORT C 12 12 10 DC2 (0) 11 10 9 TDE (1) RDF (0) X:$FFEE 6 SYN (0) • 7 GCK (0) • MOD (0) 9 DC1 (0) X:$FFEE TE (0) 11 DC3 (0) FRAME RATE DIVIDER CONTROL DC4 (0) 8 7 7 5 SHFD (0) 6 4 5 RFS (0) 3 PM3 (0) 4 SCD2 (0) 3 SCD1 (0) 2 SCD0 (0) 2 PM2 (0) 1 OF1 (0) 1 PM1 (0) 0 OF0 (0) 0 PM0 (0) TFS (0) • 2 IF0 (0) • 0 Figure 6-44 SSI Programming Model — Control and Status Registers TRANSMITTER UNDERRUN ERROR FLAG RECEIVE FRAME SYNC SSI STATUS REGISTER (SSISR) (READ) SSI TIME SLOT REGISTER (TSR) (WRITE) SSI CONTROL REGISTER B (CRB) (READ/WRITE) SSI CONTROL REGISTER A (CRA) (READ/WRITE) TRANSMIT FRAME SYNC INPUT FLAGS IF1 (0) • 1 GATED CLOCK CONTROL SYNC/ASYNC CONTROL FRAME SYNC LENGTH (BIT/WORD) FRAME SYNC LENGTH 0 (MIXED BIT/WORD) SHIFT DIRECTION SERIAL CONTROL DIRECTION OUTPUT FLAGS SCKD (0) RESET VALUE = $40 TUE (0) • 3 4 PM4 (0) PRESCALE MODULUS SELECT PM5 (0) RESET VALUE = $0000 FSL0 (0) • 6 PM6 (0) RESET VALUE = $0000 PM7 (0) RECEIVER OVERRUN ERROR FLAG ROE (0) • 5 FSL1 (0) 8 DC0 (0) TRANSMIT DATA REGISTER EMPTY RECEIVE DATA REGISTER FULL MODE SELECT (NETWORK/NORMAL) TRANSMITTER ENABLE RECEIVER ENABLE TRANSMIT INTERRUPT ENABLE RE (0) 13 WORD-LENGTH CONTROL RECEIVE INTERRUPT ENABLE X:$FFED PRESCALE RANGE X:$FFEC 14 WL1 (0) 15 PSR (0) Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 23 16 15 X:$FFEF RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE 7 0 23 SERIAL RECEIVE SHIFT REGISTER 8 7 0 SERIAL RECEIVE DATA (RX) REGISTER (READ ONLY) RECEIVE LOW BYTE 7 0 7 16 15 0 8 7 RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE 0 RECEIVE LOW BYTE 24 BIT 7 0 7 0 7 0 16 BIT 12 BIT SRD Freescale Semiconductor, Inc... 8 BIT WL1, WL0 MSB LSB 8-BIT DATA 0 MSB 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 12-BIT DATA LSB MSB 16-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received MSB first if SHFD = 0. 2. Compatible with fractional format. (a) Receive Registers for SHFD = 0 SERIAL RECEIVE SHIFT REGISTER 23 X:$FFEF 16 15 TRANSMIT HIGH BYTE 7 TRANSMIT MIDDLE BYTE 0 23 0 7 16 15 7 MSB 7 0 0 7 0 MSB SERIAL TRANSMIT SHIFT REGISTER TRANSMIT LOW BYTE 0 LSB 8-BIT DATA SERIAL TRANSMIT DATA (TX) REGISTER (WRITE ONLY) 0 8 7 TRANSMIT MIDDLE BYTE 0 0 TRANSMIT LOW BYTE 7 TRANSMIT HIGH BYTE STD 8 7 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 12-BIT DATA LSB MSB 16-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is sent MSB first if SHFD = 0. 2. Compatible with fractional format. (b) Transmit Registers for SHFD = 0 Figure 6-45 SSI Programming Model (Sheet 1 of 2) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 85 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 23 16 15 X:$FFEF RECEIVE HIGH BYTE RECEIVE MIDDLE BYTE 7 0 23 16 15 7 RECEIVE HIGH BYTE SRD 0 7 SERIAL RECEIVE DATA (RX) REGISTER (READ ONLY) 0 7 0 8 7 0 RECEIVE LOW BYTE 0 7 SERIAL RECEIVE SHIFT REGISTER 0 LSB 8-BIT DATA 0 MSB Freescale Semiconductor, Inc... 0 RECEIVE LOW BYTE RECEIVE MIDDLE BYTE 7 MSB 8 7 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 12-BIT DATA LSB MSB 16-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received LSB first if SHFD = 1. 2. Compatible with fractional format. (c) Receive Registers for SHFD = 1 23 X:$FFEF 16 15 TRANSMIT HIGH BYTE 8 7 TRANSMIT MIDDLE BYTE 0 SERIAL TRANSMIT DATA (TX) REGISTER (READ ONLY) TRANSMIT LOW BYTE 7 0 7 0 7 0 23 16 15 8 7 0 TRANSMIT HIGH BYTE 7 TRANSMIT MIDDLE BYTE 0 7 TRANSMIT LOW BYTE 0 7 SERIAL TRANSMIT/SHIFT REGISTER 0 24 BIT 16 BIT 12 BIT STD 8 BIT WL1, WL0 MSB LSB 8-BIT DATA 0 MSB 0 LEAST SIGNIFICANT ZERO FILL 0 LSB 12-BIT DATA LSB MSB 16-BIT DATA MSB LSB 24-BIT DATA NOTES: 1. Data is received LSB first if SHFD = 1. 2. Compatible with fractional format. (d) Transmit Registers for SHFD = 1 Figure 6-45 SSI Programming Model (Sheet 2 of 2) 6 - 86 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.1 SSI Control Register A (CRA) CRA is one of two 16-bit read/write control registers used to direct the operation of the SSI. The CRA controls the SSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The high-order bits of CRA are read as zeros by the DSP CPU. The CRA control bits are described in the following paragraphs. 6.4.2.1.1 CRA Prescale Modulus Select (PM7–PM0) Bits 0–7 The PM0–PM7 bits specify the divide ratio of the prescale divider in the SSI clock generator. A divide ratio from 1 to 256 (PM=0 to $FF) may be selected. The bit clock output is available at the transmit clock (SCK) and/or the receive clock (SC0) pins of the DSP. The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be generated. Hardware and software reset clear PM0–PM7. 6.4.2.1.2 CRA Frame Rate Divider Control (DC4–DC0) Bits 8–12 The DC4–DC0 bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks (see Figure 6-43). In network mode, this ratio may be interpreted as the number of words per frame minus one. In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (DC=00000 to 11111) for normal mode and 2 to 32 (DC=00001 to 11111) for network mode. A divide ratio of one (DC=00000) in network mode is a special case (see 6.4.7.4). In normal mode, a divide ratio of one (DC=00000) provides continuous periodic data word transfers. A bit-length sync (FSL1=1, FSL0=0) must be used in this case. Hardware and software reset clear DC4–DC0. 6.4.2.1.3 CRA Word Length Control (WL0, WL1) Bits 13 and 14 The WL1 and WL0 bits are used to select the length of the data words being transferred via the SSI. Word lengths of 8, 12, 16, or 24 bits may be selected according to Table 6-10. Table 6-10 Number of Bits/Word MOTOROLA WL1 WL0 Number of Bits/Word 0 0 8 0 1 12 1 0 16 1 1 24 PORT C For More Information On This Product, Go to: www.freescale.com 6 - 87 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... These bits control the number of active clock transitions in the gated clock modes and control the word length divider (see Figure 6-42 and Figure 6-43), which is part of the frame rate signal generator for continuous clock modes. The WL control bits also control the frame sync pulse length when FSL0 and FSL1 select a WL bit clock (see Figure 6-42). Hardware and software reset clear WL0 and WL1. 6.4.2.1.4 CRA Prescaler Range (PSR) Bit 15 The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired (see Figure 6-42). When PSR is cleared, the fixed prescaler is bypassed. When PSR is set, the fixed divide-by-eight prescaler is operational. This allows a 128-kHz master clock to be generated for MC14550x series codecs. The maximum internally generated bit clock frequency is fosc/4, the minimum internally generated bit clock frequency is fosc/4/8/256=fosc/8192. Hardware and software reset clear PSR. 6.4.2.2 SSI Control Register B (CRB) The CRB is one of two 16-bit read/write control registers used to direct the operation of the SSI. CRB controls the SSI multifunction pins, SC2, SC1, and SC0, which can be used as clock inputs or outputs, frame synchronization pins, or serial I/O flag pins. The serial output flag control bits and the direction control bits for the serial control pins are in the SSI CRB. Interrupt enable bits for each data register interrupt are provided in this control register. When read by the DSP, CRB appears on the two low-order bytes of the 24-bit word, and the high-order byte reads as zeros. Operating modes are also selected in this register. Hardware and software reset clear all the bits in the CRB. The relationships between the SSI pins (SC0, SC1, SC2, and SCK) and some of the CRB bits are summarized in Tables Table 6-5, Table 6-12, and Table 6-13. The SSI CRB bits are described in the following paragraphs. 6.4.2.2.1 CRB Serial Output Flag 0 (OF0) Bit 0 When the SSI is in the synchronous clock mode and the serial control direction zero bit (SCD0) is set, indicating that the SC0 pin is an output, then data present in OF0 will be written to SC0 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. Hardware and software reset clear OF0. 6.4.2.2.2 CRB Serial Output Flag 1 (OF1) Bit 1 When the SSI is in the synchronous clock mode and the serial control direction one 6 - 88 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) (SCD1) bit is set, indicating that the SC1 pin is an output, then data present in OF1 will be written to the SC1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode (see 6.4.7). Freescale Semiconductor, Inc... The normal sequence for setting output flags when transmitting data is to poll TDE (TX empty), to first write the flags, and then write the transmit data to the TX register. OF0 and OF1 are double buffered so that the flag states appear on the pins when the TX data is transferred to the transmit shift register (i.e., the flags are synchronous with the data). Hardware and software reset clear OF1. Note: The optional serial output pins (SC0, SC1, and SC2) are controlled by the frame timing and are not affected by TE or RE. 6.4.2.2.3 CRB Serial Control 0 Direction (SCD0) Bit 2 SCD0 controls the direction of the SC0 I/O line. When SCD0 is cleared, SC0 is an input; when SCD0 is set, SC0 is an output (see Tables Table 6-5 and Table 6-6, and Figure 6-46). Hardware and software reset clear SCD0. 6.4.2.2.4 CRB Serial Control 1 Direction (SCD1) Bit 3 SCD1 controls the direction of the SC1 I/O line. When SCD1 is cleared, SC1 is an input; when SCD1 is set, SC1 is an output (see Tables Table 6-5 and Table 6-6 and Figure 6-46). Hardware and software reset clear SCD1. 6.4.2.2.5 CRB Serial Control 2 Direction (SCD2) Bit 4 SCD2 controls the direction of the SC2 I/O line. When SCD2 is cleared, SC2 is an input; when SCD2 is set, SC2 is an output (see Tables Table 6-5 and Table 6-6, and Figure 6-46). Hardware and software reset clear SCD2. 6.4.2.2.6 CRB Clock Source Direction (SCKD) Bit 5 SCKD selects the source of the clock signal used to clock the transmit shift register in the asynchronous mode and both the transmit shift register and the receive shift register in the synchronous mode. When SCKD is set, the internal clock source becomes the bit clock for the transmit shift register and word length divider and is the output on the SCK pin. When SCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCK pin, and an external clock source may drive this pin. Hardware and software reset clear SCKD. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 89 6 - 90 X:$FFED For More Information On This Product, Go to: www.freescale.com PORT C TE RE SC0 SC1 SC2 SCK SRD STD 12 13 MOD 11 GCK 10 FSL1 8 FSL0 7 SCD0 SCD1 SCD2 SCKD — — DIRECTION CONTROLLED BY SYN 9 SCD2 (0) SCKD (0) SCD1 (0) 3 SCD0 (0) 2 BASIC FUNCTION 1 = OUTPUT 0 = INPUT 4 5 OF1 1 0 OF0 RECEIVE CLOCK/FLAG 0 RECEIVE FRAME SYNC/FLAG 1 TRANSMIT FRAME SYNC/TX AND RX FRAME SYNC TRANSMIT CLOCK/TX AND RX CLOCK SSI RECEIVE DATA SSI TRANSMIT DATA SHFD 6 Figure 6-46 Serial Control, Direction Bits NOTE: Parentheses indicate RESET condition. C TIE RIE P O R T 14 15 Freescale Semiconductor, Inc... SSI CONTROL REGISTER B (CRB) (READ/WRITE) Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.2.7 CRB Shift Direction (SHFD) Bit 6 This bit causes the transmit shift register to shift data out MSB first when SHFD equals zero or LSB first when SHFD equals one. Receive data is shifted in MSB first when SHFD equals zero or LSB first when SHFD equals one. Hardware reset and software reset clear SHFD. 6.4.2.2.8 CRB Frame Sync Length (FSL0 and FSL1) Bits 7 and 8 These bits select the type of frame sync to be generated or recognized (see Table 6-11). If FSL1 equals zero and FSL0 equals zero, a word-length frame sync is selected for both TX and RX that is the length of the data word defined by bits WL1 and WL0. If FSL1 equals one and FSL0 equals zero, a 1-bit clock period frame sync is selected for both TX and RX. When FSL0 equals one, the TX and RX frame syncs are different lengths. Hardware reset and software reset clear FSL0 and FSL1. Table 6-11 Frame Sync Length FSL1 FSL0 Frame Sync Length 0 0 WL bit clock for both TX/RX 0 1 One-bit clock for TX and WL bit clock for RX 1 0 One-bit clock for both TX/RX 1 1 One-bit clock for RX and WL bit clock for TX 6.4.2.2.9 CRB Sync/Async (SYN) Bit 9 SYN controls whether the receive and transmit functions of the SSI occur synchronously or asynchronously with respect to each other. When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections. When SYN is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. Hardware reset and software reset clear SYN. 6.4.2.2.10 CRB Gated Clock Control (GCK) Bit 10 GCK is used to select between a continuously running data clock or a clock that runs only when there is data to be sent in the transmit shift register. When GCK is cleared, a continuous clock is selected; when GCK is set, the clock will be gated. Hardware reset and software reset clear GCK. Note: For gated clock mode with externally generated bit clock, internally generated frame sync is not defined. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 91 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.2.11 CRB SSI Mode Select (MOD) Bit 11 MOD selects the operational mode of the SSI. When MOD is cleared, the normal mode is selected; when MOD is set, the network mode is selected. In the normal mode, the frame rate divider determines the word transfer rate – one word is transferred per frame sync during the frame sync time slot. In network mode, a word is (possibly) transferred every time slot. For more details, see 6.4.3. Hardware and software reset clear MOD. 6.4.2.2.12 CRB SSI Transmit Enable (TE) Bit 12 TE enables the transfer of data from TX to the transmit shift register. When TE is set and a frame sync is detected, the transmit portion of the SSI is enabled for that frame. When TE is cleared, the transmitter will be disabled after completing transmission of data currently in the SSI transmit shift register. The serial output is three-stated, and any data present in TX will not be transmitted (i.e., data can be written to TX with TE cleared; TDE will be cleared, but data will not be transferred to the transmit shift register). The normal mode transmit enable sequence is to write data to TX or TSR before setting TE. The normal transmit disable sequence is to clear TE and TIE after TDE equals one. In the network mode, the operation of clearing TE and setting it again will disable the transmitter after completing transmission of the current data word until the beginning of the next frame. During that time period, the STD pin will remain in the high-impedance state. Hardware reset and software reset clear TE. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE can be left enabled. Note: TE does not inhibit TDE or transmitter interrupts. TE does not affect the generation of frame sync or output flags. 6.4.2.2.13 CRB SSI Receive Enable (RE) Bit 13 When RE is set, the receive portion of the SSI is enabled. When this bit is cleared, the receiver will be disabled by inhibiting data transfer into RX. If data is being received while this bit is cleared, the remainder of the word will be shifted in and transferred to the SSI receive data register. RE must be set in the normal mode and on-demand mode to receive data. In network mode, the operation of clearing RE and setting it again will disable the receiver after reception of the current data word until the beginning of the next data frame. Hardware and software reset clear RE. Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation 6 - 92 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) of a frame sync. Freescale Semiconductor, Inc... 6.4.2.2.14 CRB SSI Transmit Interrupt Enable (TIE) Bit 14 The DSP will be interrupted when TIE and the TDE flag in the SSI status register is set. (In network mode, the interrupt takes effect in the next frame synch, not in the next time slot.) When TIE is cleared, this interrupt is disabled. However, the TDE bit will always indicate the transmit data register empty condition even when the transmitter is disabled with the TE bit. Writing data to TX or TSR will clear TDE, thus clearing the interrupt. Hardware and software reset clear RE. There are two transmit data interrupts that have separate interrupt vectors: 1. Transmit data with exceptions – This interrupt is generated on the following condition: TIE=1, TDE=1, and TUE=1 2. Transmit data without exceptions – This interrupt is generated on the following condition: TIE=1, TDE=1, and TUE=0 See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more information on exceptions. 6.4.2.2.15 CRB SSI Receive Interrupt Enable (RIE) Bit 15 When RIE is set, the DSP will be interrupted when RDF in the SSI status register is set. (In network mode, the interrupt takes effect in the next frame synch, not in the next time slot.) When RIE is cleared, this interrupt is disabled. However, the RDF bit still indicates the receive data register full condition. Reading the receive data register will clear RDF, thus clearing the pending interrupt. Hardware and software reset clear RIE. There are two receive data interrupts that have separate interrupt vectors: 1. Receive data with exceptions – This interrupt is generated on the following condition: RIE=1, RDF=1, and ROE=1 2. Receive data without exceptions – This interrupt is generated on the following condition: RIE=1, RDF=1, and ROE=0 See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more information on exceptions. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 93 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.3 SSI Status Register (SSISR) The SSISR is an 8-bit read-only status register used by the DSP to interrogate the status and serial input flags of the SSI. When the SSISR is read to the internal data bus, the register contents occupy the low-order byte of the data bus, and the high-order portion is zero filled. The status bits are described in the following paragraphs. 6.4.2.3.1 SSISR Serial Input Flag 0 (IF0) Bit 0 The SSI latches data present on the SC0 pin during reception of the first received bit after frame sync is detected. IF0 is updated with this data when the receive shift register is transferred into the receive data register. The IF0 bit is enabled only when SCD0 is cleared and SYN is set, indicating that SC0 is an input and the synchronous mode is selected (see Table 6-5); otherwise, IF0 reads as a zero when it is not enabled. Hardware, software, SSI individual, and STOP reset clear IF0. 6.4.2.3.2 SSISR Serial Input Flag 1 (IF1) Bit 1 The SSI latches data present on the SC1 pin during reception of the first received bit after frame sync is detected. The IF1 flag is updated with the data when the receiver shift register is transferred into the receive data register. The IF1 bit is enabled only when SCD1 is cleared and SYN is set, indicating that SC1 is an input and the synchronous mode is selected (see Table 6-5); otherwise, IF1 reads as a zero when it is not enabled. Hardware, software, SSI individual, and STOP reset clear IF1. 6.4.2.3.3 SSISR Transmit Frame Sync Flag (TFS) Bit 2 When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. If word-wide transmit frame sync is selected (FSL0=FSL1), this indicates that the frame sync was high at least at the beginning of the time slot if external frame sync is selected, or high throughout the time slot if internal frame sync was selected. If bit-wide transmit frame sync is selected (FSL0≠FSL1), this indicates that the frame sync (either internal or external) was high during the last Tx clock bit period prior to the current time slot, and that the frame sync falling edge corresponds to the assertion of the first output data bit, as shown below. Bit-Length Fs Word-Length Fs Time slots Time slot #1 Time slot #2 Time slot #3 Tx shift clock TFS set here 6 - 94 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Data written to the transmit data register during the time slot when TFS is set will be transmitted (in network mode) during the second time slot in the frame. TFS is useful in network mode to identify the start of the frame. This is illustrated in a typical transmit interrupt handler: MOVEP JCLR JMP X:(R4)+,X:SSITx #2,X:SSISR,_NoTFS;1 = FIRST TIMESLOT ;Do something _DONE _NoTFS ;Do something else Freescale Semiconductor, Inc... _DONE Note: In normal mode, TFS will always read as a one when transmitting data because there is only one time slot per frame – the “frame sync” time slot. TFS, which is cleared by hardware, software, SSI individual, or STOP reset, is not affected by TE. 6.4.2.3.4 SSISR Receive Frame Sync Flag (RFS) Bit 3 When set, RFS indicates that a receive frame sync occurred during reception of the word in the serial receive data register. This indicates that the data word is from the first time slot in the frame. If word-wide receive frame sync is selected (FSL1=0), this indicates that the frame sync was high at least at the beginning of the timeslot. If bit-wide receive frame sync is selected (FSL1=1), this indicates that the frame sync (either internal or external) was high during the last bit period prior to the current timeslot, and that the frame sync falling edge corresponds to the assertion of the first output data bit, as shown below. Bit-Length Fs Word-Length Fs Time slots Time slot #1 Time slot #2 Time slot #3 Rx shift clock RFS set here When RFS is clear and a word is received, it indicates (only in network mode) that the frame sync did not occur during reception of that word. RFS is useful in network mode to identify the start of the frame. This feature is illustrated in a typical receive interrupt handler: MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 95 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOVEP JCLR JMP X:SSIRx,X:(R4)+ #3,X:SSISR,_NoRFS ;1 = FIRST TIMESLOT ;Do something _DONE _NoRFS ;Do something else _DONE Freescale Semiconductor, Inc... Note: In normal mode, RFS will always read as a one when reading data because there is only one time slot per frame – the “frame sync” time slot. RFS, which is cleared by hardware, software, SSI individual, or STOP reset, is not affected by RE. 6.4.2.3.5 SSISR Transmitter Underrun Error Flag (TUE) Bit 4 TUE is set when the serial transmit shift register is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data (which is still present in the TX) will be retransmitted. In the normal mode, there is only one transmit time slot per frame. In the network mode, there can be up to 32 transmit time slots per frame. TUE does not cause any interrupts; however, TUE does cause a change in the interrupt vector used for transmit interrupts so that a different interrupt handler may be used for a transmit underrun condition. If a transmit interrupt occurs with TUE set, the transmit data with exception status interrupt will be generated; if a transmit interrupt occurs with TUE clear, the transmit data without errors interrupt will be generated. Hardware, software, SSI individual, and STOP reset clear TUE. TUE is also cleared by reading the SSISR with TUE set, followed by writing TX or TSR. 6.4.2.3.6 SSISR Receiver Overrun Error Flag (ROE) Bit 5 This flag is set when the serial receive shift register is filled and ready to transfer to the receiver data register (RX) and RX is already full (i.e., RDF=1). The receiver shift register is not transferred to RX. ROE does not cause any interrupts; however, ROE does cause a change in the interrupt vector used for receive interrupts so that a different interrupt handler may be used for a receive error condition. If a receive interrupt occurs with ROE set, the receive data with exception status interrupt will be generated; if a receive interrupt occurs with ROE clear, the receive data without errors interrupt will be generated. Hardware, software, SSI individual, and STOP reset clear ROE. ROE is also cleared by reading the SSISR with ROE set, followed by reading the RX. Clearing RE does not affect ROE. 6 - 96 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.3.7 SSISR SSI Transmit Data Register Empty (TDE) Bit 6 This flag is set when the contents of the transmit data register are transferred to the transmit shift register; it is also set for a disabled time slot period in network mode (as if data were being transmitted after the TSR was written). Thirdly, it can be set by the hardware, software, SSI individual, or STOP reset. When set, TDE indicates that data should be written to the TX or to the time slot register (TSR). TDE is cleared when the DSP writes to the transmit data register or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TDE is set. The vector of the interrupt will depend on the state of the transmitter underrun bit. 6.4.2.3.8 SSISR SSI Receive Data Register Full (RDF) Bit 7 RDF is set when the contents of the receive shift register are transferred to the receive data register. RDF is cleared when the DSP reads the receive data register or cleared by hardware, software, SSI individual, or STOP reset. If RIE is set, a DSP receive data interrupt request will be issued when RDF is set. The vector of the interrupt request will depend on the state of the receiver overrun bit. 6.4.2.3.9 SSI Receive Shift Register This 24-bit shift register receives the incoming data from the serial receive data pin. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O (or gated clock) is asserted. Data is assumed to be received MSB first if SHFD equals zero and LSB first if SHFD equals one. Data is transferred to the SSI receive data register after 8, 12, 16, or 24 bits have been shifted in, depending on the word-length control bits in the CRA (see Figure 6-47). 6.4.2.3.10 SSI Receive Data Register (RX) RX is a 24-bit read-only register that accepts data from the receive shift register as it becomes full. The data read will occupy the most significant portion of the receive data register (see Figure 6-47). The unused bits (least significant portion) will read as zeros. The DSP is interrupted whenever RX becomes full if the associated interrupt is enabled. 6.4.2.3.11 SSI Transmit Shift Register This 24-bit shift register contains the data being transmitted. Data is shifted out to the serial transmit data pin by the selected (internal/external) bit clock when the associated frame sync I/O (or gated clock) is asserted. The number of bits shifted out before the shift register is considered empty and may be written to again can be 8, 12, 16, or 24 bits (determined by the word-length control bits in CRA). The data to be transmitted occupies the most significant portion of the shift register. The unused portion of the register is ignored. Data is shifted out of this register MSB first if SHFD equals zero and LSB first if SHFD equals one (see Figure 6-48). MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 97 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) GDB 23 16 15 12 11 8 7 0 Freescale Semiconductor, Inc... RX 24 BITS RECEIVE SHIFT REGISTER SRD SHFD = 0 16 BITS 12 BITS 8 BITS (a) SHFD = 0 GDB 23 16 15 12 11 8 7 0 RX RECEIVE SHIFT REGISTER SRD SHFD = 1 (b) SHFD = 1 Figure 6-47 Receive Data Path 6 - 98 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) GDB 23 16 15 8 7 0 TX Freescale Semiconductor, Inc... 12 11 TRANSMIT SHIFT REGISTER STD SHFD = 0 (a) SHFD = 0 GDB 23 16 15 8 7 0 TX 12 11 24 BITS TRANSMIT SHIFT REGISTER STD SHFD = 1 8 BIT 12 BIT 16 BIT (b) SHFD = 1 Figure 6-48 Transmit Data Path MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 99 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.2.3.12 SSI Transmit Data Register (TX) TX is a 24-bit write-only register. Data to be transmitted is written into this register and is automatically transferred to the transmit shift register. The data written (8, 12, 16, or 24 bits) should occupy the most significant portion of TX (see Figure 6-48). The unused bits (least significant portion) of TX are don’t care bits. The DSP is interrupted whenever TX becomes empty if the transmit data register empty interrupt has been enabled. 6.4.2.3.13 Time Slot Register (TSR) TSR is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. For the purposes of timing, TSR is a write-only register that behaves like an alternative transmit data register, except that, rather than transmitting data, the transmit data pin is in the high-impedance state for that time slot. 6.4.3 Operational Modes and Pin Definitions Table 6-12 and Table 6-13 completely describe the SSI operational modes and pin definitions (Table 6-5 is a simplified version of these tables). The operational modes are as follows: 1. Continuous Clock Mode 1 – Normal with Internal Frame Sync Mode 2 – Network with Internal Frame Sync Mode 3 – Normal with External Frame Sync Mode 4 – Network with External Frame Sync 2. Gated Clock Mode 5 – External Gated Clock Mode 6 – Normal with Internal Gated Clock Mode 7 – Network with Internal Gated Clock 3. Special Case (Both Gated and Continuous Clock) Mode 8 – On-Demand Mode (Transmitter Only) Mode 9 – Receiver Follows Transmitter Clocking 6.4.4 Registers After Reset Hardware or software reset clears the port control register bits, which configure all I/O as general-purpose input. The SSI will remain in reset while all SSI pins are programmed as general-purpose I/O (CC8–CC3=0) and will become active only when at least one of the SSI I/O pins is programmed as not general-purpose I/O. Table 6-14 shows how each type of reset affects each SSI register bit. 6 - 100 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-12 Mode and Pin Definition Table – Continuous Clock Control Bits Mode Freescale Semiconductor, Inc... MOD GCLK SYN SCD2 SCD1 SCD0 SCKD DC4- TX RX DC0 SC0 In SC1 SC2 SCK In Out Out In Out In Out RXC RXC — FSR — FST TXC TXC F1 F1 — FS* — FSR — FST TXC TXC F1 F1 — FS* 0 0 0 1 1 X X X 1 1 0 0 1 1 X X X X 1 1 1 0 0 1 1 X X 1 2 2 1 0 1 1 X X X 1 2 2 0 0 0 0 1 X X X 3 1 RXC RXC 0 0 0 1 0 X X X 1 3 RXC RXC FSR — — 0 0 0 0 0 X X X 3 3 RXC RXC FSR — FST — TXC TXC 0 0 1 0 X X X X 3 3 F1 FS* — *XC 1 0 0 0 1 X X X 4 2 RXC RXC FSR FST — TXC TXC 1 0 0 1 0 X X 1 2 4 RXC RXC FSR — — 1 0 0 0 0 X X X 4 4 RXC RXC FSR — FST — TXC TXC 1 0 1 0 X X X X 4 4 F1 F1 FS* — *XC 1 0 0 1 1 X X 0 8 2 — FSR — FST TXC TXC 1 0 1 1 X X X 0 8 9 F1 F1 — FS* 1 0 0 1 0 X X 0 8 4 — — FST TXC TXC F0 F0 RXC RXC F0 F0 F0 F0 F0 F0 RXC RXC F0 F0 — FSR FST F1 — RXC RXC FSR — *XC *XC *XC *XC TXC TXC FST TXC TXC *XC FST TXC TXC *XC *XC *XC DC4-DC0 = 0 means that bits DC4 = 0, DC3 = 0, DC2 = 0, DC1 = 0, and DC0 = 0 DC4-DC0 = 1 means that bits DC4-DC0≠0 TXC — Transmitter Clock RXC — Receiver Clock *XC — Transmitter/Receiver Clock (Synchronous Operation) FST — Transmitter Frame Sync FSR — Receiver Frame Sync FS* — Transmitter/Receiver Frame Sync (Synchronous Operation) F0 — Flag 0 F1 — Flag 1 MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 101 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-13 Mode and Pin Definition Table – Gated Clock Control Bits Mode Freescale Semiconductor, Inc... MOD GCLK SYN SCD2 SCD1 SCD0 SCKD DC4- TX RX DC0 SC0 SC1 SC2 SCK In Out In Out In Out In Out 0 1 0 X X 1 1 X 6 6 — RXC ? FSR ? FST — TXC 0 1 1 X X X 1 X 6 6 F0 F0 F0 F1 ? FS* — *XC 0 1 0 X X 1 0 X 5 6 — RXC ? FSR ? ? TXC — 0 1 0 X X 0 0 X 5 5 RXC — ? ? ? ? TXC — 0 1 1 X X X 0 X 5 5 F0 F0 F1 F1 ? ? *XC — 1 1 0 X X 1 1 0 8 7 — RXC ? FSR ? FST — TXC 1 1 0 X X 0 1 0 8 5 RXC — ? ? ? FST — TXC 1 1 1 X X X 1 0 8 9 F0 F0 F1 F1 ? FS* — *XC 0 1 0 X X 0 1 X 6 5 RXC — ? ? ? FST — TXC DC4–DC0=0 means that bits DC4=0, DC3=0, DC2=0, DC1=0, and DC0=0. TXC – Transmitter Clock RXC – Receiver Clock *XC – Transmitter/Receiver Clock (Synchronous Operation) FST – Transmitter Frame Sync FSR – Receiver Frame Sync FS* – Transmitter/Receiver Frame Sync (Synchronous Operation) F0 – Flag 0 F1 – Flag 1 ? – Undefined 6 - 102 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-14 SSI Registers After Reset Register Name Bit Number PSR HW Reset SW Reset Individual Reset ST Reset 15 0 0 – – WL(2–0) 13,14 0 0 – – DC(4–0) 8–12 0 0 – – PM(7–0) 0–7 0 0 – – RIE 15 0 0 – – TIE 14 0 0 – – RE 13 0 0 – – TE 12 0 0 – – MOD 11 0 0 – – GCK 10 0 0 – – SYN 9 0 0 – – FSL1 8 0 0 – – FSL0 7 0 0 – – SHFD 6 0 0 – – SCKD 5 0 0 – – SCD(2–0) 2–4 0 0 – – OF(1–0) 0,1 0 0 – – RDF 7 0 0 0 0 TDE 6 1 1 1 1 ROE 5 0 0 0 0 TUE 4 0 0 0 0 RFS 3 0 0 0 0 TFS 2 0 0 0 0 IF(1–0) 0,1 0 0 0 0 RDR RDR (23–0) 23–0 – – – – TDR TDR (23–0) 23–0 – – – – RSR RDR (23–0) 23–0 – – – – TSR RDR (23–0) 23–0 – – – – CRA Freescale Semiconductor, Inc... Reset Register Data CRB SSISR NOTES: 1. RSR – SSI receive shift register 2. TSR – SSI transmit shift register 3. HW – Hardware reset is caused by asserting the external pin RESET. 4. SW – Software reset is caused by executing the RESET instruction. 5. IR – Individual reset is caused by SSI peripheral pins (i.e., PCC(3–8)) being configured as general-purpose I/O. 6. ST – Stop reset is caused by executing the STOP instruction. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 103 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) HARDWARE OR SOFTWARE REST PROGRAM CRA AND CRB Freescale Semiconductor, Inc... SELECT PINS TO BE USED PORT C CONTROL REGISTER Figure 6-49 SSI Initialization Block Diagram 6.4.5 SSI Initialization The correct way to initialize the SSI is as follows: 1. Hardware, software, SSI individual, or STOP reset 2. Program SSI control registers 3. Configure SSI pins (at least one) as not general-purpose I/O During program execution, CC8–CC3 may be cleared, causing the SSI to stop serial activity and enter the individual reset state. All status bits of the interface will be set to their reset state; however, the contents of CRA and CRB are not affected. This procedure allows the DSP program to reset each interface separately from the other internal peripherals. The DSP program must use an SSI reset when changing the MOD, GCK, SYN, SCKD, SCD2, SCD1, or SCD0 bits to ensure proper operation of the interface. Figure 6-49 is a flowchart illustrating the three initialization steps previously listed. Figure 6-50, Figure 6-51, and Figure 6-52 provide additional detail to the flowchart. 6 - 104 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA WL1 PSR WL0 13 For More Information On This Product, Go to: www.freescale.com PORT C TIE RIE NOTES: 1. NORMAL — MOD = 0 2. NETWORK — MOD = 1 3. FSL1 = 1, FSL0 = 0 X:$FFED 14 15 SSI BIT RATE CLOCK DIVIDE BY 2 RE 13 PRESCALER IF PSR = 1, THEN DIVIDE BY 8 IF PSR = 0, THEN DIVIDE BY 1 X:$FFEC 14 15 MOD GCK 10 DC2 10 DC0 8 SYN 9 12 8 FSL0 7 PM7 7 (SEE NOTE 3) FSL1 8 Bits/Word DC1 9 SHFD 6 PM6 6 PM4 4 SCKD 5 PM1 1 SCD1 SCD0 OF1 • • 1• • • 4• SCD2 4 00011 OF0 0 3 00010 2 2 00001 SSI CONTROL REGISTER B (CRB) (READ/WRITE) • • • 4 3 2 On-Demand Data Driven fosc SSI CONTROL REGISTER A (CRA) (READ/WRITE) Continuous Periodic (See Note 3) PM0 0 00000 DIVIDE BY 2 PM2 2 Words/Frame (See Note 2) 3 PM3 3 Word Transfer Rate (See Note 1) DC4-DC0 DIVIDE BY 1 TO 256 PM5 5 Figure 6-50 SSI CRA Initialization Procedure (SEE NOTES 1 AND 2) TE 11 1 0 12 0 WL0 DC3 11 0 WL1 DC4 12 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6 - 105 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) FRAME SYNC LENGTH 0 0 = RX AND TX SAME LENGTH 1 = RX AND TX DIFFERENT LENGTH FRAME SYNC LENGTH 1 0 = RX IS WORD LENGTH 1 = RX IS BIT LENGTH SHIFT DIRECTION 0 = MSB FIRST 1 = LSB FIRST Freescale Semiconductor, Inc... SYNC/ASYNC CONTROL 0 = ASYNCHRONOUS 1 = SYNCHRONOUS GATED CLOCK CONTROL 0 = CONTINUOUS CLOCK 1 = GATED CLOCK CLOCK SOURCE DIRECTION 0 = INPUT (EXTERNAL) 1 = OUTPUT (INTERNAL) SERIAL CONTROL DIRECTION BITS 0 = INPUT 1 = OUTPUT SSI MODE SELECT 0 = NORMAL 1 = NETWORK 15 14 13 12 RIE TIE RE TE MOD 11 GCK 10 SYN 9 FSL1 8 FSL0 SHFD SCKD SCD2 SCD1 SCD0 7 6 5 4 3 2 TRANSMIT ENABLE 0 = DISABLE 1 = ENABLE OUTPUT FLAG 1 IF SYN = 1, SCD1 = 1 OF1 SC1 PIN RECEIVE ENABLE 0 = DISABLE 1 = ENABLE OUTPUT FLAG 0 IF SYN = 1, SCD0 = 1 OF0 SC0 PIN 1 0 OF1 OF0 TRANSMIT INTERRUPT ENABLE 0 = DISABLE 1 = ENABLE RECEIVE INTERRUPT ENABLE 0 = DISABLE 1 = ENABLE Figure 6-51 SSI CRB Initialization Procedure 6 - 106 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 23 X:$FFE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC CC CC CC CC CC CC CC CC 8 7 6 5 4 3 2 1 0 STD SCK SRD Freescale Semiconductor, Inc... CCx GPIO 1 Serial Interface C SC1 SC0 Function 0 P O R T SC2 PORT C CONTROL REGISTER (PCC) PC0 PC1 PC2 SC0 SC1 SC2 SCK SRD STD SERIAL CONTROL PIN 0 SERIAL CONTROL PIN 1 SERIAL CONTROL PIN 2 SERIAL CLOCK PIN SERIAL RECEIVE DATA PIN SERIAL TRANSMIT DATA PIN Figure 6-52 SSI Initialization Procedure Figure 6-52 shows the six control bits in the PCC, which select the six SSI pins as either general-purpose I/O or as SSI pins. The STD pin can only transmit data; the SRD pin can only receive data. The other four pins can be inputs or outputs, depending on how they are programmed. This programming is accomplished by setting bits in CRA and CRB as shown in Figure 6-46. The CRA (see Figure 6-50) sets the SSI bit rate clock with PSR and PM0–PM7, sets the word length with WL1 and WL0, and sets the number of words in a frame with DC0–DC4. There is a special case where DC4–DC0 equals zero (one word per frame). Depending on whether the normal or network mode is selected (MOD=0 or MOD=1, respectively), either the continuous periodic data mode is selected, or the on-demand data driven mode is selected. The continuous periodic mode requires that FSL1 equals one and FSL0 equals zero. Figure 6-51 shows the meaning of each individual bit in the CRB. These bits should be set according to the application requirements. Table 6-15 (a) and Table 6-15 (b) provide a convenient listing of PSR and PM0–PM7 settings for the common data communication rates and the highest rate possible for the SSI for the chosen crystal frequencies. The crystal frequency selected for Table 6-15 (a) is the one used by the DSP56002ADS board; the one selected for Table 6-15 (b) is the closest one to 40 MHz that divides down to exactly 128 kHz. If an exact baud rate is required, the crystal frequency may have to be selected. Table 6-16 gives the PSR and PM0–PM7 settings in addition to the required crystal frequency for three common telecommunication frequencies. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 107 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-15 (b) SSI Bit Rates for a 39.936-MHz Crystal Freescale Semiconductor, Inc... Table 6-15 (a) SSI Bit Rates for a 40-MHz Crystal Bit Rate (BPS) PSR PM Bit Rate (BPS) PSR PM 1000 1 $4E1 1000 1 $4DF 2000 1 $270 2000 1 $26F 4000 1 $138 4000 1 $137 8000 1 $9B 8000 1 $9B 16K 1 $4D 16K 1 $4D 32K 1 $26 32K 1 $26 64K 0 $9B 64K 0 $9B 128K 0 $4D 128K 0 $4D 10M 0 $00 9.984M 0 $00 BPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1)) where fosc=39.936 MHz PSR = 0 or 1 PM = 0 to $FFF BPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1)) where fosc=40 MHz PSR = 0 or 1 PM = 0 to $FFF Table 6-16 Crystal Frequencies Required for Codecs Bit Rate (BPS) PSR PM Crystal Frequency 1.536M 0 $05 36.864 MHz 1.544M 0 $05 37.056 MHz 2.048M 0 $03 32.678 MHz BPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1)) PSR = 0 or 1 PM = 0 to $FFF 6 - 108 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6.4.6 SSI Exceptions The SSI can generate four different exceptions (see Figure 6-53 and Figure 6-54): 1. SSI Receive Data – occurs when the receive interrupt is enabled, the receive data register is full, and no receive error conditions exist. Reading RX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. Freescale Semiconductor, Inc... 2. SSI Receive Data with Exception Status – occurs when the receive interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. ROE is cleared by first reading the SSISR and then reading RX. 3. SSI Transmit Data – occurs when the transmit interrupt is enabled, the transmit data register is empty, and no transmitter error conditions exist. Writing to TX or the TSR will clear this interrupt. This error-free interrupt may use a fast interrupt service routine for minimum overhead. 4. SSI Transmit Data with Exception Status – occurs when the transmit interrupt is enabled, the transmit data register is empty, and a transmitter underrun error has occurred. TUE is cleared by first reading the SSISR and then writing to TX or the TSR to clear the pending interrupt. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 109 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) EXCEPTION STARTING ADDRESS PROGRAM MEMORY SPACE Freescale Semiconductor, Inc... EXCEPTION SOURCE TWO WORDS PER VECTOR $0000 HARDWARE RESET $0002 STACK ERROR $0004 TRACE $0006 SWI (SOFTWARE INTERRUPT) $0008 IRQA EXTERNAL HARDWARE INTERRUPT EXTERNAL INTERRUPTS INTERNAL INTERRUPTS $000A IRQB EXTERNAL HARDWARE INTERRUPT $000C SSI RECEIVE DATA $000E SSI RECEIVE DATA WITH EXCEPTION STATUS $0010 SSI TRANSMIT DATA $0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS $0014 SCI RECEIVE DATA $0016 SCI RECEIVE DATA WITH EXCEPTION STATUS $0018 SCI TRANSMIT DATA $001A SCI IDLE LINE $001C SCI TIMER $001E RESERVED $0020 HOST RECEIVE DATA $0022 HOST TRANSMIT DATA $0024 HOST COMMAND (DEFAULT) $0026 AVAILABLE FOR HOST COMMAND $0028 AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND $003C TIMER $003E ILLEGAL INSTRUCTION $0040 AVAILABLE FOR HOST COMMAND $007E AVAILABLE FOR HOST COMMAND SYNCHRONOUS SERIAL INTERFACE INTERNAL INTERRUPTS • • • $003A EXTERNAL INTERRUPTS SERIAL COMMUNICATIONS INTERFACE HOST INTERFACE INTERNAL INTERRUPTS • • • Figure 6-53 SSI Exception Vector Locations 6 - 110 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) RECEIVE INTERRUPT SERVICE ROUTINE SSI CONTROL REGISTER (CRB) (READ/WRITE) X:$FFED 15 14 13 12 11 10 9 8 RIE TIE RE TE MOD GCK SYN FSL1 1. INTERRUPT IS GENERATED WHEN RIE = 1, RDF = 1, AND ROE = 0. 2. PENDING INTERRUPT IS CLEARED BY READING RX. Freescale Semiconductor, Inc... SSI EXCEPTION MASK RECEIVE WITH EXCEPTION STATUS INTERRUPT SERVICE ROUTINE 1. INTERRUPT IS GENERATED WHEN RIE = 1, RDF = 1, AND ROE = 1. SSI EXCEPTION MASK EXCEPTION STARTING ADDRESS 2. ROE IS CLEARED BY READING SSISR FOLLOWED BY: EXCEPTION VECTOR TABLE $0000 3. READING RX TO CLEAR PENDING INTERRUPT. 4. APPLICATION-SPECIFIC CODE. $000C SSI RECEIVE DATA $000E SSI RECEIVE DATA WITH EXCEPTIONS STATUS TRANSMIT INTERRUPT SERVICE ROUTINE $0010 SSI TRANSMIT DATA $0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS 1. INTERRUPT IS GENERATED WHEN TIE = 1, TDF = 1, AND TUE = 0. 2. PENDING INTERRUPT IS CLEARED BY WRITING TO TX OR TSR. SSI STATUS REGISTER (SSISR) (READ ONLY) X:$FFFE 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF1 IF0 SSI STATUS BITS TRANSMIT WITH EXCEPTION STATUS INTERRUPT SERVICE ROUTINE 1. INTERRUPT IS GENERATED WHEN TIE = 1, TDF = 1, AND TUE = 1. 2. TUE IS CLEARED BY READING SSISR FOLLOWED BY: 3. WRITING TO TX OR TSR TO CLEAR PENDING INTERRUPT. 4. APPLICATION-SPECIFIC CODE. Figure 6-54 SSI Exceptions MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 111 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Table 6-17 SSI Operating Modes Freescale Semiconductor, Inc... Operating Format Serial Clock TX, RX Sections Typical Applications Normal Continuous Asynchronous Single Asynchronous Codec; Stream-Mode Channel Interface Normal Continuous Synchronous Multiple Synchronous Codecs Normal Gated Asynchronous DSP-to-DSP; Serial Peripherals (A/D,D/A) Normal Gated Synchronous SPI-Type Devices; DSP to MCU Network Continuous Asynchronous TDM Networks Network Continuous Synchronous TDM Codec Networks, TDM DSP Networks On Demand Gated Asynchronous Parallel-to-Serial and Serial-to-Parallel Conversion On Demand Gated Synchronous DSP to SPI Peripherals 6.4.7 Operating Modes – Normal, Network, and On-Demand The SSI has three basic operating modes and many data/operation formats. These modes can be programmed by several bits in the SSI control registers. Table 6-17 lists the SSI operating modes and some of the typical applications in which they may be used. The data/operation formats are selected by choosing between gated and continuous clocks, synchronization of transmitter and receiver, selection of word or bit frame sync, and whether the LSB is transferred first or last. The following paragraphs describe how to select a particular data/operation format and describe examples of normal-mode and network-mode applications. The on-demand mode is selected as a special case of the network mode. The SSI can function as an SPI master or SPI slave, using additional logic for arbitration, which is required because the SSI interface does not perform SPI master/slave arbitration. An SPI master device always uses an internally generated clock; whereas, an SPI slave device always uses an external clock. 6.4.7.1 Data/Operation Formats The data/operation formats available to the SSI are selected by setting or clearing control bits in the CRB. These control bits are MOD, GCK, SYN, FSL1, FSL0, and SHFD. 6.4.7.1.1 Normal/Network Mode Selection Selecting between the normal mode and network mode is accomplished by clearing or setting the MOD bit in the CRB (see Figure 6-55). For normal mode, the SSI functions with one data word of I/O per frame (see Figure 6-56). For the network mode, 2 to 32 data words of 6 - 112 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... I/O may be used per frame. In either case, the transfers are periodic. The normal mode is typically used to transfer data to/from a single device. Network mode is typically used in time division multiplexed (TDM) networks of codecs or DSPs with multiple words per frame (see Figure 6-57, which shows two words in a frame with either word-length or bit-length frame sync). The frame sync shown in Figure 6-55 is the word-length frame sync. A bit-length frame sync can be chosen by setting FSL1 and FSL0 for the configuration desired. 6.4.7.1.2 Continuous/Gated Clock Selection The TX and RX clocks may be programmed as either continuous or gated clock signals by the GCK bit in the CRB. A continuous TX and RX clock is required in applications such as communicating with some codecs where the clock is used for more than just data transfer. A gated clock, in which the clock only toggles while data is being transferred, is useful for many applications and is required for SPI compatibility. The frame sync outputs may be used as a start conversion signal by some A/D and D/A devices. Figure 6-58 illustrates the difference between continuous clock and gated clock systems. A separate frame-sync signal is required in continuous clock systems to delimit the active clock transitions. Although the word-length frame sync is shown in Figure 6-58, a bit-length frame sync can be used (see Figure 6-59). In gated clock systems, frame synchronization is inherent in the clock signal; thus a separate sync signal is not required (see Figure 6-60 and Figure 6-61). The SSI can be programmed to generate frame sync outputs in gated clock mode but does not use frame sync inputs. Input flags (see Figure 6-60 and Figure 6-61) are latched on the negative edge of the first data bit of a frame. Output flags are valid during the entire frame. 6.4.7.1.3 Synchronous/Asynchronous Operating Modes The transmit and receive sections of this interface may be synchronous or asynchronous – i.e., the transmitter and receiver may use common clock and synchronization signals (synchronous operating mode, see Figure 6-62) or they may have their own separate clock and sync signals (asynchronous operating mode). The SYN bit in CRB selects synchronous or asynchronous operation. Since the SSI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. Figure 6-63 illustrates the operation of the SYN bit in the CRB. When SYN equals zero, the SSI TX and RX clocks and frame sync sources are independent. If SYN equals one, the SSI TX and RX clocks and frame sync come from the same source (either external or internal). MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 113 6 - 114 DATA TIE RIE TE 12 For More Information On This Product, Go to: www.freescale.com PORT C SLOT 1 SYN 9 FSL1 8 FSL0 7 * NORMAL MOD = 0 GCK 10 * NETWORK MOD = 1 SLOT 3 RECEIVER INTERRUPT AND FLAGS SET SLOT 2 SHFD 6 RECEIVER INTERRUPT AND FLAGS SET TRANSMITTER INTERRUPTS AND FLAGS SET SLOT 1 DATA SCKD 5 SCD2 4 Figure 6-55 CRB MOD Bit Operation NOTE: Interrupts occur every time slot and a word may be transferred. SERIAL DATA FRAME SYNC SERIAL CLOCK * MOD 11 TRANSMITTER INTERRUPT AND FLAGS SET RE 13 NOTE: Interrupts occur and data is transferred once per frame sync. SERIAL DATA FRAME SYNC SERIAL CLOCK X:$FFED 14 15 SCD1 3 SLOT 2 SCD0 2 Freescale Semiconductor, Inc... OF1 1 OF0 0 SSI CONTROL REGISTER B (CRB) (READ/WRITE) Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) FRAME SYNC (FSL0 = 0, FSL1 = 0) FRAME SYNC (FSL0 = 0, FSL1 = 1) Freescale Semiconductor, Inc... DATA OUT FLAGS SLOT 0 WAIT SLOT 0 Figure 6-56 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) FRAME SYNC (FSL0 = 0, FSL1 = 0) FRAME SYNC (FSL0 = 0, FSL1 = 1) DATA FLAGS SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 6-57 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 115 6 - 116 TIE RIE DATA RE 13 TE 12 For More Information On This Product, Go to: www.freescale.com PORT C DATA MOD 11 SYN 9 FSL1 8 FSL0 7 SHFD 6 SCKD 5 SCD2 4 * GATED CLOCK GCK = 1 SCD1 3 DATA DATA STABLE DATA CHANGES DATA DATA STABLE DATA CHANGES * CONTINUOUS CLOCK GCK = 0 * GCK 10 Figure 6-58 CRB GCK Bit Operation NOTES: 1. Word synchronization is inherent in the serial clock signal. 2. Frame Sync generation is optional. SERIAL DATA SERIAL CLOCK NOTE: Frame sync is required to tell when data is present. SERIAL DATA FRAME SYNC SERIAL CLOCK X:$FFED 14 15 SCD0 2 OF1 1 Freescale Semiconductor, Inc... OF0 0 SSI CONTROL REGISTER B (CRB) (READ/WRITE) Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT C 7 7 DATA NOT DEFINED 0 6 6 5 5 4 4 3 3 2 2 1 1 Figure 6-59 Continuous Clock Timing Diagram (8-Bit Example) NOTES: 1. For FSL1 = 0 the frame sync is latched and enables the STD output buffer, but data may not be valid until the rising edge of the bit clock. 2. WL bit frame sync (FSL0 = 0, FSL1 = 0) is not defined for DC = 0 in continuous clock mode. 3. Data and flags transition after external frame sync but not before the rising edge of the clock. OUTPUT FLAGS DATA OUT FOR: FSL1 = 0, FSL0 = 0 FSL0 = 0, FSL1 = 0 FRAME SYNC IN: FSL0 = 0, FSL1 = 1 OUTPUT FLAGS FSL0 = 0, FSL1 = 0 FRAME SYNC OUT: FSL0 = 0, FSL1 = 1 INPUT FLAGS LATCHED DATA IN LATCHED DATA OUT (FOR DC = 0, OR NETWORK MODES) DATA OUT (FOR DC > 0) CONTINUOUS CLOCK 7 Freescale Semiconductor, Inc... (DC = 0) (DC = 0) 0 0 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6 - 117 6 - 118 For More Information On This Product, Go to: www.freescale.com PORT C 0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Figure 6-60 Internally Generated Clock Timing (8-Bit Example) OUTPUT FLAGS (DC = 0) OUTPUT FLAGS (DC > 0) INPUT FLAGS LATCHED FRAME SYNC OUT: FSL0 = 0, FSL1 = 0 FRAME SYNC OUT: FSL0 = 0, FSL1 = 1 DATA IN LATCHED DATA OUT (DC = 0) GATED CLOCK (DC = 0) DATA OUT (DC > 0) GATED CLOCK OUTPUT (DC>0) Freescale Semiconductor, Inc... (DC = 0) 0 0 7 6 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT C 0 7 7 6 6 5 5 4 4 3 3 2 2 Figure 6-61 Externally Generated Gated Clock Timing (8-Bit NOTES: 1. Output enabled on rising edge of first clock input. 2. Output disabled on falling edge of last clock pulse. 3. tdhgc is guaranteed by circuit design. 4. Frame syncs (in or out) are not defined for external gated clock mode. INPUT FLAGS LATCHED DATA IN LATCHED DATA OUT (DC = 0) GATED CLOCK (DC = 0) DATA OUT (DC > 0) GATED CLOCK INPUT (DC>0) Freescale Semiconductor, Inc... 1 1 0 0 7 tdhgc ≥ 5 ns 6 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Data clock and frame sync signals can be generated internally by the DSP or may be ob- 6 - 119 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) START OF FRAME ONE FRAME WORD TRANSFER FATE (=3) 3 WORDS PER FRAME WORD WORD WORD WORD SERIAL CLOCK Freescale Semiconductor, Inc... FRAME SYNC TRANSMITTER EMPTY INTERNAL INTERRUPTS AND FLAGS TRANSMIT DATA XMIT DATA XMIT DATA RECEIVER FULL INTERNAL INTERRUPTS AND FLAGS RECEIVE DATA REC DATA REC DATA 3-STATE 3-STATE Figure 6-62 Synchronous Communication tained from external sources. If internally generated, the SSI clock generator is used to derive bit clock and frame sync signals from the DSP internal system clock. The SSI clock generator consists of a selectable fixed prescaler and a programmable prescaler for bit rate clock generation and also a programmable frame-rate divider and a word-length divider for frame-rate sync-signal generation. Figures Figure 6-64 through Figure 6-67 show the definitions of the SSI pins during each of the four main operating modes of the SSI I/O interface. Figure 6-64 uses a gated clock (from either an external source or the internal clock), which means that frame sync is inherent in the clock. Since both the transmitter and receiver use the same clock (synchronous configuration), both use the SCK pin. SC0 and SC1 are designated as flags or can be used as general purpose-parallel I/O. SC2 is not defined if it is an input; SC2 is the transmit and receive frame sync if it is an output. Figure 6-65 shows a gated clock (from either an external source or the internal clock), which means that frame sync is inherent in the clock. Since this configuration is asynchronous, SCK is the transmitter clock pin (input or output) and SC0 is the receiver clock pin (input or output). SC1 and SC2 are designated as receive or transmit frame sync, respectively, if they are se- 6 - 120 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SSI CONTROL REGISTER B (CRB) (READ/WRITE) X:$FF 15 14 13 12 11 10 9 8 7 6 RIE TIE RE TE MOD GCK SYN FSL1 FSL0 SHFD 5 4 SCKD SCD2 3 2 SCD1 SCD0 1 0 OF1 OF0 * *ASYNCHRONOUS SYN = 0 TRANSMITTER Freescale Semiconductor, Inc... STD FRAME SYNC CLOCK EXTERNAL TRANSMIT CLOCK EXTERNAL TRANSMIT FRAME SYNC SCK SC2 INTERNAL CLOCK INTERNAL FRAME SYNC EXTERNAL RECEIVE CLOCK EXTERNAL RECEIVE FRAME SYNC SSI BIT CLOCK SC0 SC1 CLOCK FRAME SYNC SRD RECEIVER NOTE: Transmitter and receiver may have different clocks and frame syncs. * SYNCHRONOUS SYN = 1 TRANSMITTER STD FRAME SYNC CLOCK EXTERNAL CLOCK EXTERNAL FRAME SYNC SCK SSI BIT CLOCK SC2 INTERNAL CLOCK INTERNAL FRAME SYNC CLOCK FRAME SYNC SRD RECEIVER NOTE: Transmitter and receiver may have the same clock frame syncs. Figure 6-63 CRB SYN Bit Operation MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 121 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) PC8 STD PC7 SRD PC6 SCK (TXC and RXC) SSI PC3 PC4 PC5 SC0 FLAG0 SC1 FLAG1 SC2 ? FSt and FSr Freescale Semiconductor, Inc... Figure 6-64 Gated Clock — Synchronous Operation PC8 STD PC7 SRD PC6 SCK (TXC) SSI PC3 PC4 PC5 SC0 SC1 SC2 RXC ? FSr ? FSt Figure 6-65 Gated Clock — Asynchronous Operation PC8 STD PC7 SRD PC6 SCK (TXC and RXC) SSI PC3 PC4 PC5 SC0 SC1 SC2 FLAG 0 FLAG 1 FSr and FSt Figure 6-66 Continuous Clock — Synchronous Operation PC8 STD PC7 SRD PC6 SCK (TXC) SSI PC3 PC4 PC5 SC0 SC1 SC2 RXC FSr FSt Figure 6-67 Continuous Clock — Asynchronous Operation 6 - 122 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) lected to be outputs; these bits are undefined if they are selected to be inputs. SC1 and SC2 can also be used as general-purpose parallel I/O. Freescale Semiconductor, Inc... Figure 6-66 shows a continuous clock (from either an external source or the internal clock), which means that frame sync must be a separate signal. SC2 is used for frame sync, which can come from an internal or external source. Since both the transmitter and receiver use the same clock (synchronous configuration), both use the SCK pin. SC0 and SC1 are designated as flags or can be used as general-purpose parallel I/O. Figure 6-67 shows a continuous clock (from either an external source or the internal clock), which means that frame sync must be a separate signal. SC1 is used for the receive frame sync, and SC2 is used for the transmit frame sync. Either frame sync can come from an internal or external source. Since the transmitter and receiver use different clocks (asynchronous configuration), SCK is used for the transmit clock, and SC0 is used for the receive clock. 6.4.7.1.4 Frame Sync Selection The transmitter and receiver can operate totally independent of each other. The transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or opposite format. The selection is made by programming FSL0 and FSL1 in the CRB as shown in Figure 6-68. 1. If FSL1 equals zero (see Figure 6-69), the RX frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, SPI serial peripherals, serial A/D and D/A converters, shift registers, and telecommunication PCM serial I/O. 2. If FSL1 equals one (see Figure 6-70), the RX frame sync pulses active for one bit clock immediately before the data transfer period. This frame sync length is compatible with Intel and National components, codecs, and telecommunication PCM serial I/O. The ability to mix frame sync lengths is useful in configuring systems in which data is received from one type device (e.g., codec) and transmitted to a different type device. FSL0 controls whether RX and TX have the same frame sync length (see Figure 6-68). If FSL0 equals zero, RX and TX have the same frame sync length, which is selected by FSL1. If FSL0 equals one, RX and TX have different frame sync lengths, which are selected by FSL1. The SSI receiver looks for a receive frame sync leading edge only when the previous MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 123 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SSI CONTROL REGISTER B (CRB) (READ/WRITE) X:$FFED 15 14 13 12 11 10 9 8 7 6 RIE TIE RE TE MOD GCK SYN FSL1 FSL0 SHFD * * 5 4 SCKD SCD2 3 2 SCD1 SCD0 1 0 OF1 OF0 * WORD LENGTH: FSL1 = 0, FSL0 = 0 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA Freescale Semiconductor, Inc... DATA DATA NOTE: Frame sync occurs while data is valid. * ONE BIT: FSL1 = 1, FSL0 = 0 SERIAL CLOCK RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA NOTE: Frame sync occurs for one bit time preceding the data. * MIXED FRAME LENGTH: FSL1 = 0, FSL0 = 1 SERIAL CLOCK RX FRAME SYNC RX SERIAL DATA DATA DATA DATA DATA TX FRAME SYNC TX SERIAL DATA * MIXED FRAME LENGTH: FSL1 = 1, FSL0 = 1 SERIAL CLOCK RX FRAME SYNC RX SERIAL DATA DATA DATA DATA DATA TX FRAME SYNC TX SERIAL DATA Figure 6-68 CRB FSL0 and FSL1 Bit Operation 6 - 124 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA X:$FFEC X:$FFEC WL0 WL1 TIE RIE RE 13 TE 12 For More Information On This Product, Go to: www.freescale.com PORT C DC2 0 10 DC1 0 9 0 8 DC0 0 8 SHFD 6 PM6 6 1 5 PM5 5 1 4 PM4 4 INTERNAL INTERRUPTS AND FLAGS SCD0 2 PM2 2 OF1 1 PM1 1 OF0 0 PM0 0 SSI CONTROL REGISTER B (CRB) (READ/WRITE) SSI CONTROL REGISTER A (CRA) (READ/WRITE) CODEC DATA DSP DATA FSL1 FRAME SYNC LENGTH 0 = WORD CLOCK FSL0 FRAME SYNC LENGTH 0 = SAME LENGTHS SCKD CLOCK SOURCE DIRECTION 1 = OUTPUT SCD2 SERIAL CONTROL 2 DIRECTION 1 = OUTPUT SCD1 3 PM3 3 INTERNAL INTERRUPTS AND FLAGS 0 7 PM7 7 Figure 6-69 Normal Mode Initialization for FLS1=0 and FSL0=0 CODEC DATA 1 9 RECEIVE DATA 0 10 DSP DATA 0 11 3 WORD FRAME RATE DC3 0 11 TRANSMIT DATA FRAME SYNC SERIAL CLOCK SYN SYNC/ASYNC CONTROL 1 = SYNCHRONOUS GCK GATED CLOCK CONTROL 0 = CONTINUOUS CLOCK MOD SSI MODE SELECT 0 = NORMAL 14 15 0 12 DC4 8-BIT WORD LENGTH 0 0 PSR 13 14 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6 - 125 6 - 126 X:$FFED X:$FFEC TIE RIE RE 13 For More Information On This Product, Go to: www.freescale.com PORT C TE 12 SYN SYNC/ASYNC CONTROL 1 = SYNCHRONOUS GCK GATED CLOCK CONTROL 0 = CONTINUOUS SERIAL DATA DC2 0 10 DATA 1 0 11 0 10 1 9 DC1 0 9 DATA 2 1 8 DC0 0 8 0 7 PM7 7 PM5 5 PM4 4 SHFD 6 DATA 3 1 5 1 4 3 PM3 3 SCD0 2 PM2 2 OF1 1 PM1 1 OF0 0 PM0 0 SSI CONTROL REGISTER B (CRB) (READ/WRITE) SSI CONTROL REGISTER A (CRA) (READ/WRITE) DATA 4 FSL1 FRAME SYNC LENGTH 1 = WL CLOCK FOR RX FSL0 FRAME SYNC LENGTH 0 = DIFFERENT LENGTHS SCKD CLOCK SOURCE DIRECTION 1 = OUTPUT DATA 5 SCD2 SERIAL CONTROL 2 DIRECTION 1 = OUTPUT SCD1 CONTINUOUS PERIODIC PM6 6 Figure 6-70 Normal Mode Initialization for FSL1=1 and FSL0=0 TRANSMIT AND RECEIVE FRAME SYNC SERIAL CLOCK DC3 0 11 8-BIT WORD LENGTH DC4 0 12 MOD SSI MODE SELECT 0 = NORMAL 14 WL0 WL1 15 0 0 PSR 13 14 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... frame is completed. If the frame sync goes high before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync), the current frame sync will not be recognized, and the receiver will be internally disabled until the next frame sync. Frames do not have to be adjacent – i.e., a new frame sync does not have to immediately follow the previous frame. Gaps of arbitrary periods can occur between frames. The transmitter will be three-stated during these gaps. 6.4.7.1.5 Shift Direction Selection Some data formats, such as those used by codecs, specify MSB first other data formats, such as the AES-EBU digital audio, specify LSB first. To interface with devices from both systems, the shift registers in the SSI are bidirectional. The MSB/LSB selection is made by programming SHFD in the CRB. Figure 6-71 illustrates the operation of the SHFD bit in the CRB. If SHFD equals zero (see Figure 6-71(a)), data is shifted into the receive shift register MSB first and shifted out of the transmit shift register MSB first. If SHFD equals one (see Figure 6-71(b)), data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first. 6.4.7.2 Normal Mode Examples The normal SSI operating mode characteristically has one time slot per serial frame, and data is transferred every frame sync. When the SSI is not in the normal mode, it is in the network mode. The MSB is transmitted first (SHFD=0), with overrun and underrun errors detected by the SSI hardware. Transmit flags are set when data is transferred from the transmit data register to the transmit shift register. The receive flags are set when data is transferred from the receive shift register to the receive data register. Figure 6-72 shows an example of using the SSI to connect an MC15500 codec with a DSP56002. No glue logic is needed. The serial clock, which is generated internally by the DSP, provides the transmit and receive clocks (synchronous operation) for the codec. SC2 provides all the necessary handshaking. Data transfer begins when the frame sync is asserted. Transmit data is clocked out and receive data is clocked in with the serial clock while the frame sync is asserted (word-length frame sync). At the end of the data transfer, DSP internal interrupts programmed to transfer data to/from will occur, and the SSISR will be updated. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 127 :$FFED 6 - 128 TIE RIE For More Information On This Product, Go to: www.freescale.com PORT C STD X:$FFEF X:$FFEF 14 15 MOD 11 10 7 0 7 FSL0 7 0 7 8 7 0 7 8 7 * 0 7 8 7 0 7 SCD2 4 SCD1 3 TRANSMIT LOW BYTE RECEIVE LOW BYTE 16 BIT RECEIVE LOW BYTE RECEIVE LOW BYTE SCKD 5 (a) SHFD = 0 TRANSMIT MIDDLE BYTE RECEIVE MIDDLE BYTE 8 7 12 BIT RECEIVE MIDDLE BYTE 8 BIT 6 SHFD RECEIVE MIDDLE BYTE FSL1 8 0 0 0 0 0 0 0 0 OF1 1 OF0 0 SSI CONTROL REGISTER B (CRB) (READ/WRITE) SRD SERIAL TRANSMIT SHIFT REGISTER SERIAL RECEIVE DATA REGISTER (RX) (READ ONLY) 24 BIT SERIAL RECEIVE SHIFT REGISTER (RX) SERIAL RECEIVE DATA REGISTER (RX) (READ ONLY) SCD0 2 Figure 6-71 CRB SHFD Bit Operation (Sheet 1 of 2) TRANSMIT HIGH BYTE 16 15 23 7 0 RECEIVE HIGH BYTE 7 16 15 0 7 23 7 16 15 23 RECEIVE HIGH BYTE 0 7 9 SYN 16 15 GCK RECEIVE HIGH BYTE TE 12 7 23 RE 13 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA MOTOROLA X:$FFEF SRD X:$FFEF 7 For More Information On This Product, Go to: www.freescale.com PORT C 7 7 12 BIT 0 7 8 7 0 7 8 7 0 7 8 7 0 7 (b) SHFD=1 8 BIT TRANSMIT MIDDLE BYTE TRANSMIT MIDDLE BYTE RECEIVE MIDDLE BYTE RECEIVE MIDDLE BYTE 8 7 16 BIT TRANSMIT LOW BYTE TRANSMIT LOW BYTE RECEIVE LOW BYTE RECEIVE LOW BYTE 0 0 0 0 0 0 0 0 24 BIT STD SERIAL TRANSMIT SHIFT REGISTER SERIAL TRANSMIT DATA REGISTER (TX) (WRITE ONLY) SERIAL RECEIVE SHIFT REGISTER (RX) SERIAL RECEIVE DATA REGISTER (RX) (READ ONLY) Figure 6-71 CRB SHFD Bit Operation (Sheet 2 of 2) 0 16 15 7 16 15 0 23 TRANSMIT HIGH BYTE 7 16 15 0 0 TRANSMIT HIGH BYTE RECEIVE HIGH BYTE RECEIVE HIGH BYTE 16 15 7 23 7 23 7 23 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6 - 129 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... MC1550x CODEC FILTER ANALOG INPUT TX1 ANALOG OUTPUT RX0 DSP56002 TDD RDD TDC RDC TDE RCE MSI SRD STD SCK SC2 SERIAL CLOCK SERIAL SYNC TRANSMIT DATA DSP DATA DSP DATA RECEIVE DATA CODEC DATA CODEC DATA Figure 6-72 Normal Mode Example 6.4.7.2.1 Normal Mode Transmit The conditions for data transmission from the SSI are as follows: 1. Transmitter is Enabled (TE=1) 2. Frame sync (or clock in gated clock mode) is active When these conditions occur in normal mode, the next data word will be transferred from TX to the transmit shift register, the TDE flag will be set (transmitter empty), and the transmit interrupt will occur if TIE equals one (transmit interrupt enabled.) The new data word will be transmitted immediately. The transmit data output (STD) is three-stated, except during the data transmission period. The optional frame sync output, flag outputs, and clock outputs are not three-stated even if both receiver and transmitter are disabled. The optional output flags are always updated at the beginning of the frame, regardless of TE. The state of the flag does not change for the entire frame. 6 - 130 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Figure 6-73 is an example of transmitting data using the SSI in the normal mode with a continuous clock, a bit-length frame sync, and 16-bit data words. The purpose of the program is to interleave and transmit right and left channels in a compact disk player. Four SSI pins are used: 1. SC0 is used as an output flag to indicate right-channel data (OF0=1) or left-channel data (OF0=0) 2. SC2 is TX and RX frame sync out Freescale Semiconductor, Inc... 3. STD is transmit data out 4. SCK clocks the transmit data out Equates are set for convenience and readability. Test data is then put in the low X: memory locations. The transmit interrupt vector contains a JSR instruction (which forms a long interrupt). The data pointer and channel flag are initialized before initializing CRA and CRB. It is assumed that the DSP CPU and SSI have been previously reset. At this point, the SSI is ready to transmit except that the interrupt is masked because the MR was cleared on reset and Port C is still configured as general-purpose I/O. Unmasking the interrupt and enabling the SSI pins allows transmission to begin. A “jump to self” instruction causes the DSP to hang and wait for interrupts to transmit the data. When an interrupt occurs, a JSR instruction at the interrupt vector location causes the XMT routine to be executed. Data is then moved to the TX register, and the data pointer is incremented. The flag is tested by the JSET instruction and, if it is set, a jump to left occurs, and the code for the left channel is executed. If the flag is not set, the code for the right channel is executed. In either case, the channel flag in X0 and then the output flag are set to reflect the channel being transmitted. Control is then returned to the main program, which will wait for the next interrupt. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 131 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... ;************************************************* ; SSI and other I/O EQUATES* ;************************************************* IPR EQU $FFFF CRA EQU $FFEC CRB EQU $FFED PCC EQU $FFE1 TX EQU $FFEF FLG EQU $0010 ORG X:0 DC $AAAA00 DC $333300 DC $CCCC00 DC $F0F000 ;************************************************* ; INTERRUPT VECTOR* ;************************************************* ORG P:$0010 JSR XMT ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG P:$40 MOVE #0,R0 MOVE #3,M0 MOVE #0,X0 MOVE X0,X:FLG ;************************************************* ; Initialize SSI Port* ;************************************************* MOVEP #$3000,X:IPR MOVEP #$401F,X:CRA MOVEP #$5334,X:CRB ;Data to transmit. ;Pointer to data buffer. ;Set modulus to 4. ;Initialize channel flag for SSI flag. ;Start with right channel first. ;Set interrupt priority register for SSI. ;Set continuous clock=5.12/32 MHz ;word length=16. ;Enable TIE and TE; make clock and ;frame sync outputs; frame ;sync=bit mode; synchronous mode; ;make SC0 an output. Figure 6-73 Normal Mode Transmit Example (Sheet 1 of 2) 6 - 132 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... ;************************************************* ; Init SSI Interrupt* ;************************************************* ANDI #$FC,MR MOVEP #$01F8,X:PCC JMP * ;************************************************* ; MAIN INTERRUPT ROUTINE* ;************************************************* XMT MOVEP X:(R0);pl,X:TX JSET #0,X:FLG,LEFT RIGHT BCLR #0,X:CRB MOVE #>$01,X0 MOVE X0,X:FLG RTI LEFT BSET #0,X:CRB MOVE #>$00,X0 MOVE X0,X:FLG RTI END ;Unmask interrupts. ;Turn on SSI port. ;Wait for interrupt. ;Move data to TX register. ;Check channel flag. ;Clear SC0 indicating right channel data ;Set channel flag to 1 for next data. ;Set SC0 indicating left channel data. ;Clear channel flag for next data. Figure 6-73 Normal Mode Transmit Example (Sheet 2 of 2) 6.4.7.2.2 Normal Mode Receive If the receiver is enabled, a data word will be clocked in each time the frame sync signal is generated (internal) or detected (external). After receiving the data word, it will be transferred from the SSI receive shift register to the receive data register (RX), RDF will be set (receiver full), and the receive interrupt will occur if it is enabled (RIE=1). The DSP program has to read the data from RX before a new data word is transferred from the receive shift register; otherwise, the receiver overrun error will be set (ROE=1). Figure 6-74 illustrates the program that receives the data transmitted by the program shown in Figure 6-73. Using the flag to identify the channel, the receive program receives the right- and left-channel data and separates the data into a right data buffer and a left data buffer. The program shown in Figure 6-74 begins by setting equates and then using a JSR instruction at the receive interrupt vector location to form a long interrupt. The main program starts by initializing pointers to the right and left data buffers. The IPR, CRA, and CRB are then initialized. The clock divider bits in the CRA do not have to be set since an external receive clock is specified (SCKD=0). Pin SC0 is specified as an input flag (SYN=1, SCD0=0); pin SC2 is specified as TX and RX frame sync (SYN=1, SCD2=0). The SSI port is then enabled and interrupts are unmasked, which allows the MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 133 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SSI port to begin data reception. A jump-to-self instruction is then used to hang the processor and allow interrupts to receive the data. Normally, the processor would execute useful instructions while waiting for the receive interrupts. When an interrupt occurs, the JSR instruction at the interrupt vector location transfers control to the RCV subroutine. The input flag is tested, and data is put in the left or right data buffer depending on the results of the test. The RTI instruction then returns control to the main program, which will wait for the next interrupt. Freescale Semiconductor, Inc... ;************************************************* ; SSI and other I/O EQUATES* ;************************************************* IPR EQU $FFFF SSISR EQU $FFEE CRA EQU $FFEC CRB EQU $FFED PCC EQU $FFE1 RX EQU $FFEF FLG EQU $0010 ;************************************************* ; INTERRUPT VECTOR* ;************************************************* ORG P:$000C JSR RCV ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG P:$40 MOVE #0,R0 MOVE #$08,R1 MOVE #1,M0 MOVE #1,M1 ;Pointer to memory buffer for ;received data. Note data will be ;split between two buffers which are ;modulus 2. Figure 6-74 Normal Mode Receive Example (Sheet 1 of 2) 6 - 134 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) ;************************************************* ; Initialize SSI Port* Freescale Semiconductor, Inc... ;************************************************* MOVEP #$3000,X:IPR MOVEP #$4000,X:CRA MOVEP #$A300,X:CRB ;Set interrupt priority register for SSI. ;Set word length = 16 bits. ;Enable RIE and RE; synchronous ;mode with bit frame sync; ;clock and frame sync are ;external; SC0 is an output. ;************************************************* ; Init SSI Interrupt* ;************************************************* ANDI #$FC,MR MOVEP #$01F8,X:PCC JMP * ;Unmask interrupts. ;Turn on SSI port. ;Wait for interrupt. ;************************************************* ; MAIN INTERRUPT ROUTINE* ;************************************************* RCV JSET #0,X:SSISR, RIGHT LEFT MOVEP X:RX,X:(RO)+ RTI RIGHT MOVEP X:RX,X:(R1)+ RTI END ;Test SCO flag. ;If SCO clear, receive data ;into left buffer (R0). ;If SCO set, receive data ;into right buffer (R1). Figure 6-74 Normal Mode Receive Example (Sheet 2 of 2) 6.4.7.3 Network Mode Examples The network mode, the typical mode in which the DSP would interface to a TDM codec network or a network of DSPs, is compatible with Bell and CCITT PCM data/operation formats. The DSP may be a master device (see Figure 6-75) that controls its own private network or a slave device that is connected to an existing TDM network, occupying one or more time slots. The key characteristic of the network mode is that each time slot (data word time) is identified by an interrupt or by polling status bits, which allows the option of ignoring the time slot or transmitting data during the time slot. The receiver operates in the same manner except that data is always being shifted into the receive shift register and transferred to the RX. The DSP reads the receive data register and uses or discards the contents. Overrun and underrun errors are detected. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 135 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MASTER TRANSMIT MASTER RECEIVE DSP56002 MASTER DSP56002 SLAVE 1 DSP56002 SLAVE 3 STD STD STD STD SRD SRD SRD SRD SCK SCK SCK SCK SC2 TIME SLOT 1 DSP56002 SLAVE 2 SC2 TIME SLOT 2 SC2 TIME SLOT 3 SC2 TIME SLOT 4 Freescale Semiconductor, Inc... MASTER CLOCK MASTER SYNC Figure 6-75 Network Mode Example The frame sync signal indicates the beginning of a new data frame. Each data frame is divided into time slots; transmission or reception can occur in each time slot (rather than in just the frame sync time slot as in normal mode). The frame rate dividers (controlled by DC4, DC3, DC2, DC1, and DC0) control the number of time slots per frame from 2 to 32. Time-slot assignment is totally under software control. Devices can transmit on multiple time slots, receive multiple time slots, and the time-slot assignment can be changed dynamically. A simplified flowchart showing operation of the network mode is shown in Figure 6-76. Two counters are used to track the current transmit and receive time slots. Slot counter one (SLOTCT1) is used to track the transmit time slot; slot counter two (SLOTCT2) is used for receive. When the transmitter is empty, it generates an interrupt; a test is then made to see if it is the beginning of a frame. If it is the beginning of a frame, SLOTCT1 is cleared to start counting the time slots. If it is not the beginning of a frame, SLOTCT1 is incremented. The next test checks to see if the SSI should transmit during this time slot. If it is time to transmit, data is written to the TX; otherwise, dummy data is written to the TSR, which prevents a transmit underrun error from occurring and three-states the STD pin. The DSP can then return to what it was doing before the interrupt and wait for the next interrupt to occur. SLOTCT1 should reflect the data in the shift registers to coincide with TFS. Software must recognize that the data being written to TX will be transmitted in time slot SLOTCT1 plus one. 6 - 136 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA MOTOROLA For More Information On This Product, Go to: www.freescale.com PORT C WRITE DATA TO TX YES CLEAR SLOT NUMBER SLOTCT1 YES EXIT WRITE DUMMY DATA TO TSR NO INCREMENT SLOT NUMBER SLOTCT1 = SLOTCT1 + 1 NO KEEP DATA YES CLEAR SLOT NUMBER SLOTCT2 = 0 YES Figure 6-76 TDM Network Software Flowchart MY TURN TO TRANSMIT? SLOTCT1 = MYSLOT? TEST FOR FRAME SYNC TFS = 1? TRANSMITTER EMPTY INTERRUPT EXIT IS DATA FOR ME? SLOTCT2 = MYSLOT? TEST FOR FRAME SYNC RFS = 1? READ DATA FROM RX RECEIVER FULL INTERRUPT Freescale Semiconductor, Inc... NO DISCARD DATA INCREMENT SLOT NUMBER SLOTCT2 = SLOTCT2 + 1 NO Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6 - 137 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... The receiver operates in a similar manner. When the receiver is full, an interrupt is generated, and a test is made to see if this is the beginning of a frame. If it is the beginning of a frame, SLOTCT2 is cleared to start counting the time slots. If it is not the beginning of a frame, SLOTCT2 is incremented. The next test checks to see if the data received is intended for this DSP. If the current time slot is the one assigned to the DSP receiver, the data is kept; otherwise, the data is discarded, and the DSP can then return to what it was doing before the interrupt. SLOTCT2 should reflect the data in the receive shift register to coincide with the RFS flag. Software must recognize that the data being read from RX is for time slot SLOTCT2 minus two. Initializing the network mode is accomplished by setting the bits in CRA and CRB as follows (see Figure 6-77): 1. The word length must be selected by setting WL1 and WL0. In this example, an 8-bit word length was chosen (WL1=0 and WL0=0). 2. The number of time slots is selected by setting DC4–DC0. Four time slots were chosen for this example (DC4–DC0=$03). 3. The serial clock rate must be selected by setting PSR and PM7–PM0 (see Table 6-15 (a), Table 6-15 (b), and Table 6-16). 4. RE and TE must be set to activate the transmitter and receiver. If interrupts are to be used, RIE and TIE should be set. RIE and TIE are usually set after everything else is configured and the DSP is ready to receive interrupts. 5. The network mode must be selected (MOD=1). 6. A continuous clock is selected in this example by setting GCK=0. 7. Although it is not required for the network mode, synchronous clock control was selected (SYN=1). 8. The frame sync length was chosen in this example as word length (FSL1=0) for both transmit and receive frame sync (FSL0=0). Any other combinations could have been selected, depending on the application. 9. Control bits SHFD, SCKD, SCD2, SCD1, SCD0, and the flag bits (OF1 and OF0) should be set as needed for the application. 6 - 138 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SSI CONTROL REGISTER A (CRA) (READ/WRITE) X:$FFEC 15 14 13 12 11 10 PSR 0 0 0 0 0 WL1 WL0 DC4 DC3 8-BIT WORD LENGTH 9 8 1 DC2 1 DC1 7 6 5 4 3 2 1 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 6 5 4 3 2 1 0 SCD2 SCD1 SCD0 OF1 OF0 DC0 FOUR TIME SLOTS Freescale Semiconductor, Inc... SSI CONTROL REGISTER B (CRB) (READ/WRITE) X:$FFED 15 14 13 12 RIE TIE RE TE 11 10 9 8 7 1 0 1 0 0 SHFD SCKD SCD2 SERIAL CONTROL 2 DIRECTION 1 = OUTPUT (MASTER) 0 = INPUT (SLAVE) MOD SSI MODE SELECT 1 = NETWORK GCK GATED CLOCK CONTROL 0 = CONTINUOUS CLOCK SCKD CLOCK SOURCE DIRECTION 1 = OUTPUT (MASTER) 0 = INPUT (SLAVE) SYN SYNC/ASYNC CONTROL 1 = SYNCHRONOUS FLS0 FRAME SYNC LENGTH 0 0 =TX, RX SYNC SAME LENGTH FSL1 FRAME SYNC LENGTH 1 0 = WORD WIDTH 7 6 5 4 3 2 1 0 X:$FFEE RDF TDE ROE TUE RFS TFS IF1 IF0 X:$FFEE * * * * * * * * SSI STATUS REGISTER (SR) (READ) SSI TIME SLOT REGISTER B (TSR) (WRITE) SERIAL CLOCK FRAME SYNC INTERNAL TX FLAGS AND INTERRUPTS SERIAL DATA 4 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 1 S INTERNAL RX FLAGS AND INTERRUPTS Figure 6-77 Network Mode Initialization MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 139 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) 6.4.7.3.1 Network Mode Transmit When TE is set, the transmitter will be enabled only after detection of a new data frame sync. This procedure allows the SSI to synchronize to the network timing. Freescale Semiconductor, Inc... Normal startup sequence for transmission in the first time slot is to write the data to be transmitted to TX, which clears the TDE flag. Then set TE and TIE to enable the transmitter on the next frame sync and to enable transmit interrupts. Alternatively, the DSP programmer may decide not to transmit in the first time slot by writing any data to the time slot register (TSR). This will clear the TDE flag just as if data were going to be transmitted, but the STD pin will remain in the high-impedance state for the first time slot. The programmer then sets TE and TIE. When the frame sync is detected (or generated), the first data word will be transferred from TX to the transmit shift register and will be shifted out (transmitted). TX being empty will cause TDE to be set, which will cause a transmitter interrupt. Software can poll TDE or use interrupts to reload the TX register with new data for the next time slot. Software can also write to TSR to prevent transmitting in the next time slot. Failing to reload TX (or writing to the TSR) before the transmit shift register is finished shifting (empty) will cause a transmitter underrun. The TUE error bit will be set, causing the previous data to be retransmitted. The operation of clearing TE and setting it again will disable the transmitter after completion of transmission of the current data word until the beginning of the next frame sync period. During that time, the STD pin will be three-stated. When it is time to disable the transmitter, TE should be cleared after TDE is set to ensure that all pending data is transmitted. The optional output flags are updated every time slot regardless of TE. To summarize, the network mode transmitter generates interrupts every time slot and requires the DSP program to respond to each time slot. These responses can be: 1. Write data register with data to enable transmission in the next time slot 2. Write the time slot register to disable transmission in the next time slot 3. Do nothing – transmit underrun will occur the at beginning of the next time slot, and the previous data will be transmitted 6 - 140 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... Figure 6-78 differs from the program shown in Figure 6-73 only in that it uses the network mode to transmit only right-channel data. A time slot is assigned for the left-channel data, which could be inserted by another DSP using the network mode. In the “Initialize SSI Port” section of the program, two words per frame are selected using CRA, and the network mode is selected by setting MOD to one in the CRB. The main interrupt routine, which waits to move the data to TX, only transmits data if the current time slot is for the right channel. If the current time slot is for the left channel, the TSR is written, which three-states the output to allow another DSP to transmit the left channel during the time slot. ;************************************************* ; SSI and other I/O EQUATES* ;************************************************* IPR CRA CRB PCC TX TSR FLG EQU EQU EQU EQU EQU EQU EQU ORG DC DC DC DC $FFFF $FFEC $FFED $FFE1 $FFEF $FFEE $0010 X:0 $AAAA00 $333300 $CCCC00 $F0F000 ;Data to transmit. ;************************************************* ; INTERRUPT VECTOR* ;************************************************* ORG JSR P:$0010 XMT ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG P:$40 MOVE #0,R0 ;Pointer to data buffer. MOVE #3,M0 ;Set modulus to 4. MOVE #0,X0 ;Initialize user flag for SSI flag. MOVE X0,X:FLG ;Start with the right channel. Figure 6-78 Network Mode Transmit Example Program (Sheet 1 of 2) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 141 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... ;************************************************* ; Initialize SSI Port* ;************************************************* MOVEP #$3000,X:IPR ;Set interrupt priority register for SSI. MOVEP #$411F,X:CRA ;Set continuous clock=5.12/32 MHz ;word length=16. MOVEP #$5B34,X:CRB ;Enable TIE and TE; make clock and ;frame sync outputs; frame ;sync=bit mode; synchronous mode; ;make SC0 an output. ;************************************************* ; Init SSI Interrupt* ;************************************************* ANDI #$FC,MR ;Unmask interrupts. MOVEP #$01F8,X:PCC ;Turn on SSI port. JMP * ;Wait for interrupt. ;************************************************* ; MAIN INTERRUPT ROUTINE* ;************************************************* XMT JSET #0,X:FLG,LEFT ;Check user flag. RIGHT BCLR #0,X:CRB ;Clear SC0 indicating right channel data MOVEP X:(R0)+,X:TX Move data to TX register. MOVE #>$01,X0 ;Set user flag to 1 MOVE X0,X:FLG ;for next data. RTI LEFT BSET #0,X:CRB ;Set SC0 indicating left channel data. MOVEP X0,X:TSR ;Write to TSR register. MOVE #>$00,X0 ;Clear user flag MOVE X0,X:FLG ;for next data. RTI END Figure 6-78 Network Mode Transmit Example Program (Sheet 2 of 2) 6 - 142 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) ;************************************************* ; SSI and other I/O EQUATES* Freescale Semiconductor, Inc... ;************************************************* IPR EQU $FFFF SSISR EQU $FFEE CRA EQU $FFEC CRB EQU $FFED PCC EQU $FFE1 RX EQU $FFEF ;************************************************* ; INTERRUPT VECTOR* ;************************************************* ORG JSR P:$000C RCV ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG MOVE MOVE MOVE MOVE P:$40 #0,R0 #$08,R1 #3,M0 #3,M1 ;Pointer to memory buffer for ;received data. Note data will be ;split between two buffers which are ;modulus 4. ;************************************************* ; Initialize SSI Port* ;************************************************* MOVEP MOVEP MOVEP #$3000,X:IPR #$4100,X:CRA #$AB00,X:CRB ;Set interrupt priority register for SSI. ;Set word length = 16 bits. ;Enable RIE and RE; synchronous ;mode with bit frame sync; ;clock and frame sync are ;external; SC0 is an input. Figure 6-79 Network Mode Receive Example Program (Sheet 1 of 2) MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 143 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) ;************************************************* ; Init SSI Interrupt* ;************************************************* ANDI MOVEP JMP #$FC,MR #$01F8,X:PCC * ;Unmask interrupts. ;Turn on SSI port. ;Wait for interrupt. ;************************************************* Freescale Semiconductor, Inc... ; MAIN INTERRUPT ROUTINE* ;************************************************* RCV LEFT RIGHT JSET MOVEP RTI MOVEP RTI END #0,X:SSISR, RIGHT ;Test SCO flag. X:RX,X:(RO)+ ;If SCO clear, receive data ;into left buffer (R0). X:RX,X:(R1)+ ;If SCO set, receive data ;into right buffer (R1). Figure 6-79 Network Mode Receive Example Program (Sheet 2 of 2) 6.4.7.3.2 Network Mode Receive The receive enable will occur only after detection of a new data frame with RE set. The first data word is shifted into the receive shift register and is transferred to the RX, which sets RDF if a frame sync was received (i.e., this is the start of a new frame). Setting RDF will cause a receive interrupt to occur if the receiver interrupt is enabled (RIE=1). The second data word (second time slot in the frame) begins shifting in immediately after the transfer of the first data word to the RX. The DSP program has to read the data from RX (which clears RDF) before the second data word is completely received (ready to transfer to RX), or a receive overrun error will occur (ROE=1), and the data in the receiver shift register will not be transferred and will be lost. If RE is cleared and set again by the DSP program, the receiver will be disabled after receiving the current time slot in progress until the next frame sync (first time slot). This mechanism allows the DSP programmer to ignore data in the last portion of a data frame. Note: The optional frame sync output and clock output signals are not affected, even if the transmitter and/or receiver are disabled. TE and RE do not disable bit clock and frame sync generation. 6 - 144 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) To summarize, the network mode receiver receives every time slot data word unless the receiver is disabled. An interrupt can occur after the reception of each data word, or the programmer can poll RDF. The DSP program response can be 1. Read RX and use the data 2. Read RX and ignore the data Freescale Semiconductor, Inc... 3. Do nothing – the receiver overrun exception will occur at the end of the current time slot 4. Toggle RE to disable the receiver until the next frame, and read RX to clear RDF Figure 6-79 is essentially the same program shown in Figure 6-74 except that this program uses the network mode to receive only right-channel data. In the “Initialize SSI Port” section of the program, two words per frame are selected using the DC bits in the CRA, and the network mode is selected by setting MOD to one in the CRB. If the program in Figure 6-78 is used to transmit to the program in Figure 6-79, the correct data will appear in the data buffer for the right channel, but the buffer for the left channel will probably contain $000000 or $FFFFFF, depending on whether the transmitter output was high or low when TSR was written and whether the output was three-stated. 6.4.7.4 On-Demand Mode Examples A divide ratio of one (DC=00000) in the network mode is defined as the on-demand mode of the SSI because it is the only data-driven mode of the SSI – i.e., data is transferred whenever data is present (see Figure 6-80 and Figure 6-81). STD and SCK from DSP1 are connected to DSP2 – SRD and SC0, respectively. SC0 is used as an input clock pin in this application. Receive data and receive data clock are separate from the transmit signals. On-demand data transfers are nonperiodic, and no time slots are defined. When there is a clock in the gated clock mode, data is transferred. Although they are not necessarily needed, frame sync and flags are generated when data is transferred. Transmitter underruns (TUE) are impossible in this mode and are therefore disabled. In the on-demand transmit mode, two additional SSI clock cycles are automatically inserted between each data word transmitted. This procedure guarantees that frame sync will be low between every transmitted data word or that the clock will not be continuous between two consecutive words in the gated clock mode. The on-demand mode is similar to the SCI shift register mode with SSFTD equals one and SCKP equals one. The receiver should be configured to receive the bit clock and, if continuous clock is used, to receive an external frame sync. Therefore, for all full-duplex communication in on-demand mode, the asynchronous mode should be used. The on-demand mode is SPI compatible. MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 145 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... DSP56002 DSP1 DSP56002 DSP2 STD SRD SCK SCO SRD STD SC0 SCK Figure 6-80 On Demand Example Initializing the on-demand mode for the example illustrated in Figure 6-81 is accomplished by setting the bits in CRA and CRB as follows: 1. The word length must be selected by setting WL1 and WL0. In this example, a 24-bit word length was chosen (WL1=1 and WL0=1). 2. The on-demand mode is selected by clearing DC4–DC0. 3. The serial clock rate must be selected by setting PSR and PM7–PM0 (see Table 6-15 (a), Table 6-15 (b), and Table 6-16). 4. RE and TE must be set to activate the transmitter and receiver. If interrupts are to be used, RIE and TIE should be set. RIE and TIE are usually set after everything else is configured and the DSP is ready to receive interrupts. 5. The network mode must be selected (MOD=1). 6. A gated clock (GCK=1) is selected in this example. A continuous clock example is shown in Figure 6-78. 7. Asynchronous clock control was selected (SYN=0) in this example. 8. Since gated clock is used, the frame sync is not necessary. FSL1 and FSL0 can be ignored. 9. SCKD must be an output (SCKD=1). 10. SCD0 must be an input (SCD0=0). 11. Control bit SHFD should be set as needed for the application. Pins SC1 and SC2 are undefined in this mode (see Table 6-13) and should be programmed as general-purpose I/O pins. 6 - 146 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SSI CONTROL REGISTER A (CRA) (READ/WRITE) 15 14 X:$FFEC PSR 1 WL1 13 12 1 WL0 11 0 0 DC4 DC3 24-BIT WORD LENGTH 10 0 DC2 9 0 8 7 6 5 4 3 2 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 DC1 DC0 1 0 ON-DEMAND Freescale Semiconductor, Inc... SSI CONTROL REGISTER B (CRB) (READ/WRITE) X:$FFED 15 14 13 12 RIE TIE RE TE 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 FSL1 FSL0 SHFD 1 SCD2 SCD1 0 OF1 OF0 SCD0 SERIAL CONTROL 2 DIRECTION 0 = INPUT MOD SSI MODE SELECT 1 = NETWORK GCK GATED CLOCK CONTROL 1=GATED CL0CK SCKD CLOCK SOURCE DIRECTION 1 = OUTPUT SYN SYNC/ASYNC CONTROL 0 = ASYNCHRONOUS TRANSMIT CLOCK 24-BIT DATA FROM DSP1 TO DSP2 TRANSMIT DATA RECEIVE CLOCK TWO SSI BIT CLOCKS (MIN.) RECEIVE DATA DSP2 TO DSP1 24-BIT DATA FROM DSP2 TO DSP1 NOTE: Two SSI bit clock times are automatically inserted between each data word. This guarantees frame sync will be low between every data word transmitted and the clock will not be continuous for two consecutive data words. Figure 6-81 On-Demand Data-Driven Network Mode MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 147 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DATA CHANGES SERIAL CLOCK DATA STABLE FRAME SYNC SERIAL DATA Freescale Semiconductor, Inc... DATA DATA (a) Continuous SERIAL CLOCK SERIAL DATA DATA DATA (b) Gated Figure 6-82 Clock Modes 6.4.7.4.1 On-Demand Mode – Continuous Clock This special case will not generate a periodic frame sync. A frame sync pulse will be generated only when data is available to transmit (see Figure 6-82(a)). The frame sync signal indicates the first time slot in the frame. The on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). Therefore, for simplex operation, the synchronous mode could be used; however, for full-duplex operation, the asynchronous mode must be used. Data transmission that is data driven is enabled by writing data into TX. Although the SSI is double buffered, only one word can be written to TX, even if the transmit shift register is empty. The receive and transmit interrupts function as usual using TDE and RDF; however, transmit and receive underruns are impossible for on-demand transmission and are disabled. This mode is useful for interfacing to codecs requiring a continuous clock. 6.4.7.4.2 On-Demand Mode – Gated Clock Gated clock mode (see Figure 6-82(b)) is defined for on-demand mode, but the gated clock mode is considered a frame sync source; therefore, in gated clock mode, the transmit clock must be internal (output) and the receive clock must be external (input). For ondemand mode, with internal (output) synchronous gated clock, output clock is enabled for 6 - 148 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) the transmitter and receiver when TX data is transferred to the transmit data shift register. This SPI master operating mode is shown in Figure 6-83. Word sync is inherent in the clock signal, and the operation format must provide frame synchronization. Freescale Semiconductor, Inc... Figure 6-84 is the block diagram for the program presented in Figure 6-85. This program contains a transmit test program that was written as a scoping loop (providing a repetitive sync) using the on-demand, gated, synchronous mode with no interrupts (polling) to transmit data to the program shown in Figure 6-86. The program also demonstrates using GPIO pins as general-purpose control lines. PC3 is used as an external strobe or enable for hardware such as an A/D converter. The transmit program sets equates for convenience and readability. Test data is then written to X: memory, and the data pointer is initialized. Setting M0 to two makes the buffer circular (modulo 3), which saves the step of resetting the pointer each loop. PC3 is configured as a general-purpose output for use as a scope sync, and CRA and CRB are then initialized. Setting the PCC bits begins SSI operation; however, no data will be transmitted until data is written to TX. PC3 is set high at the beginning of data transmission; data is then moved to TX to begin transmission. A JCLR instruction is then used to form a wait loop until TDE equals one and the SSI is ready for another data word to be transmitted. Two more data words are transmitted in this fashion (this is an arbitrary number chosen for this test loop). An additional wait is included to make sure that the frame sync has gone low before PC3 is cleared, indicating on the scope that transmission is complete. A wait of 100 NOPs is implemented by using the REP instruction before starting the loop again. MASTER SLAVE SHIFT REGISTER SHIFT REGISTER DSP1 DSP2 SPI CLOCK GENERATOR Figure 6-83 SPI Configuration MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 149 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DSP56002 DSP56002 PC3 SC2 SRD STD SCK Freescale Semiconductor, Inc... SCK 15K Figure 6-84 On-Demand Mode Example — Hardware Configuration ;************************************************* ; SSI and other I/O EQUATES* ;************************************************* CRA EQU $FFEC CRB EQU $FFED PCC EQU $FFE1 PCD EQU $FFE5 SSISR EQU $FFEE TX EQU $FFEF PCDDR EQU $FFE3 ORG DC DC DC X:0 $AA0000 $330000 $F00000 ;Data to transmit. ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG P:$40 MOVE MOVE #0,R0 #2,M0 ;Pointer to data buffer ;Length off buffer is 3 Figure 6-85 On-Demand Mode Transmit Example Program (Sheet 1 of 2) 6 - 150 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOVEP #$08,X:PCDDR ;SC0 (PC3) as general purpose output. MOVEP #$001F,X:CRA MOVEP #$1E30,X:CRB ;Set Word Length=8, CLK=5.12/32 MHz. ;Enable transmitter, Mode=On- Demand, ;Gated clock on, synchronous mode, ;Word frame sync selected, frame ;sync and clock are internal and ;output to port pins. ;Set PCC for SSI and MOVEP #$1F0,X:PCC Freescale Semiconductor, Inc... LOOP0 BSET #3,X:PCD TDE3 ;Set PC3 high (this is example enable ;or strobe for an external device :such as an ADC). MOVEP X:(R0);pl,X:TX ;Move data to TX register JCLR #6,X:SSISR,TDE1 ;Wait for TDE (transmit data register ;empty) to go high. MOVEP X:(R0);pl,X:TX ;Move next data to TX. JCLR #6,X:SSISR,TDE2 ;Wait for TDE to go high. MOVEP X:(R0);pl,X:TX ;Move data to TX. JCLR #6,X:SSISR,TDE3 ;Wait for TDE=1. FSC JSET #5,X:PCD,FSC ;Wait for frame sync to go low. NOTE: ;State of frame sync is directly ;determined by reading PC5. BCLR #3,X:PCD ;Set PC3 lo (example external enable). TDE1 TDE2 ;anything goes here (i.e., any processing) REP #100 NOP JMP LOOP0 ;Continue sequence forever. END Figure 6-85 On-Demand Mode Transmit Example Program (Sheet 2 of 2) Figure 6-86 is the receive program for the scoping loop program presented in Figure 6-85. The receive program also uses the on-demand, gated, synchronous mode with no interrupts (polling). Initialization for the receiver is slightly different than for the transmitter. In CRB, RE is set rather than TE, and SCKD and SCD2 are inputs rather than outputs. After initialization, a JCLR instruction is used to wait for a data word to be received (RDF=1). MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 151 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) When a word is received, it is put into the circular buffer and loops to wait for another data word. The data in the circular buffer will be overwritten after three words are received (does not matter in this application). Freescale Semiconductor, Inc... ;************************************************* ; SSI and other I/O EQUATES* ;************************************************* CRA EQU $FFEC CRB EQU $FFED PCC EQU $FFE1 PCD EQU $FFE5 SSISR EQU $FFEE RX EQU $FFEF PCDDR EQU $FFE3 ;************************************************* ; MAIN PROGRAM* ;************************************************* ORG P:$40 MOVE MOVE #0,R0 #2,M0 MOVEP #$001F,X:CRA MOVEP #$1E30,X:CRB MOVEP #$1F0,X:PCC ;Pointer to data buffer ;Length of buffer is 3 ;Set Word Length=8, CLK=5.12/32 MHz. ;Enable receiver, Mode=On-Demand, ;gated clock on, synchronous mode, ;Word frame sync selected, frame ;sync and clock are external. ;Set PCC for SSI LOOP RDF1 JCLR #7,X:SSISR,RDF1 ;Wait for RDF (receive data register ;Full) go to high. MOVEP X:RX,X:(R0)+ ;Read data from RX into memory. JMP LOOP ;Continue sequence forever. END Figure 6-86 On-Demand Mode Receive Example Program 6 - 152 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) Freescale Semiconductor, Inc... 6.4.8 Flags Two SSI pins (SC1 and SC0) are available in the synchronous mode for use as serial I/O flags. The control bits (OF1 and OF0) and status bits (IF1 and IF0) are double buffered to/from SC1 and SC0. Double buffering the flags keeps them in sync with TX and RX. The direction of SC1 and SC0 is controlled by SCD1 and SCD0 in CRB. Figure 6-87 shows the flag timing for a network mode example. Initially, neither TIE nor TE is set, and the flag outputs are the last flag output value. When TIE is set, a TDE interrupt occurs (the transmitter does not have to be enabled for this interrupt to occur). Data (D1) is written to TX, which clears TDE, and the transmitter is enabled by software. When the frame sync occurs, data (D1) is transferred to the transmit shift register, setting TDE. Data (D1) is shifted out during the first word time, and the output flags are updated. These flags will remain stable until the next frame sync. The TDE interrupt is then serviced by writing data (D2) to TX, clearing TDE. After the TSR completes transmission, the transmit pin is three-stated until the next frame sync Figure 6-88 shows a speaker phone example that uses a DSP56002 and two codecs. No additional logic is required to connect the codecs to the DSP. The two serial output flags in this example (OF1 and OF0) are used as chip selects to enable the appropriate codec for I/O. This procedure allows the transmit lines to be ORed together. The appropriate output flag pin changes at the same time as the first bit of the transmit word and remains stable until the next transmit word (see Figure 6-89). Applications include serial-device chip selects, implementing multidrop protocols, generating Bell PCM signaling frame syncs, and outputting status information. Initializing the flags (see Figure 6-89) is accomplished by setting SYN, SCD1, and SCD0. No other control bits affect the flags. The synchronous control bit must be set (SYN=1) to select the SC1 and SC0 pins as flags. SCD1 and SCD0 select whether SC1 and SC0 are inputs or outputs (input=0, output=1). The other bits selected in Figure 6-89 are chosen for the speaker phone example in Figure 6-88. In this example, the codecs require that the SSI be set for normal mode (MOD=0) with a gated clock (GCK=1) out (SCKD=1). Serial input flags, IF1 and IF0, are latched at the same time as the first bit is sampled in the receive data word (see Figure 6-90). Since the input was latched, the signal on the input flag pin can change without affecting the input flag until the first bit of the next receive data word. To initialize SC1 or SC0 as input flags, the synchronous control bit in CRB must be set to one (SYN=1) and SCD1 set to zero for pin SC1, and SCD0 must be set to zero for pin SC0. The input flags are bits 1 and 0 in the SSISR (at X:$FFEE). MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 153 6 - 154 For More Information On This Product, Go to: www.freescale.com PORT C * D1 D1 D1 D2 F1 WORD TIME TIME SLOT Figure 6-87 Output Flag Timing NOTES: 1. Fn = flags associated with Dn data. 2. Output flags are double buffered with transmit data. 3. Output flags change when data is transferred from TX to the transmit data shift register. 4. Initial flag outputs (*) = last flag output value. 5. Data and flags transition after external frame sync but not before rising edge of clock. OUTPUT FLAGS DATA WORD LOAD TSR TDE INTERRUPTS TE TIE FRAME SYNC START D2 D2 D3 F2 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MC15500 CODEC FILTER 1 SPEAKER PHONE TDD MICROPHONE TXI RDD TDC RDC SPEAKER RXO OF0 RCE OUTPUT FLAG 0 MSI Freescale Semiconductor, Inc... DSP5002 TDE SRD STD SCK SC0 MC15500 CODEC FILTER 2 SC1 TDD PHONE LINE INPUT TXI RDD TDC RDC PHONE LINE OUTPUT RXO OF1 TDE RCE OUTPUT FLAG 1 MSI NOTE: SC0 and SC1 are output flag 0 and 1 used to software select either filter 1 or 2. Figure 6-88 Output Flag Example MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 155 6 - 156 TIE RIE RE 13 For More Information On This Product, Go to: www.freescale.com PORT C B6 B5 B4 1 10 B3 1 9 B2 B1 FSL0 7 B0 SHFD 6 1 5 SCD2 4 1 3 OUTPUT FLAGS ARE ALWAYS VALID UNTIL THE NEXT WORD TRANSMITTED. FSL1 8 Figure 6-89 Output Flag Initialization 0 11 VALID OUTPUT FLAG B7 TE 12 OF0 AND LF1 ARE CLOCKED OUT ON THE RISING EDGE OF THE TRANSMIT CLOCK. OUTPUT FLAG TRANSMIT DATA TRANSMIT CLOCK SCD1 AND SCD0 SERIAL CONTROL 1 AND 0 DIRECTION 1 = OUTPUT SCKD CLOCK SOURCE DIRECTION 1 = OUTPUT SYN SYNC/ASYNC CONTROL 1 = SYNCHRONOUS GCK GATED CLOCK CONTROL 1 = GATED CLOCK MOD SSI MODE SELECT 0 = NORMAL 14 15 Freescale Semiconductor, Inc... 1 2 1 = FILTER 1 0 = FILTER 2 1 OF0 0 0 OF1 1 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) X:$FFEE 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF1 IF0 SSI STATUS REGISTER (SSISR) (READ) INPUT FLAGS RECEIVE CLOCK RECEIVE DATA B7 B6 B5 B4 B3 B2 B1 B0 Freescale Semiconductor, Inc... INPUT FLAG SAMPLE Figure 6-90 Input Flags 6.4.9 Example Circuits The DSP-to-DSP serial network shown in Figure 6-91 uses no additional logic chips for the network connection. All serial data is synchronized to the data source (all serial clocks and serial syncs are common). This basic configuration is useful for decimation and data reduction when more processing power is needed than one DSP can provide. Cascading DSPs in this manner is useful in several network topologies including star and ring networks. DSP56002 DSP56002 DSP56002 DSP56002 DATA IN DATA OUT SRD STD SRD STD SRD STD SRD STD SCK SCK SCK SCK SC2 SC2 SC2 SC2 SERIAL CLOCK SERIAL SYNC Figure 6-91 SSI Cascaded Multi-DSP System MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 157 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SYNCHRONOUS SERIAL INTERFACE (SSI) TDM networks are useful to reduce the wiring needed for connecting multiple processors. A TDM parallel topology, such as the one shown in Figure 6-92, is useful for interpolating filters. Serial data can be received simultaneously by all DSPs, processing can occur in parallel, and the results are then multiplexed to a single serial data out line. This configuration can be cascaded and/or looped back on itself as needed to fit a particular application (see Figure 6-93). The serial and parallel configurations can be combined to form the array processor shown in Figure 6-94. A nearest neighbor array, which is applicable to matrix relaxation processing, is shown in Figure 6-95. To simplify the drawing, only the center DSP is connected in this illustration. In use, all DSPs would have four three-state buffers connected to their STD pin. The flags (SC0 and SC1) on the control master operate the three-state buffers, which control the direction that data is transferred in the matrix (north, south, east, or west). The bus architecture shown in Figure 6-96 allows data to be transferred between any two DSPs. However, the bus must be arbitrated by hardware or a software protocol to prevent collisions. The master/slave configuration shown in Figure 6-97 also allows data to be transferred between any two DSPs but simplifies network control. 6 - 158 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DSP56002 SRD STD SCK SC2 Freescale Semiconductor, Inc... DSP56002 SRD STD SCK SERIAL DATA IN SERIAL DATA OUT SC2 DSP56002 SRD STD SCK SC2 DSP56002 SRD STD SCK SC2 SERIAL SYNC SERIAL CLOCK Figure 6-92 SSI TDM Parallel DSP Network MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 159 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DSP56002 Freescale Semiconductor, Inc... SRD DSP56002 STD SRD SCK SCK SC2 SC2 DSP56002 SRD DSP56002 STD SRD SCK SC2 SC2 DSP56002 STD SRD STD SCK SCK SC2 SC2 DSP56002 SRD STD SCK DSP56002 SRD STD DSP56002 STD SRD STD SCK SCK SC2 SC2 SERIAL CLOCK FRAME SYNC Figure 6-93 SSI TDM Connected Parallel Processing Array 6 - 160 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DSP56002 Freescale Semiconductor, Inc... SRD DSP56002 STD SRD STD SRD STD SCK SCK SCK SC2 SC2 SC2 DSP56002 SRD DSP56002 DSP56002 STD SRD DSP56002 STD SRD STD SERIAL IN SERIAL OUT SCK SCK SCK SC2 SC2 SC2 DSP56002 SRD DSP56002 STD SRD STD SRD STD SCK SCK SCK SC2 SC2 SC2 DSP56002 SRD DSP56002 DSP56002 STD SRD DSP56002 STD SRD STD SCK SCK SCK SC2 SC2 SC2 SERIAL CLOCK SERIAL SYNC Figure 6-94 SSI TDM Serial/Parallel Processing Array MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 161 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) DSP56002 DSP56002 SRD SRD STD SC0 SCK SCK SCK SC1 SC2 SC2 SC2 DSP56002 Freescale Semiconductor, Inc... DSP56002 SRD SRD DSP56002 STD SRD STD DSP56002 STD SRD STD SCK SCK SCK SC2 SC2 SC2 DSP56002 SRD STD DSP56002 STD SRD DSP56002 STD SRD STD SCK SCK SCK SC2 SC2 SC2 SERIAL CLOCK FRAME SYNC Figure 6-95 SSI Parallel Processing — Nearest Neighbor Array 6 - 162 PORT C For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) SERIAL SYNC SERIAL CLOCK SERIAL DATA BUS Freescale Semiconductor, Inc... DSP56002 DSP56002 DSP56002 DSP56002 STD STD STD STD SRD SRD SRD SRD SCK SCK SCK SCK SC2 SC2 SC2 SC2 Figure 6-96 SSI TDM Bus DSP Network MOTOROLA PORT C For More Information On This Product, Go to: www.freescale.com 6 - 163 6 - 164 For More Information On This Product, Go to: www.freescale.com PORT C SRD SCK SC2 SC1 SC0 SRD SCK SC2 SC1 SC0 SC0 SC1 SC2 SCK SRD STD DSP56002 SLAVE 2 Figure 6-97 SSI TDM Master-Slave DSP Network NOTE: Flags can specify data types: control, address, and data. FLAG 0 FLAG 1 MASTER SYNC MASTER CLOCK STD DSP56002 SLAVE 1 STD DSP56002 MASTER MASTER RECEIVE MASTER TRANSMIT Freescale Semiconductor, Inc... SC0 SC1 SC2 SCK SRD STD DSP56002 SLAVE 3 Freescale Semiconductor, Inc. SYNCHRONOUS SERIAL INTERFACE (SSI) MOTOROLA Freescale Semiconductor, Inc. SECTION 7 Freescale Semiconductor, Inc... DSP56002 TIMER AND EVENT COUNTER MOTOROLA For More Information On This Product, Go to: www.freescale.com 7-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION CONTENTS 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 TIMER/EVENT COUNTER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 TIMER COUNT REGISTER (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4 TIMER CONTROL/STATUS REGISTER (TCSR) . . . . . . . . . . . . . . . . . . . . 7-5 7.5 TIMER/EVENT COUNTER MODES OF OPERATION . . . . . . . . . . . . . . . . 7-7 7.6 TIMER/EVENT COUNTER BEHAVIOR DURING WAIT and STOP . . . . . . 7-16 7.7 OPERATING CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.8 SOFTWARE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7-2 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION 7.1 INTRODUCTION This section describes the timer/event counter module*. The timer can use internal or external clocking and can interrupt the processor after a number of events (clocks) specified by a user program, or it can signal an external device after counting internal events. Freescale Semiconductor, Inc... The timer connects to the external world through the bidirectional TIO pin. When TIO is used as input, the module is functioning as an external event counter or is measuring external pulse width/signal period. When TIO is used as output, the module is functioning as a timer and TIO becomes the timer pulse. When the TIO pin is not used by the timer module it can be used as a general purpose I/O (GPIO) pin. Note: When the timer is disabled, the TIO pin becomes three-stated. To prevent undesired spikes from occurring, the TIO pin should be pulled up or down when it is not in use. 7.2 TIMER/EVENT COUNTER BLOCK DIAGRAM Figure 7-1 shows a block diagram of the timer module. It includes a 24-bit read-write Timer Control and Status Register (TCSR), a 24-bit read-write Timer Count Register (TCR), a 24-bit counter, and logic for clock selection and interrupt generation. GDB 24 24 24 24-bit Timer Control/ Status Register (TCSR) 24-bit Timer Count Register (TCR) 24 3 24-bit Counter Clock select CLK/2 TIO Timer interrupt Figure 7-1 Timer/Event Counter Module Block Diagram * The first version of the DSP56002 (mask number D41G) did not have the timer/event counter. Later versions of the DSP56002 which have different mask numbers do have the timer/event counter. This mask number can be found below the part number on each chip. MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7-3 Freescale Semiconductor, Inc. TIMER COUNT REGISTER (TCR) TIMER ENABLE TIMER INTERRUPT ENABLE INVERTER TIMER CONTROL BITS TIMER CONTROL/STATUS REGISTER (TCSR) ADDRESS X:$FFDE READ/WRITE 0 23 * * * * * * * * * * * * * DO DI DIR TS GPIO TC2 TC1 TC0 INV TIE TE (0) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0) Freescale Semiconductor, Inc... GENERAL PURPOSE I0 TIMER STATUS DIRECTION BIT DATA INPUT DATA OUTPUT RESERVED TIMER COUNT REGISTER (TCR) ADDRESS X:$FFDF READ/WRITE 23 0 * - reserved, read as zero, should be written with zero for future compatibility Figure 7-2 Timer/Event Counter Programming Model The DSP56002 views the timer as a memory-mapped peripheral occupying two 24-bit words in the X data memory space, and may use it as a normal memory-mapped peripheral by using standard polled or interrupt programming techniques.The programming model is shown in Figure 7-2. 7.3 TIMER COUNT REGISTER (TCR) The 24-bit read-write TCR contains the value (specified by the user program) to be loaded into the counter when the timer is enabled (TE=1), or when the counter has been decremented to zero and a new event occurs. If the TCR is loaded with n, the counter will be reloaded after (n+1) events. If the timer is disabled (TE=0) and the user program writes to the TCR, the value is stored there but will not be loaded into the counter until the timer becomes enabled. When the timer is enabled (TE=1) and the user program writes to the TCR, the value is stored there and will be loaded into the counter after the counter has been decremented to zero and a new event occurs. In Timer Modes 4 and 5, however, the TCR will be loaded with the current value of the counter on the appropriate edge of the TIO input signal (rather than with a value specified by the user program). The value loaded to the TCR represents the width or the period of 7-4 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER CONTROL/STATUS REGISTER (TCSR) the signal coming in on the TIO pin, depending on the timer mode. See Sections 7.5.4 and 7.5.5 for detailed descriptions of Timer Modes 4 and 5. Freescale Semiconductor, Inc... 7.4 TIMER CONTROL/STATUS REGISTER (TCSR) The 24-bit read/write TCSR controls the timer and verifies its status. The TCSR can be accessed by normal move instructions and by bit manipulation instructions. The control and status bits are described in the following paragraphs. 7.4.1 Timer Enable (TE) Bit 0 The TE bit enables or disables the timer. Setting the TE bit (TE=1) will enable the timer, and the counter will be loaded with the value contained in the TCR and will start decrementing at each incoming event. Clearing the TE bit will disable the timer. Hardware RESET and software RESET (RESET instruction) clear TE. 7.4.2 Timer Interrupt Enable (TIE) Bit 1 The TIE bit enables the timer interrupts after the counter reaches zero and a new event occurs. If TCR is loaded with n, an interrupt will occur after (n+1) events. Setting TIE (TIE=1) will enable the interrupts.When the bit is cleared (TIE=0) the interrupts are disabled. Hardware and software resets clear TIE. 7.4.3 Inverter (INV) Bit 2 The INV bit affects the polarity of the external signal coming in on the TIO input and the polarity of the output pulse generated on the TIO output. If TIO is programmed as an input and INV=0, the 0-to-1 transitions on the TIO input pin will decrement the counter. If INV=1, the 1-to-0 transitions on the TIO input pin will decrement the counter. If TIO is programmed as output and INV=1, the pulse generated by the timer will be inverted before it goes to the TIO output pin. If INV=0, the pulse is unaffected. In Timer Mode 4 (see Section 7.5.4 Timer Mode 4 (Pulse Width Measurement Mode)), the INV bit determines whether the high pulse or the low pulse is measured to determine input pulse width. In Timer Mode 5 (see Section 7.5.5 Timer Mode 5 (Period Measurement Mode)), the INV bit determines whether the period is measured between leading or trailing edges. In GPIO mode, the INV bit determines whether the data read from or written to the TIO pin shall be inverted (INV=1) or not (INV=0). INV is cleared by hardware and software resets. Note: Because of its affect on signal polarity, and on how GPIO data is read and written, MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7-5 Freescale Semiconductor, Inc. TIMER CONTROL/STATUS REGISTER (TCSR) the status of the INV bit is crucial to the timer’s function. Change it only when the timer is disabled (TE=0). 7.4.4 Timer Control (TC0-TC2) Bits 3-5 The three TC bits control the source of the timer clock, the behavior of the TIO pin, and the timer mode of operation. Table 7-1 summarizes the functionality of the TC bits. A detailed description of the timer operating modes is given in Chapter 3. Freescale Semiconductor, Inc... The timer control bits are cleared by hardware RESET and software RESET (RESET instruction). Note 1: If the clock is external, the counter will be decremented by the transitions on the TIO pin. The DSP synchronizes the external clock to its own internal clock. The external clock’s frequency should be lower than the maximum internal frequency divided by 4 (CLK/4). Note 2: The TC2-TC0 bits should be changed only when TE=0 (timer disabled) to ensure proper functionality. Table 7-1 Timer/Event Counter Control Bits TC2 TC1 TC0 TIO CLOCK MODE 0 0 0 GPIO* Internal Timer (Mode 0) 0 0 1 Output Internal Timer Pulse (Mode 1) 0 1 0 Output Internal Timer Toggle (Mode 2) 0 1 1 — — Reserved - Do Not Use 1 0 0 Input Internal Input Width (Mode 4) 1 0 1 Input Internal Input Period (Mode 5) 1 1 0 Input External Standard Time Counter (Mode 6) 1 1 1 Input External Event Counter (Mode 7) * - the GPIO function is enabled only if TC2-TC0 are all 0 (zero) and the GPIO bit is set. 7.4.5 General Purpose I/O (GPIO) Bit 6 If the GPIO bit is set (GPIO=1) and if TC2-TC0 are all zeros, the TIO pin operates as a general purpose I/O pin, whose direction is determined by the DIR bit. If GPIO=0 the general purpose I/O function is disabled. GPIO is cleared by hardware and software resets. Note: The case where TC2-TC0 are not all zero and GPIO=1 is undefined and should not be used 7.4.6 Timer Status (TS) Bit 7 When the TS bit is set, it indicates that the counter has been decremented to zero. 7-6 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION The TS bit is cleared when the TCSR is read. The bit is also cleared when the timer interrupt is serviced (timer interrupt acknowledge). TS is cleared by hardware and software resets. Freescale Semiconductor, Inc... 7.4.7 Direction (DIR) Bit 8 The DIR bit determines the behavior of the TIO pin when TIO acts as general purpose I/O. When DIR=0, the TIO pin acts as an input. When DIR=1, the TIO pin acts as an output. DIR is cleared by hardware and software resets. Note: The TIO pin can act as a general purpose I/O pin only when TC2-TC0 are all zero and the GPIO bit is set. If one of TC2, TC1 or TC0 is not 0, the GPIO function is disabled and the DIR bit has no effect. 7.4.8 Data Input (DI) Bit 9 When the TIO pin acts as a general purpose I/O input pin (TC2-TC0 are all zero and DIR=0), the contents of the DI bit will reflect the value the TIO pin. However, if the INV bit is set, the data in DI will be inverted. When GPIO mode is disabled or it is enabled in output mode (DIR=1), the DI bit reflects the value of the TIO pin, again depending on the status of the INV bit. DI is set by hardware and software resets. 7.4.9 Data Output (DO) Bit 10 When the TIO pin acts as a general purpose I/O output pin (TC2-TC0 are all zero and DIR=1), writing to the DO bit writes the data to the TIO pin. However, if the INV bit is set, the data written to the TIO pin will be inverted. When GPIO mode is disabled, writing to the DO bit will have no effect. DO is cleared by hardware and software resets. 7.4.10 TCSR Reserved bits (Bits 11-23) These reserved bits are read as zero and should be written with zero for future compatibility. 7.5 TIMER/EVENT COUNTER MODES OF OPERATION This section gives the details of each of the timer modes of operation. Table 7-1 on page 7-6 summarizes the items which determine the timer mode, including the configuration of the timer control bits, the function of the TIO pin, and the clock source. 7.5.1 Timer Mode 0 (Standard Timer Mode, Internal Clock, No Timer Output) Timer Mode 0 is defined by TCSR bits TC2-TC0 equal to 000. With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The counter is decremented by a clock derived from the internal DSP clock, divided by two (CLK/2). During the clock cycle following the point where the counter reaches 0, the TS bit is set and the timer generates an interrupt. The counter is reloaded with the value contained by the TCR, and the entire process is repeated until the timer is disabled (TE=0). Figure 7-3 illustrates Mode 0 MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7-7 Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION with the timer enabled. Figure 7-4 illustrates the events with the timer disabled. Note: It is recommended that the GPIO input function of Mode 0 only be activated with the timer disabled. If the processor attempts to read the DI bit to determine the GPIO pin direction, it must read the entire TCSR register, which would clear the TS bit and, thus, clear a pending timer interrupt. Freescale Semiconductor, Inc... 7.5.2 Timer Mode 1 (Standard Timer Mode, Internal Clock, Output Pulse Enabled) Timer Mode 1 is defined by TC2-TC0 equal to 001. With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The counter is decremented by a clock derived from the DSP’s internal clock, divided by two (CLK/2). During the clock cycle following the point where the counter reaches 0, the TS bit is set and the timer generates an interrupt. A pulse with a two clock cycle width and whose polarity is determined by the INV bit, will be put out on the TIO pin. The counter is reloaded with the First Event Write Preload (N) Last Event TE Clock (CLK/2) TCR Counter N N N-1 0 N TS Interrupt Figure 7-3 Standard Timer Mode (Mode 0) 7-8 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION Stop Counting Preload (N) First Event Freescale Semiconductor, Inc... TE Clock (CLK/2) TCR N Counter N-k N-k-1 N-k-1 N N-1 TS Interrupt Figure 7-4 Timer/Event Counter Disable value contained by the TCR. The entire process is repeated until the timer is disabled (TE=0). Figure 7-5 illustrates Timer Mode 1 when INV=0, and Figure 7-6 illustrates Timer Mode 1 when INV=1. 7.5.3 Timer Mode 2 (Standard Timer Mode, Internal Clock, Output Toggle Enabled) Timer Mode 2 is defined by TC2-TC0 equal to 010. With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The counter is decremented by a clock derived from the DSP’s internal clock, divided by two (CLK/2). MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7-9 Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION During the clock cycle following the point where the counter reaches 0, the TS bit in TCSR is set and, if the TIE is set, an interrupt is generated.The counter is reloaded with the value contained by the TCR and the entire process is repeated until the timer is disabled (TE=0). Each time the counter reaches 0, the TIO output pin will be toggled. The INV bit determines the polarity of the TIO output. Figure 7-7 illustrates Timer Mode 2. Freescale Semiconductor, Inc... 7.5.4 Timer Mode 4 (Pulse Width Measurement Mode) Timer Mode 4 is defined by TC2-TC0 equal 100. In this mode, TIO acts as a gating signal for the DSP’s internal clock. With the timer enabled (TE=1), the counter is driven by a clock derived from the DSP’s internal clock divided Write Preload (N) First Event Last Event New Event TE Clock (CLK/2) TCR N Counter N N-1 0 N N-1 Interrupt 2xCLK TIO Figure 7-5 Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=0) 7 - 10 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION by two (CLK/2). The counter is loaded with 0 by the first transition occurring on the TIO input pin and starts incrementing. When the first edge of opposite polarity occurs on TIO, the counter stops, the TS bit in TCSR is set and, if TIE is set, an interrupt is generated. The contents of the counter is loaded into the TCR. The user’s program can read the TCR, which now represents the widths of the TIO pulse. The process is repeated until the timer is disabled (TE=0).The INV bit determines whether the counting is enabled when TIO is high (INV=0) or when TIO is low (INV=1). Figure 7-8 illustrates Timer Mode 4 when INV=0 and Figure 7-9 illustrates Timer Mode 4 with INV=1. Freescale Semiconductor, Inc... Write Preload (N) First Event Last Event New Event TE Clock (CLK/2) TCR N Counter N N-1 0 N N-1 Interrupt 2xCLK TIO Figure 7-6 Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=1) MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 11 Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION Freescale Semiconductor, Inc... 7.5.5 Timer Mode 5 (Period Measurement Mode) Timer Mode 5 is defined by TC2-TC0 equal 101. In Timer Mode 5, the counter is driven by a clock derived from the DSP’s internal clock divided by 2 (CLK/2). With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR and starts incrementing. On each transition of the same polarity that occurs on TIO, the TS bit in TCSR is set and, if TIE is set, an interrupt is generated. The contents of the counter is loaded in the TCR. The user’s program can read the TCR and subtract consecutive values of the counter to determine the distance between TIO edges. The counter is not stopped and it continues to increment. The INV bit determines whether the period is measured between 0-to-1 transitions of TIO (INV=0), or between 1-to-0 transitions of TIO (INV=1). Figure 7-10 illustrates Timer Mode 5 when INV=0, and Figure 7-11 illustrates this mode with INV=1. Last Event First Event Last Event New Event TE Clock (CLK/2) TCR N Counter 0 N N-1 0 N N-1 Interrupt TIO Figure 7-7 Standard Timer Mode, Internal Clock, Output Toggle Enable 7 - 12 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION Freescale Semiconductor, Inc... 7.5.6 Timer Mode 6 (Standard Time Counter Mode, External Clock) Time Mode 6 is defined by TC2-TC0 equal 110. With the timer enabled (TE=1) the counter is loaded with the 1’s complement of the value contained by the TCR. The counter is incremented by the transitions on the incoming signal on the TIO input pin. After each increment, the counter value is loaded into the TCR. Thus, reading the TCR will give the value of the counter at any given moment. At the transition following the point where the counter reaches 0, the TS bit in TCSR is set and, if the TIE is set, an interrupt is generated.The counter will wrap around and the process is repeated until the timer is disabled (TE=0). The INV bit determines whether 0-to-1 transitions (INV=0) or 1-to-0 transitions (INV=1) will increment the counter. Figure 7-12 illustrates Timer Mode 6 when INV=0. Figure 7-13 illustrates Timer Mode 7 when INV=1. Stop Event Start Event Start Event TE Clock N TCR Counter 0 1 N-1 N 0 Interrupt TIO Figure 7-8 Pulse Width Measurement Mode (INV=0) MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 13 Freescale Semiconductor, Inc. TIMER/EVENT COUNTER MODES OF OPERATION 7.5.7 Timer Mode 7 (Standard Timer Mode, External Clock) Timer Mode 7 is defined by TC2-TC0 equal 111. Freescale Semiconductor, Inc... With the timer enabled (TE=1), the counter is loaded with the value contained by the TCR. The counter is decremented by the transitions of the signal coming in on the TIO input pin. At the transition that occurs after the counter has reached 0, the TS bit in TCSR is set and, if the TIE is set, the timer generates an interrupt. The counter is reloaded with the value Stop Event Start Event Start Event TE Clock TCR xxx Counter N yyy 0 1 N-1 N 0 Interrupt TIO Figure 7-9 Pulse Width Measurement Mode (INV=1) 7 - 14 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TIMER/EVENT COUNTER BEHAVIOR DURING WAIT and STOP contained by the TCR, and the entire process is repeated until the timer is disabled (TE=0). The INV bit determines whether 0-to-1 transitions (INV=0) or 1-to-0 transitions (INV=1) will decrement the counter. Figure 7-14 illustrates Timer Mode 7 when INV=0, and Figure 7-15 illustrates Timer Mode 7 when INV=1. Freescale Semiconductor, Inc... 7.6 TIMER/EVENT COUNTER BEHAVIOR DURING WAIT and STOP During the execution of the WAIT instruction, the timer clocks are active and the timer activity continues undisturbed. If the timer interrupt is enabled when the final event occurs, an interrupt will be generated and serviced. It is recommended that the timer be disabled before executing the STOP instruction because during the execution of the STOP instruction, the timer clocks are disabled and the timer activity will be stopped. If, for example, the TIO pin is used as input, the changes Periodic Event (First Event) Periodic Event TE Clock TCR N Counter M N+1 N N+1 N+2 M-1 M M+1 M+2 Interrupt TIO Figure 7-10 Period Measurement Mode (INV=0) MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 15 Freescale Semiconductor, Inc. OPERATING CONSIDERATIONS that occur while in STOP will be ignored. 7.7 OPERATING CONSIDERATIONS The value 0 for the Timer Count Register (TCR) is considered a boundary case and affects the behavior of the timer under the following conditions: Freescale Semiconductor, Inc... • If the TCR is loaded with 0, and the counter contained a non-zero value before the TCR was loaded, then after the timer is enabled, it will count 224 events, generate an interrupt, and then generate an interrupt for every new event. Periodic Event (First Event) Periodic Event TE Clock TCR N Counter M N+1 N N+1 N+2 M-1 M M+1 M+2 Interrupt TIO Figure 7-11 Period Measurement Mode (INV=1) 7 - 16 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SOFTWARE EXAMPLES • If the TCR is loaded with 0, and the counter contained a zero value prior to loading, then after the timer is enabled, it will generate an interrupt for every event. • If the TCR is loaded with 0 after the timer has been enabled, the timer will be loaded with 0 when the current count is completed and then generate an interrupt for every new event. Freescale Semiconductor, Inc... 7.8 SOFTWARE EXAMPLES 7.8.1 General Purpose I/O Input The following routine can be used to read the TIO input pin: MOVEP #$000040,X:TCSR ;clear TC2-TC0, set GPIO ;and clear INV for GPIO input here First Event Write Preload (N) Last Event TE TIO (Event) N+1 N TCR Counter N N+1 FFFF FFFF 0 0 Interrupt Figure 7-12 Standard Time Counter Mode, External Clock (INV=0) MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 17 Freescale Semiconductor, Inc. SOFTWARE EXAMPLES JSET #DI,X:TCSR,here ;spin here until TIO is set Freescale Semiconductor, Inc... 7.8.2 General Purpose I/O Output The following routine can be used to write the TIO output pin: MOVEP #$000140,X:TCSR ;clear TC2-TC0, set GPIO and ;set DIR for GPIO output, set TIO to 0 BSET NOP #DO,X:TCSR ;set TIO to 1 Write Preload (N) First Event Last Event TE TIO (Event) N+1 N TCR Counter N N+1 FFFF 0 FFFF 0 Interrupt Figure 7-13 Standard Timer Mode, External Clock (INV=1) 7 - 18 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SOFTWARE EXAMPLES NOP BCLR #DO,X:TCSR ;set TIO to 0 This routine generates a pulse on the TIO pin with the duration equal to 8 CLK (assuming no wait states, no external bus conflict, etc.) Freescale Semiconductor, Inc... 7.8.3 Timer Mode 0, Input Clock, GPIO Output, and No Timer Output The following program illustrates the standard timer mode with simultaneous GPIO. The timer is used to activate an internal task after 65536 clocks; at the end of the task the TIO pin is toggled to signal end of task. ORG JSR ORG P:$3C TASK P:MAIN_BODY ;this is timer interrupt vector address ;go and execute task (long interrupt) First Event Write Preload (N) Last Event TE TIO (Event) TCR Counter N N N-1 0 N Interrupt Figure 7-14 Standard Timer Mode, External Clock (INV=0) MOTOROLA DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 19 Freescale Semiconductor, Inc. SOFTWARE EXAMPLES MOVEP Freescale Semiconductor, Inc... BSET MOVEP BSET ANDI BSET #$000042,X:TCSR ;enable timer interrupts and enable GPIO ; (input!) and set DO =0 to have stable data #DIR,X:TCSR ;change DIR to output (clean 0, no spikes) #$00FFFF,X:TCR ;load 64k -1 into the counter #IPL,X:IPR ;enable IPL for timer #$CF,MR ;remove interrupt masking in status register #TE,X:TCSR ; timer enable ...... ; application program ..... task ..... ; task instructions .... end_of_task Write Preload (N) First Event Last Event TE TIO (Event) TCR N Counter N N-1 0 N Interrupt Figure 7-15 Standard Timer Mode, External Clock (INV=1) 7 - 20 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SOFTWARE EXAMPLES BSET BCLR RTI #DO,X:TCSR #DO,X:TCSR ;set TIO to signal end of task ;clear TIO ;return to main program Freescale Semiconductor, Inc... 7.8.4 Pulse Width Measurement Mode (Timer Mode 4) The following program illustrates the usage of the timer module for input pulse width measurement. The width is measured in this example for the low active period of the input pulse on the TIO pin and is stored in a table (in multiples of the chip operating clock divided by 2). ORG pulse_width DS X:$100 $100 ORG P:$3C MOVEP X:TCR,X:(r0)+ NOP ;define buffer in X memory internal ;measure up to 256 pulses ;this is timer interrupt vector address ;store width value in table ;second word of the short interrupt .... ORG P:MAIN_BODY ..... MOVE #PULSE_WIDTH,r0 ;r0 points to start of table MOVE #$FF,M0 ;modulo 100 to wrap around on end of table MOVEP #$000026,X:TCSR ;enable timer interrupts, mode 4 and set INV ;to measure the low active pulse BSET #IPL,X:IPR ;enable IPL for timer ANDI #$CF,MR ;remove interrupt masking in status register BSET #TE,X:TCSR ;timer enable ...... ; do other tasks ..... 7.8.5 Period Measurement Mode (Timer Mode 5) The following program illustrates the usage of the timer module for input period measurement. The period is measured in this example between 0 to 1 transitions of the input signal on TIO and is stored in a table (in multiples of the chip operating clock divided by 2). period temp MOTOROLA ORG DS DS X:$100 $100 $1 ;define buffer in X memory internal ;measure up to 256 pulses ;temporary storage DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com 7 - 21 Freescale Semiconductor, Inc. SOFTWARE EXAMPLES ORG JSR P:$3C MEASURE ORG P:MAIN_BODY ;this is timer interrupt vector address ;long interrupt to measure period .... Freescale Semiconductor, Inc... ..... MOVE #0,X:TEMP MOVE #PERIOD,r0 MOVE #$FF,M0 MOVEP #$00002A,X:TCSR BSET #IPL,X:IPR ANDI #$CF,MR BSET #TE,X:TCSR ;clear temporary storage ;r0 points to start of table ;modulo 100 to wrap around on end of table ;enable timer interrupts, mode 5 ;enable IPL for timer ;remove interrupt masking in status register ;timer enable ...... ; do other tasks ..... measure MOVEP X:TCR,A ;read new counter value MOVE X:TEMP,X0 ;retrieve former read value (initially zero) SUB X0,A A,X:TEMP ;compute delta (i.e. new -old) and store the ;new read value in temp MOVE A,X:(R0)+ ;store period value in table RTI 7 - 22 DSP56002 TIMER AND EVENT COUNTER For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. APPENDIX A Freescale Semiconductor, Inc... BOOTSTRAP AND ROM CODE 0100101001011010 1010101010110110 1 0 0101001010010111 0 1010101010010111 1 0 00 0 1000101010100100 0100010101011101 0 1 0 0 1 1010100011010101 1001011001110100 0 1 1 0 0 0100101001011010 1 11010101010010111 1010101010110110 1 1 0100101001011010 1010101010110110 0101001010010111 0 0 0 1 0 0101001010010111 0 1 0 1 1010101010010111 1000101010100100 0100010101011101 1 1000101010100100 0100010101011101 1011011101101001101001010101010 1010100011010101 1001011001110100 0 1 0 0 1010100011010101 1001011001110100 1 0101101011010100110110101011010 1010101010110110 0 1 00100101001011010 1 1010010101010010101010010101010 1 0 0100101001011010 1010101010110110 1010101010010111 0101001010010111 11010101010010111 0101001010010111 1000101010100100 0100010101011101 00101010101010101010000010101100 1 0 1 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010100011010101 1001011001110100 1000101010100100 0100010101011101 1 0 10110111011010011010010101 1010101010010111 0101001010010111 0100101001011010 1010101010110110 1010100011010101 1001011001110100 1000101010100100 0100010101011101 0 1 01010 1010101010010111 0101001010010111 10110111011010011010010101 1010100011010101 1001011001110100 1000101010100100 0100010101011101 01010 1010100011010101 1001011001110100 1000101010100100 0100010101011101 10110111011010011010010101 1010100011010101 1001011001110100 01010 MOTOROLA For More Information On This Product, Go to: www.freescale.com A-1 Freescale Semiconductor, Inc. SECTION CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Freescale Semiconductor, Inc... A.1 A-2 BOOTSTRAP AND ROM CODE For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION A.1 INTRODUCTION Freescale Semiconductor, Inc... This section presents the Bootstrap program contained in the DSP56002 64-word Boot ROM. This program can load the internal program RAM starting at P:$0 from an external EPROM or the Host Interface, and may load any program RAM segment from the SCI serial interface. If MC:MB:MA=001, the program loads the internal program RAM from 1,536 consecutive byte-wide P memory locations, starting at P:$C000 (bits 7-0). These will be packed into 512 24-bit words and stored in contiguous program RAM memory locations starting at P:$0. After assembling one 24-bit word, the bootstrap program stores the result in internal program RAM memory. Note that the routine loads data starting with the least significant byte of P:$0. If MC:MB:MA=10x, the program loads internal program RAM from the Host Interface, starting at P:$0. If only a portion of the P memory is to be loaded, the Host Interface bootstrap load program may be stopped by setting Host Flag 0 (HF0). This will terminate the bootstrap loading operation and start executing the loaded program at location P:$0 of the internal program RAM. If MC:MB:MA=11x, the program loads program RAM from the SCI interface. The number of program words to be loaded and the starting address must be specified. The SCI bootstrap code expects to receive 3 bytes specifying the number of program words, 3 bytes specifying the address in internal program RAM to start loading the program words and then 3 bytes for each program word to be loaded. The number of words, the starting address and the program words are received least significant byte first followed by the mid and then by the most significant byte. After receiving the program words, program execution starts at the same address where loading started. The SCI is programmed to work in asynchronous mode with 8 data bits, 1 stop bit and no parity. The clock source is external and the clock frequency must be 16x the baud rate. After each byte is received, it is echoed back through the SCI transmitter. The bootstrap program listing is shown in Figure A-1. MOTOROLA BOOTSTRAP AND ROM CODE For More Information On This Product, Go to: www.freescale.com A-3 Freescale Semiconductor, Inc. INTRODUCTION Freescale Semiconductor, Inc... ; BOOTSTRAP CODE FOR DSP56002 - (C) Copyright 1990 Motorola Inc. ; Revised October 24, 1990. ; ; Bootstrap through the Host Interface, External EPROM or SCI. ; ; BOOT EQU $C000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located PBC HSR HRX PCC SCR SSR SCCR SRXL STXL START EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFE0 $FFE9 $FFEB $FFE1 $FFF0 $FFF1 $FFF2 $FFF4 $FFF4 ; Port B Control Register ; Host Status Register ; Host Receive Register ; Port C Control Register ; SCI Control Register ; SCI Status Register ; SCI Clock Control Register ; SCI Receive Register Low ; SCI Transmit Register Low ORG PL:$0,PL:$0 ; bootstrap code starts at $0 MOVE #<0,R0 JCLR JSET #4,OMR,EPROMLD #1,OMR,SCILD ; default P address where prog ; will begin loading ; If MC:MB:MA=0xx, go load from EPROM ; If MC:MB:MA=11x, go load from SCI ; This routine loads from the Host Interface. ; MC:MB:MA=100 - reserved ; MC:MB:MA=101 - Host HOSTLD _LBLA _LBLB BSET DO JCLR ENDDO JMP #0,X:PBC #512,_LOOP3 #3,X:HSR,_LBLB JCLR #0,X:HSR,_LBLA <_LOOP3 MOVEP X:HRX,P:(R0)+ _LOOP3 JMP ; Configure Port B as Host ; Load 512 instruction words ; if HF0=1, stop loading data. ; Must terminate the do loop <FINISH ; Wait for HRDF to go high ; (meaning data is present). ; Store 24-bit data in P mem. ; and go get another 24-bit word. ; finish bootstrap Figure A-1 DSP56002 Bootstrap Program (Sheet 1 of 3) A-4 BOOTSTRAP AND ROM CODE For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION ; This routine loads from external EPROM. ; MC:MB:MA=001 EPROMLD MOVE DO DO MOVEM REP ASR #BOOT,R1 #512,_LOOP1 #3,_LOOP2 P:(R1)+,A2 #8 A _LOOP2 Freescale Semiconductor, Inc... _LOOP1 FINISH MOVEM A1,P:(R0)+ ; and go get another 24-bit word. MOVE #<0,R1 JMP <BOOTEND ; R1 = Ext address of EPROM ; Load 512 instruction words ; Each instruction has 3 bytes ; Get the 8 LSB from ext. P mem. ; Shift 8 bit data into A1 ; Get another byte. ; Store 24-bit result in P mem. ; finish bootstrap ; This routine loads from the SCI. ; MC:MB:MA=110 - external SCI clock ; MC:MB:MA=111 - reserved SCILD MOVEP JMP NOP #$0302,X:SCR <EXTC ; Configure SCI Control Reg ; go to next boot rom segment ; just to fill the last space ORG PL:$100,PL:$100 ; starting address of 2nd 32-word bootstrap ROM EXTC MOVEP MOVEP #$C000,X:SCCR #7,X:PCC ; Configure SCI Clock Control Reg ; Configure SCLK, TXD and RXD _SCI1 DO #6,_LOOP6 JCLR MOVEP JCLR MOVEP REP ASR #2,X:SSR,* X:SRXL,A2 #1,X:SSR,* A2,X:STXL #8 A ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address ; Wait for RDRF to go high ; Put 8 bits in A2 ; Wait for TDRE to go high ; echo the received byte MOVE MOVE DO A1,R0 A1,R1 A0,_LOOP4 DO JCLR MOVEP JCLR MOVEP REP ASR #3,_LOOP5 #2,X:SSR,* X:SRXL,A2 #1,X:SSR,* A2,X:STXL #8 A MOVEM A1,P:(R0)+ _LOOP6 ; starting address for load ; save starting address ; Receive program words ; Wait for RDRF to go high ; Put 8 bits in A2 ; Wait for TDRE to go high ; echo the received byte _LOOP5 ; Store 24-bit result in P mem. _LOOP4 Figure A-1 DSP56002 Bootstrap Program (Sheet 2 of 3) MOTOROLA BOOTSTRAP AND ROM CODE For More Information On This Product, Go to: www.freescale.com A-5 Freescale Semiconductor, Inc. INTRODUCTION ; This is the exit handler that returns execution to normal ; expanded mode and jumps to the RESET vector. BOOTEND ANDI #$EC,OMR ANDI #$0,CCR JMP (R1) ; Set operating mode to 0 ; (and trigger an exit from ; bootstrap mode). ; Clear CCR as if RESET to 0. ; Delay needed for Op. Mode change ; Then go to starting Prog addr. Freescale Semiconductor, Inc... ; End of bootstrap code. Number of program words: 64 Figure A-1 DSP56002 Bootstrap Program (Sheet 3 of 3) A-6 BOOTSTRAP AND ROM CODE For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. APPENDIX B Freescale Semiconductor, Inc... PROGRAMMING SHEETS The following pages are a set of programming sheets intended to simplify programming the various DSP56002 programmable registers. The registers are grouped between the central processing module and each peripheral. Each register includes the name, address, reset value, and meaning of each bit. The sheets provide room to write the value for each bit and the hexadecimal equivalent for each register. MOTOROLA For More Information On This Product, Go to: www.freescale.com B-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SECTION CONTENTS B.1 PERIPHERAL ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2 INTERRUPT VECTOR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B.3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.4 CENTRAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 B.5 GP I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.6 HOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16 B.7 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21 B.8 SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24 B.9 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27 B-2 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PERIPHERAL ADDRESSES Freescale Semiconductor, Inc... 23 16 15 8 7 0 X:$FFFF INTERRUPT PRIORITY REGISTER (IPR) X:$FFFE PORT A — BUS CONTROL REGISTER (BCR) X:$FFFD PLL CONTROL REGISTER X:$FFFC OnCE GDB REGISTER X:$FFFB RESERVED X:$FFFA RESERVED X:$FFF9 RESERVED X:$FFF8 RESERVED X:$FFF7 RESERVED X:$FFF6 SCI HI - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF5 SCI MID - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF4 SCI LOW - REC/XMIT DATA REGISTER (SRX/STX) X:$FFF3 SCI TRANSMIT DATA ADDRESS REGISTER (STXA) X:$FFF2 SCI CONTROL REGISTER (SCCR) X:$FFF1 SCI INTERFACE STATUS REGISTER (SSR) X:$FFF0 SCI INTERFACE CONTROL REGISTER (SCR) X:$FFEF SSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX) X:$FFEE SSI STATUS/TIME SLOT REGISTER (SSISR/TSR) X:$FFED SSI CONTROL REGISTER B (CRB) X:$FFEC SSI CONTROL REGISTER A (CRA) X:$FFEB HOST RECEIVE/TRANSMIT REGISTER (HRX/HTX) X:$FFEA RESERVED X:$FFE9 HOST STATUS REGISTER (HSR) X:$FFE8 HOST CONTROL REGISTER (HCR) X:$FFE7 RESERVED X:$FFE6 RESERVED X:$FFE5 PORT C — DATA REGISTER (PCD) X:$FFE4 PORT B — DATA REGISTER (PBD) X:$FFE3 PORT C — DATA DIRECTION REGISTER (PCDDR) X:$FFE2 PORT B — DATA DIRECTION REGISTER (PBDDR) X:$FFE1 PORT C — CONTROL REGISTER (PCC) X:$FFE0 PORT B — CONTROL REGISTER (PBC) X:$FFDF TIMER COUNT REGISTER (TCR) X:$FFDE TIMER CONTROL/STATUS REGISTER (TCSR) = Read as random number; write as don’t care. X:$FFC0 RESERVED Figure B-1 On-chip Peripheral Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com B-3 Freescale Semiconductor, Inc. INTERRUPT VECTOR ADDRESSES Table B-1 Interrupts Starting Addresses and Sources Interrupt Starting Address IPL Interrupt Source Freescale Semiconductor, Inc... $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 3 3 3 3 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 3 0-2 0-2 0-2 0-2 • • • $003A $003C $003E $0040 • • • $007E B-4 Hardware RESET Stack Error Trace SWI IRQA IRQB SSI Receive Data SSI Receive Data with Exception Status SSI Transmit Data SSI Transmit Data with Exception Status SCI Receive Data SCI Receive Data with Exception Status SCI Transmit Data SCI Idle Line SCI Timer NMI Host Receive Data Host Transmit Data Host Command (default) Available for Host Command • • • 0-2 0-2 3 0-2 Available for Host Command Timer Illegal Instruction Available for Host Command • • • 0-2 Available for Host Command For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INSTRUCTIONS Table B-2 Freescale Semiconductor, Inc... Mnemonic Syntax ABS ADC ADD ADDL ADDR AND AND(I) ASL ASR BCHG BCLR BSET BTST CLR CMP CMPM DEBUG DEBUGcc DEC DIV MOTOROLA Parallel Moves D S,D S,D S,D S,D S,D #xx,D D D #n,X:<aa> #n,X:<pp> #n,X:<ea> #n,Y:<aa> #n,Y:<pp> #n,Y:<ea> #n,D #n,X:<aa> #n,X:<pp> #n,X:<ea> #n,Y:<aa> #n,Y:<pp> #n,Y:<ea> #n,D #n,X:<aa> #n,X:<pp> #n,X:<ea> #n,Y:<aa> #n,Y:<pp> #n,Y:<ea> #n,D #n,X:<aa> #n,X:<pp> #n,X:<ea> #n,Y:<aa> #n,Y:<pp> #n,Y:<ea> #n,D D S1,S2 S1,S2 D S,D Instruction Set Summary — Sheet 1 of 5 Instruction Osc. Program Clock Words Cycles S LE UNZVC (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv . . . . . . . . . . . . . . . . . . . 1+ea 2+mv 2+mv 2+mv 2+mv 2+mv 2+mv 2 2+mv 2+mv 4+mvb * * * * * * ** * * * * * ** * * * * * * ** * * * * * * ?* * * * * * * ** * * - - ? ? 0? ? ? ? ? ? ?? * * * * * * ?? * * * * * * 0? ? ? ? ? ? ? ?? . . . . . . . . . . . . . . . . . . . 1+ea 4+mvb ? ? ? ? ? ? ?? . . . . . . . . . . . . . . . . . . . 1+ea 4+mvb ? ? ? ? ? ? ?? . . . . . . . . . . . . . . . . . . . 1+ea 4+mvb - *- - - - -? (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 .................... 1 .................... 1 .................... 1 2+mv 2+mv 2+mv 4 4 2 2 * * * - For More Information On This Product, Go to: www.freescale.com * ? ? ? ? ?* * * * * ** * * * * * ** -- - - - --- - - - -* * * * * ** * - - - - ?? B-5 Freescale Semiconductor, Inc. INSTRUCTIONS Table B-2 Mnemonic Syntax Freescale Semiconductor, Inc... DO ENDDO EOR ILLEGAL INC Jcc JCLR JMP JScc JSCLR JSET JSR JSSET LSL LSR LUA MAC B-6 Instruction Set Summary — Sheet 2 of 5 Parallel Moves X:<ea>,expr X:<aa>,expr Y:<ea>,expr Y:<aa>,expr #xxx,expr S,expr Instruction Osc. Program Clock Words Cycles .................... 2 .................... 1 (parallel move) . . . . . . .1+mv .................... 1 D .................... 1 xxx . . . . . . . . . . . . . . . . . . . 1+ea #n,X:<ea>,xxxx . . . . . . . . . . . . . . . . . . . . 2 #n,X:<aa>,xxxx #n,X:<pp>,xxxx #n,Y:<ea>,xxxx #n,Y:<aa>,xxxx #n,Y:<pp>,xxxx #n,S,xxxx xxxx . . . . . . . . . . . . . . . . . . . 1+ea ea xxxx . . . . . . . . . . . . . . . . . . . 1+ea ea #n,X:<ea>,xxxx . . . . . . . . . . . . . . . . . . . . 2 #n,X:<aa>,xxxx #n,X:<pp>,xxxx #n,Y:<ea>,xxxx #n,Y:<aa>,xxxx #n,Y:<pp>,xxxx #n,S,xxxx #n,X:<ea>,xxxx . . . . . . . . . . . . . . . . . . . . 2 #n,X:<aa>,xxxx #n,X:<pp>,xxxx #n,Y:<ea>,xxxx #n,Y:<aa>,xxxx #n,Y:<pp>,xxxx #n,S,xxxx xxx . . . . . . . . . . . . . . . . . . . 1+ea ea #n,X:<ea>,xxxx . . . . . . . . . . . . . . . . . . . . 2 #n,X:<aa>,xxxx #n,X:<pp>,xxxx #n,Y:<ea>,xxxx #n,Y:<aa>,xxxx #n,Y:<pp>,xxxx #n,S,xxxx D (parallel move) . . . . . . .1+mv D (parallel move) . . . . . . .1+mv <ea>,D .................... 1 (parallel move) . . . . . . .1+mv (+)S2,S1,D (+)S1,S2,D (parallel move) (+)S,#n,D (no parallel move). . . . . . 1 S,D S LE UNZVC 6+mv **- - - - -- 2 2+mv 8 2 4+jx 6+jx * * -*-** -*- * - - - -? ? 0- - -* * ** - - -- - -- 4+jx - -- - - - -- 4+jx - -- - - - -- 6+jx **- - - - -- 6+jx **- - - - -- 4+jx - -- - - - -- 6+jx **- - - - -- 2+mv 2+mv 4 2+mv * * * *- * --- ** * ? ? 0? ? ? 0? - - -* * *- 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INSTRUCTIONS Table B-2 Mnemonic Syntax Freescale Semiconductor, Inc... MACR Instruction Set Summary — Sheet 3 of 5 Parallel Moves (+)S2,S1,D (+)S1,S2,D (+)S,#n,D MOVE S,D No parallel data move Immediate short data move Register to register data move Address register update X memory data move Instruction Osc. Program Clock Words Cycles (parallel move) . . . . . . . . .1+mv 2+mv (parallel move) (no parallel move). . . . . . . . 1 2 . . . . . . . . . . . . . . . . . . . . .1+mv 2+mv (.....) . . . . . . . . . . . . . . . . . . . . . mv mv (.....)#xx,D . . . . . . . . . . . . . . . . . mv mv * * * * * * *- (.....)S,D . . . . . . . . . . . . . . . . . . mv **- - - - -- mv (.....)ea . . . . . . . . . . . . . . . . . . . mv mv (.....)X:<ea>,D . . . . . . . . . . . . . . mv mv (.....)X:<aa>,D (.....)S,X:<ea> (.....)S,X:<aa> (.....)#xxxxxx,D X memory and register (.....)X:<ea>,D1 S2,D2 . . . . . mv mv data move (.....)S1,X:<ea> S2,D2 (.....)#xxxxxx,D1 S2,D2 (.....)A,X:<ea> X0,A (.....)B,X:<ea> X0,B Y memory data move (.....)Y:<ea>,D . . . . . . . . . . mv mv (.....)Y:<aa>,D (.....)S,Y:<ea> (.....)S,Y:<aa> (.....)#xxxxxx,D Register and Y memory (.....)S1,D1 Y:<ea>,D2 . mv mv data move (.....)S1,D1 S2,Y:<ea> (.....)S1,D1 #xxxxxx,D2 (.....)Y0,A A,Y:<ea> (.....)Y0,B B,Y:<ea> Long memory data move (.....)L:<ea>,D . . . . . . . . . . mv mv (.....)L:<aa>,D (.....)S,L:<ea> (.....)S,L:<aa> XY memory data move (.....)X:<eax>,D1 Y:<eay>,D2 . mv mv (.....)X:<eax>,D1 S2,Y:<eay> (.....)S1,X:<eax> Y:<eay>,D2 (.....)S1,X:<eax> S2,Y:<eay> MOVE(C) X:<ea>,D1 . . . . . . . . . . . . . . . . . . . . . 1+ea 2+mvc X:<aa>,D1 S1,X:<ea> S1,X:<aa> Y:<ea>,D1 Y:<aa>,D1 S1,Y:<ea> S1,Y:<aa> S1,D2 S2,D1 #xxxx,D1 #xx,D1 MOTOROLA S LE UNZVC For More Information On This Product, Go to: www.freescale.com **- - - - -- -- - - - -- -- - - - -- - -- - - - -**- - - - -- **- - - - -- **- - - - -- **- - - - -- **- - - - -- **- - - - -- ? ? ? ? ? ? ?? B-7 Freescale Semiconductor, Inc. INSTRUCTIONS Table B-2 Instruction Set Summary — Sheet 4 of 5 Mnemonic Syntax MOVE(M) Freescale Semiconductor, Inc... MOVE(P) MPY MPYR NEG NOP NORM NOT OR ORI REP B-8 Parallel Moves P:<ea>,D S,P:<ea> S,P:<aa> P:<aa>,D X:<pp>,D X:<pp>,X:<ea> X:<pp>,Y:<ea> X:<pp>,P:<ea> S,X:<pp> #xxxxxx,X:<pp> X:<ea>,X:<pp> Y:<ea>,X:<pp> P:<ea>,X:<pp> Y:<pp>,D Y:<pp>,X:<ea> Y:<pp>,Y:<ea> Y:<pp>,P:<ea> S,Y:<pp> #xxxxxx,Y:<pp> X:<ea>,Y:<pp> Y:<ea>,Y:<pp> P:<ea>,Y:<pp> (+)S2,S1,D (+)S1,S2,D (+)S,#n,D (+)S2,S1,D (+)S1,S2,D (+)S,#n,D D Rn,D D S,D #xx,D X:<ea> X:<aa> Y:<ea> Y:<aa> S #xxx Instruction Osc. Program Clock Words Cycles S LE UNZVC . . . . . . . . . . . . . . . . . . . 1+ea 2+mvm ? ? ? ? ? ? ?? . . . . . . . . . . . . . . . . . . . 1+ea 2+mvp ? ? ? ? ? ? ?? (parallel move) . . . . . . .1+mv (parallel move) (no parallel move). . . . . . 1 (parallel move) . . . . . . .1+mv (parallel move) (no parallel move). . . . . . 1 (parallel move) . . . . . . .1+mv .................... 1 .................... 1 (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 .................... 1 2+mv * * * * * * *- 2 2+mv * * * * * * *- 2 2+mv 2 2 2+mv 2+mv 2 4+mv * * * * * * *- -- - - - -- * * * * * ?* * - - ? ? 0* * - - ? ? 0? ? ? ? ? ? ?? ? ?- - - - - - For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. INSTRUCTIONS Table B-2 Freescale Semiconductor, Inc... Mnemonic Syntax RESET RND ROL ROR RTI RTS SBC STOP SUB SUBL SUBR SWI Tcc TFR TST WAIT Instruction Set Summary — Sheet 5 of 5 Parallel Moves D D D S,D S,D S,D S,D S1,D1 S1,D1 S2,D2 S,D S Instruction Osc. Program Clock Words Cycles S LE UNZVC .................... 1 (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 .................... 1 (parallel move) . . . . . . .1+mv .................... 1 (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 .................... 1 4 2+mv 2+mv 2+mv 4+rx 4+rx 2+mv n/a 2+mv 2+mv 2+mv 8 2 - -- - - - -* * * * * * ** * - - ? ? 0? * * - - ? ? 0? ? ? ? ? ? ? ?? - -- - - - -* * * * * * ** - -- - - - -* * * * * * ** * * * * * * ?* * * * * * * ** - -- - - - -- -- - - - -- (parallel move) . . . . . . .1+mv (parallel move) . . . . . . .1+mv .................... 1 2+mv 2+mv n/a **- - - - -* * * * * * 0- -- - - - -- NOTATION: - denotes the bit is unaffected by the operation. * denotes the bit may be set according to the definition, depending on parallel move conditions. ? denotes the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD). 0 denotes the bit is cleared. MOTOROLA For More Information On This Product, Go to: www.freescale.com B-9 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 1 of 3 Freescale Semiconductor, Inc... CENTRAL PROCESSOR Carry Overflow Zero Negative Unnormalized Extension Limit FFT Scaling Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag 15 14 13 12 11 10 9 Status Register (SR) Read/Write Reset = $0300 LF DM T *0 S1 S0 I1 Mode Register (MR) 8 7 6 5 4 3 2 1 0 I0 S L E U N Z V C Condition Code Register (CCR) = Reserved, Program as zero * Figure B-2 Status Register (SR) Port A Bus Control Register (BCR) X:$FFFE Read/Write 15 14 13 12 11 10 9 EXTERNAL X MEMORY EXTERNAL Y MEMORY 8 7 6 5 EXTERNAL P MEMORY 4 3 2 1 0 EXTERNAL I/0 MEMORY Figure B-3 Bus Control Register (BCR) B - 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA CENTRAL PROCESSOR IAL2 Trigger 0 Level 1 Neg. Edge IAL0 0 1 0 1 IRQA Mode IAL1 0 0 1 1 7 IBL0 0 1 0 1 IRQB Mode 8 IBL1 0 0 1 1 9 Enabled No Yes Yes Yes IPL — 0 1 2 3 IPL — 0 1 2 4 2 1 0 Date: IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 5 Enabled No Yes Yes Yes 6 Application: IBL2 Trigger 0 Level 1 Neg. Edge SCL1 SCL0 SSL1 SSL0 HPL1 HPL0 *0 *0 *0 *0 Programmer: * = Reserved, Program as zero For More Information On This Product, Go to: www.freescale.com Host IPL HPL1 HPL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SSI IPL SSL1 SSL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCI IPL ******** 0 0 0 0 0 0 0 0 $0 $0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SCL1 SCL0 Enabled IPL 0 0 No — 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 Interrupt Priority Register (IPR) X:$FFFF Read/Write Reset = $000000 MOTOROLA Figure B-4 Interrupt Priority Register (IPR) Sheet 2 of 3 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. B - 11 Mode MMM CBA 000 001 010 011 100 101 110 111 Operating Mode SD 6 5 MC 4 YD 3 DE MB 2 MA 0 1 Single-Chip Mode Bootstrap from EPROM Normal Expanded Mode Development Mode Reserved Bootstrap from Host Bootstrap from SCI (external clock) Reserved for Bootstrap 7 *0 For More Information On This Product, Go to: www.freescale.com Application: 0 1 2 3 4 5 6 7 Stop Delay 0 = 128K T Stabilization 1 = 16 T Stabilization 8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $0 $0 $0 $0 ************ ***** 0 = Y Memory controlled by DE bit 1 = All Y Memory external Internal Y Memory Disable 0 = Disable ROMs 1 = Enable ROMs Data ROM Enable CENTRAL PROCESSOR Operating Mode Register (OMR) Read/Write Reset = $000000 B - 12 Programmer: Date: * = Bit 5 and bits 7 through 23 are reserved. Program as zero Figure B-5 Operating Mode Register (OMR) Sheet 3 of 3 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA CENTRAL PROCESSOR XTAL Disable Bit (XTLD) 0 = Enable XTAL 1 = Disable XTAL DF0 Multiplication Factor Bits MF0 - MF11 MF11 - MF0 Multiplication Factor MF $000 1 $001 2 $002 3 . . . . . . $FFE 4095 $FFF 4096 MF8 8 MF7 7 MF6 6 MF5 5 MF4 4 MF3 3 MF2 2 MF1 1 MF0 0 Division Factor Bits DF0 - DF3 DF3 - DF0 Division Factor DF $0 20 $1 21 $2 22 . . . . . . $E 214 $F 215 9 MF11 MF10 MF9 Date: DF1 Application: DF2 Programmer: CKOS CSRC COD1 COD0 PEN PSTP XTLD DF3 MOTOROLA * = Reserved, Program as zero For More Information On This Product, Go to: www.freescale.com STOP Processing State Bit (PSTP) 0 = PLL Disabled During STOP Processing State 1 = PLL Enabled During STOP Processing State PLL Enable Bit (PEN) 0 = Disable PLL 1 = Enable PLL Clock Output Disable Bits COD0 - COD1 COD1 COD0 CLKOUT Pin 0 0 Clock Out Enabled, Full Strength Output Buffer 0 1 Clock Out Enabled, 2/3 Strength Output Buffer 1 0 Clock Out Enabled, 1/3 Strength Output Buffer 1 1 Clock Out Disabled Chip Clock Source Bit (CSRC) 0 = Output from Low Power Divider 1 = Output from VCO *0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CKOUT Clock Source Bit (CKOS) 0 = Output from LPD 1 = Output from VCO PLL Control Register (PCTL) X:$FFFD Read/Write Reset = $0X0000 Figure B-6 PLL Control Register (PCTL) Sheet 1 of 1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. B - 13 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 1 of 2 Port B GP I/O Freescale Semiconductor, Inc... PBC1 PBC0 Function 0 0 General Purpose I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK pin as GPIO) 1 1 Reserved 23 Port B Control Register (PBC) X:$FFE0 Read/Write Reset = $000000 •• • 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 $0 0 PBC1 PBC0 $0 $0 = Reserved, Program as zero * Figure B-7 Port B Control Register (PBC) Port B Data Direction Control 0 = Input 1 = Output Port B Data Direction Register (PBDDR) X:$FFE2 Read/Write Reset = $000000 23 • • • 15 *0 *0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 = Reserved, Program as zero * Figure B-8 Port B Data Direction Register (PBDDR) Port B Data (usually loaded by program) 23 Port B Data Register (PBD) X:$FFE4 Read/Write Reset = $000000 *0 •• • 15 14 13 12 11 10 *0 9 PB14 PB13 PB12 PB11 PB10 PB9 8 PB8 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 = Reserved, Program as zero * Figure B-9 Port B Data Register (PBD) B - 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 2 of 2 GP I/O Port C Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin Freescale Semiconductor, Inc... 23 Port C Control Register (PCC) X:$FFE1 Read/Write Reset = $000000 •• • 15 14 13 12 11 10 9 *0 *0 *0 *0 *0 *0 *0 *0 8 7 6 5 4 3 2 1 0 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 $0 * = Reserved, Program as zero SSI STD SRD SCK SC2 SC1 SC0 SCI SCLK TXD RXD Figure B-10 Port C Control Register (PCC) Port C Data Direction Control 0 = Input 1 = Output Port C Data Direction Register (PCDDR) X:$FFE3 Read/Write Reset = $000000 23 •• • 15 14 13 12 11 10 9 *0 *0 *0 *0 *0 *0 *0 *0 8 7 6 5 4 3 2 1 0 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 $0 = Reserved, Program as zero * Figure B-11 Port C Data Direction Register (PCDDR) Port C Data (usually loaded by program) 23 Port C Data Register (PCD) X:$FFE5 Read/Write Reset = $000000 *0 •• • 15 14 13 12 11 10 9 *0 *0 *0 *0 *0 *0 *0 8 7 6 5 4 3 2 1 0 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 $0 * = Reserved, Program as zero Figure B-12 Port C Data Register (PCD) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 15 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 1 of 5 HOST Freescale Semiconductor, Inc... Port B PBC1 PBC0 Function 0 0 General Purpose I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK pin as GPIO) 1 1 Reserved Port B Control Register (PBC) X:$FFE0 Read/Write Reset = $000000 23 *0 • • • 15 14 13 12 11 10 9 8 7 6 5 4 3 2 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 $0 $0 1 0 PBC1 PBC0 $0 = Reserved, Program as zero * Figure B-13 Port B Control Register (PBC) DSP SIDE Host Receive Interrupt Enable 0 = ∏ Disable1 = ∏ Enable — Interrupt on HRDF Host Transmit Interrupt Enable 0 = ∏ Disable1 = ∏ Enable — Interrupt on HTDE Host Command Interrupt Enable 0 = ∏ Disable1 = ∏ Enable — Interrupt on HCP Host Flags General Purpose Read/Write Flags 23 Host Control Register (HCR) X:$FFE8 Read/Write Reset = $00 *0 •• • 7 6 5 *0 *0 *0 4 3 2 1 0 HF3 HF2 HCIE HTIE HRIE = Reserved, Program as zero * Figure B-14 Host Control Register (HCR) B - 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 2 of 5 HOST DSP SIDE Host Receive Data Full 0 = ∏ Wait 1 = ∏ Read Freescale Semiconductor, Inc... Host Transmit Data Empty 0 = ∏ Wait 1 = ∏ Write Host Command Pending 0 = ∏ Wait 1 = ∏ Ready Host Flags Read Only DMA Status (Read Only) 0 = ∏ Disabled 1 = ∏ Enabled •• • 23 Host Status Register (HSR) X:$FFE9 Read Only Reset = $000002 7 DMA *0 6 5 *0 *0 4 HF1 3 2 1 0 HF0 HCP HTDE HRDF = Reserved, Program as zero * Figure B-15 Host Status Register (HSR) Host Receive Data Register (HRX) X:$FFEB Read Only Reset = $000000 23 22 21 20 19 18 Host Receive Data (usually Read by program) 17 16 15 14 13 12 11 10 RECEIVE HIGH BYTE 9 8 7 6 5 RECEIVE MIDDLE BYTE 4 3 2 1 0 RECEIVE LOW BYTE Figure B-16 Host Receive Data Register (HRX) Host Transmit Data Register (HTX) X:$FFEB Write Only Reset = $000000 23 22 21 20 19 18 TRANSMIT HIGH BYTE Host Transmit Data (usually loaded by program) 17 16 15 14 13 12 11 10 9 8 7 TRANSMIT MIDDLE BYTE 6 5 4 3 2 1 0 TRANSMIT LOW BYTE Figure B-17 Host Transmit Data Register (HTX) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 17 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 3 of 5 HOST Freescale Semiconductor, Inc... PROCESSOR SIDE Receive Request Enable DMA Off 0 = ∏ Interrupts Disabled DMA On 0 = Host → DSP 1 = Interrupts Enabled 1 = DSP → Host Transmit Request Enable DMA Off 0 = ∏ Interrupts Disabled DMA On 0 = DSP → Host 1 = Interrupts Enabled 1 = Host → DSP Host Flags Write Only Host Mode Control 00 = DMA Off 01 = 24 Bit DMA 10 = 16 Bit DMA 11 = 8 Bit DMA Initialize (Write Only) 0 = ∏ No Action 1 = ∏ Initialize DMA 7 INIT Interrupt Control Register (ICR) $0 Read/Write Reset = $00 6 5 HM1 HM0 4 3 HF1 HF0 2 *0 1 0 TREQ RREQ = Reserved, Program as zero * Figure B-18 Interrupt Control Register (ICR) Host Vector Executive Interrupt Routine 0-63 Host Command 0 = ∏ Idle 1 = ∏ Interrupt DSP 7 Command Vector Register (CVR) $1 Read/Write Reset = $12 HC 6 *0 5 4 3 2 1 0 HV5 HV4 HV3 HV2 HV1 HV0 = Reserved, Program as zero * Figure B-19 Command Vector Register (CVR) B - 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 4 of 5 HOST Freescale Semiconductor, Inc... PROCESSOR SIDE Receive Data Register Full 0 = Wait 1 = Read Transmit Data Register Empty 0 = Wait 1 = Write Transmitter Ready 0 = Data in HI 1 = Data Not in HI Host Flags Read Only DMA Status 0 = ∏ DMA Disabled 1 = ∏ DMA Enabled Host Request 0 = ∏ HREQ Deasserted1 = ∏ HREQ Asserted 7 Interrupt Status Register (ISR) $2 Read/Write Reset = $06 6 HREQ DMA 5 4 *0 HF3 3 2 1 0 HF2 TRDY TXDE RXDF = Reserved, Program as zero * Figure B-20 Interrupt Status Register (ISR) Exception vector number for use by MC68000 processor family vectored interrupts. Interrupt Vector Register (IVR) $3 Read/Write Reset = $0F 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 Figure B-21 Interrupt Vector Register (IVR) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 19 0 0 7 7 PROCESSOR SIDE 0 7 $5 RECEIVE HIGH BYTE Host Receive Data (usually read by program) RECEIVE MIDDLE BYTE $6 Figure B-22 Receive Byte Registers 7 TRANSMIT HIGH BYTE 0 0 7 0 7 0 0 0 0 0 0 NOT USED 0 $4 0 NOT USED 0 $4 0 0 0 0 0 0 0 0 Date: $5 Application: 0 Host Transmit Data (usually loaded by program) TRANSMIT MIDDLE BYTE $6 For More Information On This Product, Go to: www.freescale.com HOST RECEIVE LOW BYTE Receive Byte Registers $7, $6, $5, $4 Read Only Reset = $00 7 $7 TRANSMIT LOW BYTE Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = $00 7 $7 B - 20 Programmer: Figure B-23 Transmit Byte Registers Sheet 5 of 5 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 1 of 3 SCI Port C Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin Freescale Semiconductor, Inc... 23 Port C Control Register (PCC) X:$FFE1 Read/Write Reset = $000000 •• • 15 14 13 12 11 10 9 *0 *0 *0 *0 *0 *0 *0 *0 8 7 6 5 4 3 2 1 0 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 $0 = Reserved, Program as zero * Figure B-24 Port C Control Register (PCC) Word Select Bits 0 0 0 = 8-bit Synchronous Data (Shift Register Mode) 0 0 1 = Reserved 0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) 0 1 1 = Reserved 1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop) 1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop) 1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Even Parity, 1 Stop) 1 1 1 = Reserved Transmitter Enable 0=Transmitter disabled 1=Transmitter enabled Idle Line Interrupt Enable 0=Idle Line Interrupts disabled 1=Idle Line Interrupts enabled Receive Interrupt Enable Receiver Wakeup Enable Send Break SCI Shift Direction 0=Receive Interrupts disabled 1=Receive Interrupts enabled 0=Receiver has awakened 1=Wakeup function enabled 0=Send break, then revert 1=Continually send breaks 0 = LSB First 1 = MSB First Transmit Interrupt Enable Wakeup Mode Select 0=Transmit Interrupts disabled 1=Transmit Interrupts enabled 0=Idle Line Wakeup 1=Address Bit Wakeup Timer Interrupt Enable Wired-Or Mode Select 0=Timer Interrupts disabled 1=Timer Interrupts enabled 1=Multidrop 0=Point to Point SCI Timer Interrupt Rate Receiver Enable 0= ÷ 32, 1= ÷ 1 0=Receiver Disabled 1=Receiver Enabled SCI Clock Polarity 0=Clock Polarity is positive 1=Clock Polarity is negative 23 SCI Control Register (SCR) Address X:$FFF0 Read/Write *0 •• • 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE TE RE WOMS RWU WAKE SBK RIE ILIE 7 6 5 4 3 2 1 0 SSFTD WDS2WDS1 WDS0 = Reserved, Program as zero * Figure B-25 SCI Control Register (SCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 21 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 2 of 3 Freescale Semiconductor, Inc... SCI Overrun Error Flag Idle Line Flag 0=No error 1=Overrun detected 0=Idle not detected 1=Idle State Parity Error Flag Receive Data Register Full 0=No error 1=Incorrect Parity detected 0=Receive Data Register full 1=Receive Data Register empty Framing Error Flag Transmitter Data Register Empty 0=No error 1=No Stop Bit detected 0=Transmitter Data Register full 1=Transmitter Data Register empty Received Bit 8 Transmitter Empty 0=Data 1=Address 0=Transmitter full 1=Transmitter empty SCI Status Register (SSR) Address X:$FFF1 Read Only Reset = $000003 23 •• • *0 7 6 5 4 R8 FE PE OR IDLE RDRF TDRE TRNE 3 2 1 0 * = Reserved, Program as zero Figure B-26 SCI Status Register (SSR) Clock Divider Bits CD11-CD0 CD11 - CD0 lcyc Rate Transmit/Receive Clock Selection TCM RCM TX Clock RX Clock 0 0 1 1 SCLK Pin Mode 0 Internal Internal Output Synchronous/Asynchronous 1 Internal External Input Asynchronous Only 0 External Internal Input Asynchronous Only 1 External External Input Synchronous/Asynchronous Transmitter Clock Mode/Source Receiver Clock Mode/Source 0=Internal clock for transmitter 1=External clock from SCLK 0=Internal clock for receiver 1=External clock from SCLK $000 $001 $002 . . . $FFE $FFF lcyc/1 lcyc/2 lcyc/3 . . . lcyc/4095 lcyc/4096 Clock Out Divider 0=Divide clock by 16 before feed to SCLK 1=Feed clock to directly to SCLK SCI Clock Prescaler 0= SCI Clock Control Register (SCCR) Address X:$FFF2 Read/Write Reset = $000000 23 *0 •• • ÷1 1= ÷8 15 14 13 12 11 10 9 TCM RCM SCP COD CD11 CD10 CD9 8 7 6 5 4 3 2 1 0 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 = Reserved, Program as zero * Figure B-27 SCI Clock Control Register (SCCR) B - 22 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 3 of 3 SCI “A” X0 “B” “C” UNPACKING Freescale Semiconductor, Inc... 23 SCI Transmit Data Registers Address X:$FFF4 – X:$FFF6 Read/Write Reset = xxxxxx X:$FFF6 16 15 8 7 0 STX X:$FFF5 STX X:$FFF4 STX NOTE: STX is the same register decoded at three different addresses. SCI Transmit SR TXD Figure B-28 SCI Transmit Data Registers SCI Receive SR 23 SCI Receive Data Registers Address X:$FFF4 - X:$FFF6 Read/Write Reset = xxxxxx X:$FFF6 16 15 RXD 8 7 0 SRX X:$FFF5 SRX X:$FFF4 SRX NOTE: SRX is the same register decoded at three different addresses. PACKING X0 “A” “B” “C” Figure B-29 SCI Receive Data Registers MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 23 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 1 of 3 SSI Freescale Semiconductor, Inc... Port C Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin 23 Port C Control Register (PCC) X:$FFE1 Read/Write Reset = $0000 •• • 15 14 13 12 11 10 9 *0 *0 *0 *0 *0 *0 *0 *0 8 7 6 5 4 3 2 1 0 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 0 * = Reserved, Program as zero Figure B-30 SSI Control Register (PCC) Word Length Control 00 = 8 Bits/Word 01 = 12 Bits/Word 10 = 16 Bits/Word 11 = 24 Bits/Word Prescaler Range 0=/1 1=/8 SSI Control Register A (CRA) X:$FFEC Read/Write Reset = $000000 23 *0 •• • Frame Rate Divider Control 00000 = 1 11111 = 32 15 14 13 12 11 10 PSR WL1 WL0 DC4 9 8 Prescale Modulus Select 7 6 5 4 3 2 1 0 DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 = Reserved, Program as zero * Figure B-31 SSI Control Register A (CRA) B - 24 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 2 of 3 SSI Freescale Semiconductor, Inc... Serial Control Direction Bits SCDx=0 SCDx=1 (Output) (Input) SC0 Pin SC1 Pin SC2 Pin Rx Clk Rx Frame Sync Tx Frame Sync Flag 0 Flag 1 Tx, Rx Frame Sync Clock Source Direction 0 = External Clock 1 = Internal Clock Shift Direction 0 = MSB First 1 = ∏LSB First Frame Sync Length 0 0 = Rx and Tx Same Length 1 = Rx and Tx Different Length Frame Sync Length 1 0 = ∏ Rx is Word Length1 = ∏ Rx is Bit Length Sync/Async Control 0 = ∏ Asynchronous 1 = ∏ Synchronous Gated Clock Control 0 = ∏ Continuous Clock1 = Gated Clock SSI Mode Select 0 = ∏ Normal 1 = Network Transmit Enable 0 = ∏ Disable 1 = Enable Output Flag x If SYN = 1 and SCD1=1 OFx SCx Pin Receive Enable 0 = ∏ Disable 1 = Enable Transmit Interrupt Enable 0 = ∏ Disable 1 = Enable Receive Interrupt Enable 0 = ∏ Disable 1 = Enable SSI Control Register B (CRB) X:$FFED Read/Write Reset = $000000 23 *0 •• • 15 14 13 12 11 10 RIE TIE RE TE 9 8 7 6 5 4 3 2 1 0 MOD GCK SYN FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0 * = Reserved, Program as zero Figure B-32 SSI Control Register B (CRB) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 25 Freescale Semiconductor, Inc. Date: Application: Programmer: Sheet 3 of 3 SSI Freescale Semiconductor, Inc... Serial Input Flag 0 If SCD0=0 and SYN=1 latch SC0 on FS Serial Input Flag 1 If SCD1=0 and SYN=1 latch SC0 on FS Transmit Frame Sync 0 = ∏ Sync Inactive1 = ∏ Sync Active Receive Frame Sync 0 = ∏ Wait 1 = ∏ Frame Sync Occurred Transmitter Underrun Error Flag 0 = ∏ OK 1 = ∏ Error Receiver Overrun Error Flag 0 = ∏ OK 1 = ∏ Error Transmit Data Register Empty 0 = ∏ Wait 1 = ∏ Write Receive Data Register Full 0 = ∏ Wait 1 = ∏ Read 23 SSI Status Register (SSISR) X:$FFEE (Read) Reset = $000040 *0 •• • 7 6 5 4 3 2 RDF TDE ROE TUE RFS TFS 1 IF1 0 IF0 SSI Status Bits * = Reserved, Program as zero Figure B-33 SSI Status Register (SSISR) B - 26 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Date: Application: Sheet 1 of 1 Freescale Semiconductor, Inc... TIMER Note: The first version of the DSP56002 (mask number D41G) did not have the timer/ event counter. Later versions of the DSP56002 which have different mask numbers do have the timer/event counter. This mask number can be found below the part number on each chip. Timer Control Bits 3-5 (TC0 - TC2) TC2 TC1 TC0 TIO 0 0 0 GPIO 0 0 1 Output 0 1 0 Output 0 1 1 X 1 0 0 Input 1 0 1 Input 1 1 0 Input 1 1 1 Input Clock Internal Internal Internal X Internal Internal External External Mode Timer Timer Pulse Timer Toggle Undefined Input Width Input Period Standard Time Counter Event Counter Timer Status Bit 7 0 = TCSR read, or timer interrupt serviced 1 = Counter decremented to 0 Direction Bit 8 0 = TIO pin is input 1 = TIO pin is output Data Output Bit 10 0 =Zero written to TIO pin 1 = One written to TIO pin 23 Timer Control and Status Register (TCSR) X:$FFDE (Read/Write) Reset = $000200 Timer Enable Bit 0 0 = Timer Disabled 1 = Timer Enabled Inverter Bit 2 0 = 0- to-1 transitions on TIO input decrement the counter 1 = 1-to-0 transitions on TIO input decrement the counter or Timer pulse inverted before it goes to TIO output GPIO Bit 6 0 = TIO is Timer IO 1 = TIO is GPIO if TC2-TC0 are clear Data Input Bit 9 0 = Zero read on TIO pin 1 = One read on TIO pin Timer Interrupt Enable Bit 1 0 = Interrupts Disabled 1 = Interrupts Enabled •• • *0 15 14 13 12 11 10 *0 *0 *0 *0 *0 DO 9 DI 8 DIR 7 TS 6 5 4 3 2 1 0 GPIO TC2 TC1 TC0 INV TIE TE * = Reserved, Program as zero Figure B-34 Timer Control and Status Register (TCSR) 23 Timer Count Register (TCR) X:$FFDF (Read/Write) Unaffected by Reset •• • 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 *0 * = Reserved, Program as zero Figure B-35 Timer Count Register (TCR) MOTOROLA For More Information On This Product, Go to: www.freescale.com B - 27 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... INDEX MOTOROLA For More Information On This Product, Go to: www.freescale.com INDEX - 1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... INDEX —A— A0-A15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 —B— BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 4-16 BN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 4-16 Bootstrap Code . . . . . . . . . . . . . . . . . . . . . . . . .A-4 Bootstrap from EPROM (Mode 1) . . . . . . . . . . 3-8 Bootstrap from Host (Mode 5) . . . . . . . 3-11, 5-50 Bootstrap from SCI (Mode 6) . . . . . . . . 3-12, 6-71 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5, 4-16 Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 BS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 4-16 Bus Arbitration . . . . . . . . . . . . . . .4-16, 4-18, 4-20 Bus Control Register (BCR) . . . . . . . . . 4-13, B-10 —C— CD11–CD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Central Processing Module . . . . . . . . . . . . . . . 1-4 components . . . . . . . . . . . . . . . . . . . . . . . . 1-4 CKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 CKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 CLGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Clock Pins crystal output (XTAL) . . . . . . . . . . . . . . . . 2-8 external clock/crystal input (EXTAL) . . . . . 2-8 Clock Stabilization Delay . . . . . . . . . . . . . . . . . 3-7 CLVcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 COD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Command Vector Register (CVR) . . . . 5-26, B-18 CRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 bit 15 - prescaler range (PSR) . . . . . . . . 6-88 MOTOROLA bits 0-7 - prescale modulus select (PM0-PM7) . . . . . . . . . . . . . . . . . 6-87 bits 13,14 - word length control (WL0,WL1) . . . . . . . . . . . . . . . . 6-87 bits 8-12 - frame rate divider control (DC0-DC4) . . . . . . . . . . . . . . . . . 6-87 CRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-88 bit 0 - serial output flag 0 (OF0) . . . . . . . . 6-88 bit 1 - serial output flag 1 (OF1) . . . . . . . . 6-88 bit 10 - gated control clock (GCK) . . . . . . 6-91 bit 11 - mode select (MOD) . . . . . . . . . . . 6-92 bit 12 - transmit enable (TE) . . . . . . . . . . 6-92 bit 13 - receive enable (RE) . . . . . . . . . . . 6-92 bit 14 - transmit interrupt enable (TIE) . . . 6-93 bit 2 - serial control 0 direction (SCD0) . . 6-89 bit 3 - serial control 1 direction (SCD1) . . 6-89 bit 4 - serial control 2 direction (SCD2) . . 6-89 bit 5 - clock source direction (SCKD) . . . . 6-89 bit 6 - shift direction (SHFD) . . . . . . . . . . 6-91 bit 7,8 - frame sync length (FSL0, FSL1) . . . . . . . . . . . . . . . 6-91 bit 9 - sync/async (SYN) . . . . . . . . . . . . . 6-91 control bits . . . . . . . . . . . . . . . . . . . . . . . 6-112 receive interrupt enable (RIE) . . . . . . . . . 6-93 CVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-26 bit 0-5 - host vector (HV) . . . . . . . . . . . . . 5-26 bit 6 - reserved . . . . . . . . . . . . . . . . . . . . . 5-27 bit 7 - host command (HC) . . . . . . . . . . . 5-27 —D— D0-D23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Data Register (PBD) . . . . . . . . . . . . . . . . . . . B-14 Data Transfer DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 DSP to host . . . . . . . . . . . . . . . . . . 5-17, 5-51 HI host processor . . . . . . . . . . . . . . . . . . 5-34 For More Information On This Product, Go to: www.freescale.com INDEX - 3 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index (Continued) host to DSP . . . . . . . . . . . . . . . . . . . 5-17, 5-40 polling/interrupt controlled 5-38 Data Transmission . . . . . . . . . . . . . . . . . . . . . 6-30 DC4–DC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 Debug Request Input (DR) . . . . . . . . . . . . . . . 2-13 Development Mode (Mode 3) . . . . . . . . . . . . . 3-11 DMA . . . . . . . . . . . . . . . . . . . . . . .5-17, 5-19, 5-29 host to DSP . . . . . . . . . . . . . . . . . . . . . . . 5-57 DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 DMA Procedure DSP to host . . . . . . . . . . . . . . . . . . . . . . . 5-60 DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 DS1/OS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 DSCK/OS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 DSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 DSP to Host DMA Procedure . . . . . . . . . . . . . 5-60 DSP to Host Internal Processing . . . . . . . . . . 5-59 DSP56002 Features . . . . . . . . . . . . . . . . . . . . . 1-4 DSP56K Central Processing Module central components . . . . . . . . . . . . . . . . . . 1-4 —E— Exception (See Interrupt) EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 External Access Priority . . . . . . . . . . . . . . . . . . 4-3 —F— FE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Flags, SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-153 FSL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112 FSL0, FSL1 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91 FSL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112 —G— GCK . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91, 6-112 GPIO configuration . . . . . . . . . . . . . . . . . . . . . . . 5-4 programming port B . . . . . . . . . . . . . . . . . 5-5 programming port C . . . . . . . . . . . . . . . . . 6-6 —H— H0-H7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8, 5-30 HA0-HA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 INDEX - 4 HA0–HA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 HACK . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9, 5-32 Hardware Reset OnCE pins and . . . . . . . . . . . . . . . . . . . . 2-12 HC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 HCIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 HCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16, 5-19 HCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 bit 0 - host receive interrupt enable (HRIE) . . . . . . . . . . . . . . . . . . . . . 5-14 bit 1 - host transmit interrupt enable (HTIE) . . . . . . . . . . . . . . . . . . . . . 5-14 bit 2 - host command interrupt enable (HCIE) . . . . . . . . . . . . . . . . . . . . . 5-14 bit 3 - host flag 2 (HF2) . . . . . . . . . . . . . . 5-14 bit 4 - host flag 3 (HF3) . . . . . . . . . . . . . . 5-15 bits 5,6,7 - reserved . . . . . . . . . . . . . . . . . 5-15 HEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9, 5-32 HF0 . . . . . . . . . . . . . . . . . . . . . . . 5-16, 5-19, 5-23 reading during transition . . . . . . . . . . . . . 5-19 HF1 . . . . . . . . . . . . . . . . . . . . . . . 5-16, 5-19, 5-23 reading during transition . . . . . . . . . . . . . 5-19 HF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14, 5-28 HF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15, 5-28 HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3, 5-10 DSP viewpoint . . . . . . . . . . . . . . . . . . . . . 5-11 example circuits . . . . . . . . . . . . . . . . . . . . 5-62 features . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 host processor viewpoint . . . . . . . . . . . . . 5-19 programming model . . . . . . . . . . . . . . . . . 5-20 servicing protocols . . . . . . . . . . . . . . . . . . 5-33 HI Application Examples . . . . . . . . . . . . . . . . .5-37 bootstrap from host . . . . . . . . . . . . . . . . . 5-50 HI initialization . . . . . . . . . . . . . . . . . . . . . 5-38 host to DSP data transfer . . . . . . . . . . . . 5-40 polling/interrupt controlled data transfer . . . . . . . . . . . . . . . . 5-38 HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .5-34 DSP CPU . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 host processor . . . . . . . . . . . . . . . . . . . . . 5-18 HI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8, 5-30 host acknowledge (HACK) . . . . . . . 2-9, 5-32 host address (HA0-HA2) . . . . . . . . . 2-9, 5-31 host data bus pins (H0-H7) . . . . . . . 2-8, 5-30 host enable (HEN) . . . . . . . . . . . . . . 2-9, 5-32 host read/write (HR/W) . . . . . . . . . . 2-9, 5-32 host request (HREQ) . . . . . . . . . . . . 2-9, 5-32 HI Programming Model . . . . . . . . . . . . . . . . . .5-12 HM1 and HM0 . . . . . . . . . . . . . . . . . . . . . . . . .5-23 Host Command Feature . . . . . . . . . . . . . . . . .5-20 Host Control Register (HCR) . . . . . . . . . 5-14, B-16 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index (Continued) Host Flag Operation . . . . . . . . . . . . . . . . . . . . 5-15 Host Interface (HI) . . . . . . . . . . . . . . . . . 5-3, 5-10 Host Port Usage Considerations DSP Side . . . . . . . . . . . . . . . . . . . . . . 5-18 Host Port Usage Considerations Host Side . . . . . . . . . . . . . . . . . . . . . . 5-65 Host Receive Data Register (HRX) . . . 5-17, B-17 Host Registers After Reset as seen by DSP . . . . . . . . . . . . . . . . . . . 5-17 as seen by host processor . . . . . . . . . . . 5-30 Host Status Register (HSR) . . . . . . . . . 5-15, B-17 Host to DSP DMA Procedure . . . . . . . . . . . . . 5-57 Host To DSP Internal Processing . . . . . . . . . . 5-56 Host Transmit Data Register (HTX) . . . 5-17, B-17 HR/W . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9, 5-32 HRDF . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15, 5-19 HREQ Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 HREQ Pin . . . . . . . . . . . . . . . 2-9, 5-22, 5-23, 5-32 HRIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 HRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 HSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 bit 0 - host receive data full (HRDF) . . . . 5-15 bit 1 - host transmit data empty (HTDE) . . . . . . . . . . . . . . . . . . . . 5-15 bit 2 - host command pending (HCP) . . . 5-16 bit 3 - host flag 0 (HF0) . . . . . . . . . . . . . . 5-16 bit 4 - host flag 1 (HF1) . . . . . . . . . . . . . . 5-16 bit 5,6 - reserved . . . . . . . . . . . . . . . . . . . 5-17 bit 7 - DMA status (DMA) . . . . . . . . . . . . 5-17 HTDE . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15, 5-19 HTIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 HTX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26, 5-46 —I— ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 bit 0 - receive request enable (RREQ) . . 5-22 bit 1 - transmit request enable (TREQ) . . 5-22 bit 2 - reserved . . . . . . . . . . . . . . . . . . . . 5-23 bit 3 - host flag 0 (HF0) . . . . . . . . . . . . . . 5-23 bit 4 - host flag 1 (HF1) . . . . . . . . . . . . . . 5-23 bit 5,6 - host mode control (HM1, HM0) . . . . . . . . . . . . . . . . 5-23 bit 7 - initialize bit (INIT) . . . . . . . . . . . . . 5-24 IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 IF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94 IF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94 ILIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20, 6-39 INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 MOTOROLA Instruction Set Summary . . . . . . . . . . . . . . . . . B-5 Internal Processing DSP to host . . . . . . . . . . . . . . . . . . . . . . . 5-59 host to DSP . . . . . . . . . . . . . . . . . . . . . . . 5-56 INterrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Interrupt host command . . . . . . . . . . . . . . . . . . . . . 5-43 host receive data . . . . . . . . . . . . . . . . . . . 5-43 host transmit data . . . . . . . . . . . . . . . . . . 5-43 SCI idle line . . . . . . . . . . . . . . . . . . . . . . . 6-39 SCI receive data . . . . . . . . . . . . . . . . . . . 6-37 SCI receive data with exception status . . 6-39 SCI timer . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 SCI transmit data . . . . . . . . . . . . . . . . . . . 6-39 SSI receive data . . . . . . . . . . . . . . . . . . 6-109 SSI receive data with exception status . . . . . . . . . . . . 6-109 SSI transmit data . . . . . . . . . . . . . . . . . . 6-109 SSI transmit data with exception status . . . . . . . . . . . . 6-109 Starting Addresses . . . . . . . . . . . . . . . . . . B-4 Interrupt Control Register (ICR) . . . . . . 5-20, B-18 Interrupt Priority Register (IPR) . . . . . . . 3-12, B-11 Interrupt Status Register (ISR) . . . . . . . 5-27, B-19 Interrupt Vector Register (IVR) . . . . . . . 5-29, B-19 Interrupts DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 non-DMA . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 IPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 bit 0 - receive data register full (RXDF) . . 5-27 bit 1 - transmit data register empty (TXDE) . . . . . . . . . . . . . . . . . . . . 5-28 bit 2 - transmitter ready (TRDY) . . . . . . . 5-28 bit 3 - host flag 2 (HF2) . . . . . . . . . . . . . . 5-28 bit 4 - host flag 3 (HF3) . . . . . . . . . . . . . . 5-28 bit 5 - reserved . . . . . . . . . . . . . . . . . . . . . 5-28 bit 6 - DMA status (DMA) . . . . . . . . . . . . . 5-29 bit 7 - host request (HREQ) . . . . . . . . . . . 5-29 IVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 —M— MA, MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 Memory Modules . . . . . . . . . . . . . . . . . . . . . . . .3-3 program memory . . . . . . . . . . . . . . . . . . . . 3-3 X data memory . . . . . . . . . . . . . . . . . . . . . 3-4 Y data memory . . . . . . . . . . . . . . . . . . . . . 3-4 For More Information On This Product, Go to: www.freescale.com INDEX - 5 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index (Continued) MF0-MF11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 MOD . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92, 6-112 MODA/IRQA . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 MODB/IRQB . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 MODC/NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Multidrop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 address mode wakeup . . . . . . . . . . . . . . 6-61 example . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 idle line wakeup . . . . . . . . . . . . . . . . . . . . 6-57 transmitting data and address characters . . . . . . . . . . . 6-57 wired-or mode . . . . . . . . . . . . . . . . . . . . . 6-57 Multiplication Factor . . . . . . . . . . . . . . . . . . . . 3-13 —N— Network Mode . . . . . . . . . . . . . . . . . . . . . . . 6-135 Network Mode Receive . . . . . . . . . . . . . . . . 6-144 Network Mode Transmit . . . . . . . . . . . . . . . . 6-140 Normal Expanded Mode (Mode 2) . . . . . . . . . 3-11 Normal Mode Receive . . . . . . . . . . . . . . . . . 6-133 Normal Mode Transmit . . . . . . . . . . . . . . . . . 6-130 —O— OF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88 OF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88 OMR chip operating mode (bit 4) . . . . . . . . . . . . 3-7 data rom enable (bit 1) . . . . . . . . . . . . . . . 3-6 stop delay (bit 6) . . . . . . . . . . . . . . . . . . . . 3-7 Y memory disable (bit 3) . . . . . . . . . . . . . . 3-6 OnCE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 debug request input (DR) . . . . . . . . . . . . 2-13 debug serial input/chip status 0 (DS1/OS0) . . . . . . . . . . . . . . . . . 2-11 debug serial output (DS0) . . . . . . . . . . . . 2-12 On-chip Peripherals Memory Map . . . . . . . . . .B-3 Operating Mode Register (OMR) . . . . . . . . . .B-12 Operating Modes . . . . . . . . . . . . . . . . . . . 3-3, 3-7 mode 0 - single chip mode . . . . . . . . . . . . 3-8 mode 1 - bootstrap from EPROM . . . . . . . 3-8 mode 2 - normal expanded mode . . . . . . 3-11 mode 3 - development mode . . . . . . . . . 3-11 mode 4 - reserved mode . . . . . . . . . . . . . 3-11 mode 5 - bootstrap from host . . . . . . . . . 3-11 mode 6 - bootstrap from SCI . . . . . . . . . . 3-12 mode 7 - reserved mode . . . . . . . . . . . . . 3-12 setting, changing . . . . . . . . . . . . . . . . . . . . 3-7 summary . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 INDEX - 6 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 —P— PBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 PBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 PBDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 PCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 PCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 PCDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 PEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14 Peripheral Memory Map . . . . . . . . . . . . . . . . . B-3 PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 PINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14 Pins (Signals) . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 PLL Control Register (PCTL) . . . . . . . . . . . . B-13 PLL Lock State . . . . . . . . . . . . . . . . . . . . . . . .2-14 PLL Multiplication Factor . . . . . . . . . . . . . . . . .3-13 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 analog PLL circuit ground (PGND) . . . . . 2-13 analog PLL circuit power (PVcc) . . . . . . . 2-13 CKOUT Ground (CLGND) . . . . . . . . . . . . 2-13 CKOUT Polarity Control (CKP) . . . . . . . . 2-14 CKOUT power (CLVcc) . . . . . . . . . . . . . . 2-13 output clock (CKOUT) . . . . . . . . . . . . . . . 2-14 phase and frequency locked (PLOCK) . . 2-14 PLL filter off-chip capacitor (PCAP) . . . . . 2-13 PLL initialization input (PINIT) . . . . . . . . . 2-14 PLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14 PM7–PM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Port A Address Pins . . . . . . . . . . . . . . . . . 2-4, 4-3 Port A Bus Control Pins . . . . . . . . . . . . . . 2-4, 4-3 bus grant (BG) . . . . . . . . . . . . . . . . . . . . . . 2-6 bus needed (BN) . . . . . . . . . . . . . . . . . . . . 2-5 bus request (BR) . . . . . . . . . . . . . . . . . . . . 2-5 bus strobe (BS) . . . . . . . . . . . . . . . . . . . . . 2-6 bus wait (WT) . . . . . . . . . . . . . . . . . . . . . . 2-6 data memory select (DS) . . . . . . . . . . . . . . 2-5 program memory select (PS) . . . . . . . . . . . 2-4 read enable (RD) . . . . . . . . . . . . . . . . . . . . 2-5 write enable (WR) . . . . . . . . . . . . . . . . . . . 2-5 X/Y select (X/Y) . . . . . . . . . . . . . . . . . . . . . 2-5 Port A Data Bus Pins . . . . . . . . . . . . . . . . 2-4, 4-3 Port A Interrupt and Mode Control Pins . . . . . .2-6 MODA/IRQA . . . . . . . . . . . . . . . . . . . . . . . 2-6 MODB/IRQB . . . . . . . . . . . . . . . . . . . . . . . 2-7 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index (Continued) MODC/NMI . . . . . . . . . . . . . . . . . . . . . . . . 2-7 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Port A Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Port A Wait States . . . . . . . . . . . . . . . . . . . . . 4-13 Port B Control Register (PBC) . . . . . . . . . B-14, B-16 Data Direction Register (PBDDR) . . . . . . B-14 Data Register (PBD) . . . . . . . . . . . . . . . . B-14 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 host interface (HI) . . . . . . . . . . . . . . . . . . . 5-3 introduction . . . . . . . . . . . . . . . . . . . . . . . . 5-3 pin control logic . . . . . . . . . . . . . . . . . . . . . 5-4 Port B Control Register (PBC) . . . . . . . . . . . . . 5-4 Port B Data Direction Register (PBDDR) . . . . . 5-4 Port B Data Register (PBD) . . . . . . . . . . . . . . . 5-4 Port B GPIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Port C Control Register (PCC) . . . . .B-15, B-21, B-24 Data Direction Register (PCDDR) . . . . . . B-15 Data Register (PCD) . . . . . . . . . . . . . . . . B-15 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3, 6-4 introduction . . . . . . . . . . . . . . . . . . . . . . . . 6-3 pin control logic . . . . . . . . . . . . . . . . . . . . . 6-4 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Port C Control Register (PCC) . . . . . . . . . . . . . 6-4 Port C Data Direction Register (PCDDR) . . . . . 6-4 Port C Data Register . . . . . . . . . . . . . . . . . . . . 6-4 Port C GPIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Power Pins ground (GND) . . . . . . . . . . . . . . . . . . . . . . 2-8 power (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Program Memory . . . . . . . . . . . . . . . . . . . . . . . 3-3 Programming Model HI . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12, 5-20 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 PS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 PSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88 PVcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 —R— R8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 RCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 RDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97 MOTOROLA RDRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-92 Receive Byte Registers (RXH, RXM, RXL) . . . . . . . . . . 5-29, B-20 Reset register contents and . . . . . . . . . . . . . . . . 5-17 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 RFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-95 RIE . . . . . . . . . . . . . . . . . . . 6-21, 6-37, 6-39, 6-93 ROE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-96 RREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22 RWU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-97 RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10, 6-12 RXDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 RXH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 RXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 RXM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 —S— SBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 SC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10, 6-82 SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11, 6-82 SC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11, 6-83 SCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24 bit 12 - clock out divider (COD) . . . . . . . . 6-26 bit 13 - clock prescaler (SCP) . . . . . . . . . 6-26 bit 14 - receive clock mode source (RCM) . . . . . . . . . . . . . . . . . . . . 6-26 bit 15 - transmit clock source (TCM) . . . . 6-26 bits 11-0 - clock divider (CD11-CD0) . . . . 6-25 SCD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-89 SCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-89 SCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-89 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3, 6-11 example circuits . . . . . . . . . . . . . . . . . . . . 6-74 features . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 programming model . . . . . . . . . . . . . . . . . 6-12 SCI Asynchronous Data . . . . . . . . . . . . . . . . .6-44 multidrop . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 reception . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 transmission . . . . . . . . . . . . . . . . . . . . . . 6-48 SCI Clock Control Register (SCCR) . . . 6-24, B-22 SCI Control Register (SCR) . . . . . . . . . 6-14, B-21 SCI Data Registers . . . . . . . . . . . . . . . . . . . . .6-26 receive registers (SRX) . . . . . . . . . 6-26, B-23 transmit registers (STX, STXA) . . . 6-28, B-23 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . .6-31 For More Information On This Product, Go to: www.freescale.com INDEX - 7 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index (Continued) SCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 receive data (RXD) . . . . . . . . . . . . . 2-10, 6-12 SCI serial clock (SCLK) . . . . . . . . . . 2-10, 6-12 transmit data (TXD) . . . . . . . . . . . . . 2-10, 6-12 SCI Registers after Reset . . . . . . . . . . . . . . . . 6-31 SCI Status Register (SSR) . . . . . . . . . . 6-22, B-22 SCI Synchronous Data . . . . . . . . . . . . . . . . . . 6-39 SCI Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11, 6-80 SCKD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89 SCKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10, 6-12 SCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 bit 0-2 - word select (WDS0,WDS1,WDS2) . . . . . . . . 6-14 bit 10 - idle line interrupt enable (ILIE) . . 6-20 bit 12 - transmit interrupt enable (TIE) . . 6-21 bit 13 - timer interrupt enable (TMIE) . . . 6-21 bit 14 - timer interrupt rate (STIR) . . . . . . 6-21 bit 15 - clock polarity (SCKP) . . . . . . . . . 6-22 bit 3 - shift direction (SSFTD) . . . . . . . . . 6-18 bit 4 - send break (SBK) . . . . . . . . . . . . . 6-18 bit 4 - wakeup mode select (WAKE) . . . . 6-18 bit 6 - receiver wakeup enable (RWU) . . 6-18 bit 7 - wired-or mode select (WOMS) . . . 6-19 bit 8 - receiver enable (RE) . . . . . . . . . . . 6-19 bit 9 - transmitter enable (TE) . . . . . . . . . 6-19 receive interrupt enable (RIE) . . . . . . . . . 6-21 SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Serial Communication Interface (SCI) . . 6-3, 6-11 Shared Memory . . . . . . . . . . . . . . . . . . . . . . . 4-16 SHFD . . . . . . . . . . . . . . . . . . . . . . . . . 6-91, 6-112 Single Chip Mode (Mode 0) . . . . . . . . . . . . . . . 3-8 Slow Memory Accommodation . . . . . . . . . . . . 4-13 SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11, 6-80 SRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 SSFTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3, 6-76 features . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 operational modes . . . . . . . . . . . . . . . . . 6-100 pin definitions . . . . . . . . . . . . . . . . . . . . 6-100 SSI Control Register A (CRA) . . . . . . . 6-87, B-24 SSI Control Register B (CRB) . . . . . . . 6-88, B-25 SSI Example Circuits . . . . . . . . . . . . . . . . . . 6-157 SSI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-153 SSI Initialization . . . . . . . . . . . . . . . . . . . . . . 6-104 SSI Operating Modes network mode examples . . . . . . . . . . . . 6-135 normal . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112 normal mode examples . . . . . . . . . . . . . 6-127 INDEX - 8 normal/network . . . . . . . . . . . . . . . . . . . 6-112 on-demand mode examples . . . . . . . . . 6-145 SSI Pins . . . . . . . . . . . . . . . . . . . . . . . . 2-10, 6-78 serial clock (SCK) . . . . . . . . . . . . . . . . . . 6-80 serial clock zero (SC0) . . . . . . . . . . . . . . 2-10 serial control (SC0) . . . . . . . . . . . . . . . . . 6-82 serial control (SC1) . . . . . . . . . . . . . . . . . 6-82 serial control (SC2) . . . . . . . . . . . . . . . . . 6-83 serial control one (SC1) . . . . . . . . . . . . . . 2-11 serial control two (SC2) . . . . . . . . . . . . . . 2-11 serial receive data (SRD) . . . . . . . . . . . . 6-80 serial transmit data (STD) . . . . . . . . . . . . 6-78 SSI receive data (SRD) . . . . . . . . . . . . . . 2-11 SSI serial clock (SCK) . . . . . . . . . . . . . . . 2-11 SSI transmit data (STD) . . . . . . . . . . . . . 2-11 SSI Programming Model . . . . . . . . . . . . . . . . .6-83 SSI Receive Data Register (RX) . . . . . . . . . . .6-97 SSI Receive Shift Register . . . . . . . . . . . . . . .6-97 SSI Registers After Reset . . . . . . . . . . . . . . .6-100 SSI Status Register (SSISR) . . . . . . . . . 6-94, B-26 SSI Transmit Data Register (TX) . . . . . . . . .6-100 SSI Transmit Shift Register . . . . . . . . . . . . . . .6-97 SSISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-94 bit 0 - serial input flag 0 (IF0) . . . . . . . . . . 6-94 bit 1 - serial input flag 1 (IF1) . . . . . . . . . . 6-94 bit 2 - transmit frame sync flag (TFS) . . . 6-94 bit 3 - receive frame sync flag (RFS) . . . . 6-95 bit 4 - transmitter underrun error flag (TUE) . . . . . . . . . . . . . . . . . . . . . 6-96 bit 5 - receiver overrun error flag (ROE) . . . . . . . . . . . . . . . . . . . . . 6-96 bit 6 - transmit data register empty (TDE) . . . . . . . . . . . . . . . . . . . . . 6-97 bit 7 - receive data register full (RDF) . . . 6-97 SSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 bit 0 - transmitter empty (TRNE) . . . . . . . 6-22 bit 1 - transmit data register empty (TDRE) . . . . . . . . . . . . . . . . . . . 6-22 bit 2 - receive data register full (RDRF) . . 6-23 bit 3 - idle line flag (IDLE) . . . . . . . . . . . . 6-23 bit 4 - overrun error flag . . . . . . . . . . . . . . 6-23 bit 5 - parity error (PE) . . . . . . . . . . . . . . . 6-23 bit 6 - framing error flag (FE) . . . . . . . . . . 6-24 bit 7 - received bit 8 address (R8) . . . . . . 6-24 Status Register (SR) . . . . . . . . . . . . . . . . . . . B-10 STD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11, 6-78 STIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 STX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 STXA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 SYN . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91, 6-112 Synchronous Serial Interface (SSI) . . . . . . . . . .6-3 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Index (Continued) Freescale Semiconductor, Inc... —T— TCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 TCSR bit 0 - Timer Enable (TE) . . . . . . . . . . . . . . 7-5 bit 1 - Timer Interrupt Enable (TIE) . . . . . . 7-5 bit 10 - Data Output (DO) . . . . . . . . . . . . . 7-7 bit 11-23 - TCSR Reserved Bits . . . . . . . . 7-7 bit 2 - Inverter (INV) . . . . . . . . . . . . . . . . . . 7-5 bit 6 - General Purpose I/O (GPIO) . . . . . . 7-6 bit 7 - Timer Status (TS) . . . . . . . . . . . . . . 7-7 bit 8 - Direction (DIR) . . . . . . . . . . . . . . . . 7-7 bit 9 - Data Input (DI) . . . . . . . . . . . . . . . . . 7-7 bits 3-5 - Timer Control (TC0-TC2) . . . . . . 7-6 TDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97 TDRE . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22, 6-30 TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19, 6-92 TIE . . . . . . . . . . . . . . . . . . . . . . . .6-21, 6-39, 6-93 Time Slot Register (TSR) . . . . . . . . . . . . . . . 6-100 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . 7-3 Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 During STOP . . . . . . . . . . . . . . . . . . . . . . 7-16 During WAIT . . . . . . . . . . . . . . . . . . . . . . 7-16 GPIO . . . . . . . . . . . . . . . . . . . . . . . . 7-18, 7-19 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . 7-7, 7-8 Mode 0 Example . . . . . . . . . . . . . . . . . . . 7-20 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Mode 4 Example . . . . . . . . . . . . . . . . . . . 7-21 Mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Mode 5 Example . . . . . . . . . . . . . . . . . . . 7-22 Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Mode 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Operating Considerations . . . . . . . . . . . . 7-17 Period Measurement Mode . . 7-12, 7-15, 7-16 Programming Model . . . . . . . . . . . . . . . . . 7-4 PWM Mode . . . . . . . . . . . . . . 7-11, 7-13, 7-14 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . .7-5, B-27 Timer Count Register (TCR) . . . . . . .7-4, B-27 Timer/Event Counter Module Pin (TIO) . . . . . 2-14 TMIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Transmit Byte Registers (TXH, TXM, TXL) . . . . . . . . . . 5-30, B-20 TRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 TREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 TRNE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 TSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100 TUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96 MOTOROLA TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-100 TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10, 6-12 TXDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 TXH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 TXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 TXM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 —W— WAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 WDS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 WDS0, WDS1, WDS2 . . . . . . . . . . . . . . . . . . .6-14 WDS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 WDS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 WL0, WL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 WOMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 WT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 4-16 —X— X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . .3-4 X/Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 —Y— Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . .3-4 Y data ram . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Y data rom . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 YD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 For More Information On This Product, Go to: www.freescale.com INDEX - 9 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Order this document by DSP56002UM/AD Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer. OnCE is a trade mark of Motorola, Inc. Motorola Inc., 1994 For More Information On This Product, Go to: www.freescale.com