ETC EDI2CG272128V-D1

EDI2CG272128V
2x128Kx72, 3.3V Sync/Sync Burst Flow-Through
FEATURES
■ 2x128Kx72 Synchronous, Synchronous Burst
The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst
SRAM, 72 position DIMM (144 contacts) Module, small outline.
The Module contains four (4) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm TQFP
placed on a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sync Burst, Flow-Through, with support for
either linear or sequential burst. This module provides High
Performance, 2-1-1-1 accesses when used in Burst Mode, and
used as a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device architectures.
■ Flow-Through Architecture
■ Linear and Sequential Burst Support via MODE pin
■ Access Speed(s): T KHQV = 8.5, 9, 12, 15ns
■ Clock Controlled Registered Bank Enables (E1 , E2)
■ Clock Controlled Registered Address
■ Clock Controlled Registered Global Write (GW)
■ Aysnchronous Output Enable (G)
Synchronous Only operations are performed via strapping ADSC
Low, and ADSP / ADV High, which provides for Ultra Fast Accesses
in Read Mode while providing for internally self-timed Early
Writes.
■ Internally Self-timed Write
■ Individual Bank Sleep Mode Enables (ZZ 1, ZZ 2)
■ Gold Lead Finish
■ 3.3V ±10% Operation
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined for Quad Word access in
both read and write operations.
■ Common Data I/O
■ High Capacitance (30pF) Drive, at Rated Access Speed
■ Single Total Array Clock
■ Multiple Vcc and Gnd
August 2000 Rev.0
ECO#13088
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG272128V
PIN CONFIGURATION
PIN SYMBOLS
PIN NAMES
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
DQ0-63
1
VSS
37
DQ0
73
VSS
109
DQ41
DQP0-7
Parity Bits
2
VSS
38
DQ7
74
VSS
110
DQ46
A0-16
Address Bus
3
A0
39
DQ1
75
ZZ2
111
DQ42
4
RFU
40
DQ6
76
DQP3
112
DQ45
E1, E2
Synchronous Bank Enables
Array Clock
PIN
FUNCTION
Input/Output Bus
5
A16
41
DQ2
77
VCC
113
DQ43
CLK
6
A1
42
DQ5
78
VCC
114
DQ44
GW
7
A2
43
DQ3
79
DQ24
115
VSS
Synchronous Global Write
Enable
8
A15
44
DQ4
80
DQ31
116
VSS
9
A14
45
VSS
81
DQ25
117
RFU
G
Asynchronous Output Enable
DQP6
ZZ1, ZZ2 Blank Sleep Mode Enables
10
A3
46
VSS
82
DQ30
118
11
A4
47
ZZ1
83
DQ26
119
VCC
Vcc
12
A13
48
DQP1
84
DQ29
120
VCC
Vss
Ground
13
A12
49
VCC
85
DQ27
121
DQ48
NC
No Connect
14
A5
50
VCC
86
DQ28
122
DQ55
15
A6
51
DQ8
87
VSS
123
DQ49
16
A11
52
DQ15
88
VSS
124
DQ54
17
A10
53
DQ9
89
RFU
125
DQ50
18
A7
54
DQ14
90
DQP4
126
DQ53
19
A8
55
DQ10
91
VCC
127
DQ51
20
A9
56
DQ13
92
VCC
128
DQ52
21
VCC
57
DQ11
93
DQ32
129
VSS
22
VCC
58
DQ12
94
DQ39
130
VSS
23
G
59
VSS
95
DQ33
131
RFU
24
RFU
60
VSS
96
DQ38
132
DQP7
25
GW
61
E2
97
DQ34
133
VCC
26
ADV
62
DQP2
98
DQ37
134
VCC
27
ADSP
63
VCC
99
DQ35
135
DQ56
28
ADSC
64
VCC
100
DQ36
136
DQ63
29
MODE
65
DQ16
101
VSS
137
DQ57
30
CLK
66
DQ23
102
VSS
138
DQ62
31
VSS
67
DQ17
103
RFU
139
DQ58
32
VSS
68
DQP5
140
DQ61
E1
69
DQ22
DQ18
104
33
105
VCC
141
DQ59
34
DQP0
70
DQ21
106
VCC
142
DQ60
35
VCC
71
DQ19
107
DQ40
143
VSS
144
VSS
36
VCC
72
DQ20
108
DQ47
FIG. 1
3.3V Power Supply
FUNCTIONAL BLOCK DIAGRAM
A0-16
ADSC
ADSP
ADV
CLK
G
GW
E1
ZZ1
E2
ZZ2
ADSC
ADSP
ADV
CLK
G
GW
E
ZZ
ADSC
ADSP
ADV
CLK
G
GW
E
ZZ
ADSC
ADSP
ADV
CLK
G
GW
E
ZZ
ADSC
ADSP
ADV
CLK
G
GW
E
ZZ
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
DQ
DQ0-31
DQP0-3
U1
DQ
DQ0-31
DQP0-3
U2
DQ
DQ32-63
DQP4-7
U3
DQ
DQ32-63
DQP4-7
U4
August 2000 Rev.0
ECO#13088
EDI2CG272128V
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
A0-16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
25
GW
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE and BWx lines
and must meet the setup and hold times around the rising edge of CLK.
30
CLK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
33, 61
E1, E2
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP
23
G
Input
26
ADV
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
27
ADSP
Input
Synchronous
Address Status Processor: This active LOW input, along with EL and EH being LOW, causes a new externaladdress
to be registered and a READ cycle is initiated using the new address.
28
ADSC
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
29
MODE
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST.
47, 75
ZZ1, ZZ2
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode. For normal
operation, this input has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is
DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
34, 48, 62, 76,
90, 104, 118, 132
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3 is
parity bit for DQ24-31. DQP4 is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6 is parity bit for DQ48-55. DQP7
is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to
Vss through a 10K ohm resistor.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
3, 6, 10, 11, 14, 15,
18, 19, 20, 17, 16,
13, 12, 9, 8, 3, 5
August 2000 Rev.0
ECO#13088
Description
Output Enable: This active LOW asynchronous input enables the data output drivers.
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG272128V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
E1
H
X
L
L
H
H
L
H
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
E2
X
H
H
H
L
L
H
L
H
H
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
ADSP
X
X
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
X
H
X
ADSC
L
L
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
ADV
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
GW
X
X
X
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
G
X
X
L
H
L
H
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
H
L
H
L
H
L
H
X
X
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Addr. Used
None
None
External
External
External
External
External
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
August 2000 Rev.0
ECO#13088
EDI2CG272128V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1
E2
GW
G
ZZ
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
L
L
H
H
H
H
H
H
X
H
H
L
L
H
H
H
H
X
L
H
L
H
L
H
L
H
X
H
L
H
L
H
L
H
L
X
L
L
L
L
L
L
L
L
H
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Relative to Vss
Vin
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
CLK
↑
↑
↑
↑
↑
↑
↑
↑
DQ
High-Z
High-Z
High-Z
High-Z
X
High-Z
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
0°C to +70°C
-40°C to +85°C
10 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in operational sections of this
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Sym
VCC
VSS
VIH
VIL
ILI
ILo
Min
3.14
0.0
2.0
-0.3
-2
-2
Typ
3.3
0.0
3.0
0.0
1
1
Max
3.6
0.0
VCC +0.3
0.8
2
2
Units
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Power Supply Current
Power Supply Current
Symbol
Icc1
Icc
Typ
1.55
750
8.5
2.2
1.5
9
2.1
1.5
12
2.1
1.0
15
2.0
1.0
Units
A
A
IccZZ
Icc3
IccK
150
400
600
200
600
1.0
200
600
1.0
200
600
0.75
200
600
0.75
mA
mA
A
Device Selected, No Operation
Snooze Mode
CMOS Standby
Clock Running-Deselect
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/O
Z0
Z0==50Ω
50Ω
Input Pulse Levels
Input and Output Timing Levels
Output Test Equivalencies
50Ω
I/O
Unit
VSS to 3.0
V
1.25
V
See figure, at left
Vt = 1.5V
1.25V
FIG. 2
AC OUTPUT LOAD EQUIVALENT
August 2000 Rev.0
ECO#13088
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG272128V
BURST ADDRESS TABLE (MODE = NC/V CC)
First
Address
(external)
A..A00
A..A01
A..A10
A..A11
Second
Address
(internal)
A..A01
A..A00
A..A11
A..A10
Third
Address
(internal)
A..A10
A..A11
A..A00
A..A01
BURST ADDRESS TABLE (MODE = V SS)
First
Address
(external)
A..A00
A..A01
A..A10
A..A11
Fourth
Address
(internal)
A..A11
A..A10
A..A01
A..A00
Second
Address
(internal)
A..A01
A..A10
A..A11
A..A00
Third
Address
(internal)
A..A10
A..A11
A..A00
A..A01
Fourth
Address
(internal)
A..A11
A..A00
A..A01
A..A10
READ CYCLE TIMING PARAMETERS
8.5ns
9ns
Description
Sym
Min
Max
Min
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
10
4
4
12ns
Max
Min
15ns
Max
12
5
5
10
3
2
4
0
5
0
4
2.5
2.5
1.0
1.0
12
3
2
4
0
Max
15
5
5
9
3
2
Min
4
2.5
2.5
1.0
1.0
5
2.5
2.5
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*TBD
FIG. 3
SYNCHRONOUS ONLY READ CYCLE
tKHKH
tKHKL
tKLKH
CLK
tAVKH
EX
ADDR
G
Addr 1
Addr 1
tKHAX
tKHQV
tGLQV
tGLQX
GW
tKHQX
DQ
Addr 2
Q(Addr 1)
Q(Addr 1)
tKHQZ
tKHQX1
Read Cycle
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Q(Addr 2)
Back to Back Read
6
August 2000 Rev.0
ECO#13088
EDI2CG272128V
FIG. 4
SYNCHRONOUS-BURST READ CYCLE
tKHKH
tKHKL
tKLKH
CLK
tSPVKH
tKHSPX
ADSP
tSCVKH
tKHSCX
ADSC
tAVKH
tKHAX
ADDR
BWx,
GW
tEVKH
tKHEX
Ex
tAVVKH
tKHAVX
ADV
tGHQX
tKHQV
G
tGLQV
tGLQX
tGHQZ
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
August 2000 Rev.0
ECO#13088
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG272128V
WRITE CYCLE TIMING PARAMETERS
8.5ns
Description
Sym
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
FIG. 5
Min
9ns
Max
Min
12ns
Max
9
4
4
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Min
15ns
Max
12
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNCHRONOUS (NON-BURST) WRITE CYCLE
tKHKH
tKHKL
tAVKH
tKHAX
tKLKH
CLK
Ex
ADDR
Addr 1
Addr 1
Addr 2
tKHGWH
tGWLKH
GW
G
tKHGH
DQ
tKHDX
tDVKH
tGHKH
Write Cycle
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Back to Back Writes
8
August 2000 Rev.0
ECO#13088
EDI2CG272128V
FIG. 6
SYNCHRONOUS-BURST WRITE CYCLE
tKHKH
tKHKL
tKLKH
CLK
ADSP
ADSC
tAVKH
tKHAX
ADDR
BWx,
GW
tEVKH
tKHEX
Ex
tAVVKH
tKHAVX
ADV
G
tDVKH
tKHQX
DQ
tKHQX
Early Write Cycle
August 2000 Rev.0
ECO#13088
Burst - Late Write- Cycle
9
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG272128V
FIG. 7
SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
tKHKH
tKHKL
tKLKH
CLK
tAVKH
Ex
ADDR
G
Addr 1
Addr 2
tKHQV
tKHDX
GW
tKHQX
DQ
Q (Addr 1)
D (Addr 2)
tDVKH
Read Cycle
tKHDX
Write Cycle
Back to Back Cycles
G Controlled
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
10
August 2000 Rev.0
ECO#13088
EDI2CG272128V
PACKAGE DESCRIPTION:
144 LEAD SMALL OUTLINE DIMM
Package No. 409
0.175
MAX.
R9
R3
R1
R11
2.667 MAX.
0.157
U1
R18
U3
R17
R15
R7
R13
R5
1.000
MAX.
0.788
P1
0.181 TYP
0.913
1.112
1.291
1.490
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
EDI2CG272128V85D1*
EDI2CG272128V9D1*
EDI2CG272128V12D1
EDI2CG272128V15D1
Organization
2x128Kx72
2x128Kx72
2x128Kx72
2x128Kx72
Voltage
3.3
3.3
3.3
3.3
Speed (ns)
8.5
9
12
15
Package
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
*Consult Factory for Availability
August 2000 Rev.0
ECO#13088
11
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com