ETC EDI2CG472256V-D2

EDI2CG472256V
4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through
FEATURES
■ 4x256Kx72 Synchronous, Synchronous Burst
The EDI2CG472256VxxD2 is a Synchronous/Synchronous Burst
SRAM, 84 position Dual Key; Double High DIMM (168 contacts)
Module, organized as 4x256Kx72. The Module contains sixteen
(16) Synchronous Burst Ram Devices, packaged in the industry
standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/Sync
Burst, Flow-Through, with support for either linear or sequential
burst. This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only Mode,
provides a high performance cost advantage over BiCMOS
aysnchronous device architectures.
■ Flow-Through Architecture
■ Linear and Sequential Burst Support via MODE pin
■ Clock Controlled Registered Module Enable (EM\)
■ Clock Controlled Registered Bank Enables (E1\, E2\, E 3\, E 4\)
■ Clock Controlled Byte Write Mode Enable (BWE\)
■ Clock Controlled Byte Write Enables (BW1\ - BW8\)
■ Clock Controlled Registered Address
■ Clock Controlled Registered Global Write (GW\)
■ Aysnchronous Output Enable (G\)
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
■ Internally self-timed Write
■ Individual Bank Sleep Mode enables (ZZ1, ZZ 2, ZZ 3, ZZ4 )
■ Gold Lead Finish
■ 3.3V ±10%, - 5% Operation
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
■ Access Speed(s): tKHQV = 9, 10, 12, 15ns
■ Common Data I/O
■ High Capacitance (30pF) drive, at rated Access Speed
■ Single total array Clock
■ Multiple Vcc and Gnd
August 1998 Rev. 1
ECO #10656
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
PIN CONFIGURATION
PIN SYMBOLS
PIN
FRONT
PIN
BACK
1
2
3
4
5
6
7
VSS
A0
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VSS
A17
A1
A15
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
A16
A2
A14
VCC
A4
A12
A6
A10
VSS
A8
NC
E4\
E2 \
VSS
MODE
EM\
GW\
NC1
VCC
BW4\
BW3\
BW8\
BW7\
ADSC\
ADSP\
VSS
NC2
VCC
DQ0
DQ1
DQ2
DQ3
VSS
ZZ1
VCC
DQ8
DQ9
DQ10
DQ11
VSS
121
122
123
124
125
126
A3
VCC
A13
A5
A11
A7
VSS
A9
NC3
E1\
E3 \
VSS
CLK
VSS
G\
BWE\
VCC
BW2\
BW1\
BW6\
BW5\
VSS
ADV\
VSS
DQP0
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQP1
VCC
DQ15
DQ14
DQ13
DQ12
VSS
PIN NAMES
PIN
FRONT
PIN
BACK
DQ0-63
43
NC4
VCC
DQ16
127
128
DQP2
VCC
DQ23
DQ22
DQ21
DQ20
DQP0-7
Parity Bits
A0-17
Address Bus
EM\
Address Enable
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ17
DQ18
DQ19
VSS
ZZ2
VCC
DQ24
DQ25
DQ26
DQ27
VSS
NC5
VCC
DQ32
DQ33
DQ34
DQ35
VSS
ZZ3
VCC
DQ40
DQ41
DQ42
DQ43
VSS
NC6
VCC
DQ48
DQ49
DQ50
DQ51
VSS
ZZ4
VCC
DQ56
DQ57
DQ58
DQ59
VSS
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129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
DQP3
VCC
DQ31
DQ30
DQ29
DQ28
VSS
DQP4
VCC
DQ39
DQ38
DQ37
DQ36
VSS
DQP5
VCC
DQ47
DQ46
DQ45
DQ44
VSS
DQP6
VCC
DQ55
DQ54
DQ53
DQ52
VSS
DQP7
VCC
DQ63
DQ62
DQ61
DQ60
VSS
2
Input/Output Bus
E1\, E2\,
Synchronous Bank Enables
E3\, E4\
BWE\
Byte Write Mode Enable
BW1-8\
Byte Write Enables
CLK
Array Clock
GW\
Synchronous Global Write
Enable
G\
Asynchronous Output Enable
ZZ1, ZZ2,
Synchronous Bank Enables
ZZ3, ZZ4
Vcc
3.3V Power Supply
Vss
Ground
NC
No Connect
EDI2CG472256V
FUNCTIONAL BLOCK DIAGRAM
ZZ1
E1\
MODE
GW\
G\
EM\
CLK
ADSC\
ADSP\
ADV\
A0-17
BW1\
BW2\
DQP0
DQP1
DQ0-15
ZZ2
E2\
ZZ3
E 3\
ZZ4
E4\
U1
U5
U9
U13
BW3\
BW4\
DQP2
DQP3
DQ16-31
U2
U6
U10
U14
BW5\
BW6\
DQP4
DQP5
DQ32-47
U3
U7
U11
U15
BW7\
BW8\
DQP6
DQP7
DQ48-63
U4
U8
U12
U16
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
A0-17
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times around the rising
edgeof CLK. The burst counter generates internal addresses associated with A0 and A1, during burst
and wait cycle.
BW1\, BW2\,
BW3\, BW4\,
BW5\, BW6\,
BW7\, BW8\
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW0/ controls DQ0-7
and DQP0, BW1\ controls DQ8-15 and DQP1. BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31
and DQP3. BW4\ controls DQ32-39 and DQP4. BW5\ controls DQ40-47 and BW6\ controls DQ48-55 and
DQP6. BW7\ controls DQ56-64 and DQP7.
104
BWE\
Input
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
times around the rising edge of CLK.
19
GW\
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and
BWx\ lines and must meet the setup and hold times around the rising edge of CLK.
101
CLK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on
its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
E1\, E2\
E3\, E4\
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
103
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
111
ADV\
Input
Synchronous
Address Status Processor: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle (no address advance).
27
ADSP\
Input
Synchronous
Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a
new external address to be registered and a READ cycle is initiated using the new address.
26
ADSC\
Input
Synchronous
Address Status Controller: This active LOW input causes device to be deselected or selected along
with new external address to be registered. A READ or WRITE cycle is initiated depending upon write
control inputs.
17
MODE
Input Static
36, 50,
64, 78
ZZ1, ZZ2,
ZZ3, ZZ4
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode.
For normal operation, this input has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is
DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
113, 120, 127,
134, 141, 148,
155, 162
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit
for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4\ is parity bit for DQ32-39. DQP5 is parity bit for
DQ40-47. DQP6\ is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and DQP7. In order to use the
device configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor.
Various
Vcc
Supply
Power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
2, 87, 4, 89, 7, 92
9, 94, 12, 96, 10
93, 8, 91, 5, 88,
3, 86
107, 106, 23,
22, 109, 108,
25, 24
98, 15,
99,14
Description
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
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4
EDI2CG472256V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
E1\
H
X
L
L
H
H
L
H
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
E2\
X
H
H
H
L
L
H
L
H
H
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
E3\
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
E4\
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ADSP\ ADSC\
X
L
X
L
L
X
L
X
L
X
L
X
H
L
H
L
H
L
H
L
H
L
H
L
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
H
H
X
H
H
H
X
H
H
H
H
H
H
H
H
H
X
H
X
H
X
H
X
H
H
H
X
H
H
H
X
H
ADV\
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
GW\
X
X
X
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
G\
X
X
L
H
L
H
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
H
L
H
L
H
L
H
X
X
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Addr. Used
None
None
External
External
External
External
External
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
*All Truth Table Functions Repeat for Bank 3 (E3\) and Bank 4 (E4\)
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
E1\
L
L
H
H
H
H
H
H
X
E2\
H
H
L
L
H
H
H
H
X
E3\
H
H
H
H
L
L
H
H
X
E4\
H
H
H
H
H
H
L
L
X
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Relative to Vss
Vin
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
GW\
L
H
L
H
L
H
L
H
X
G\
H
L
H
L
H
L
H
L
X
ZZ
L
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
Output High
IOH = -4mA
Output Low
IOL = 8mA
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
0°C to +70°C
-40°C to +85°C
20mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Sym
VCC
VSS
VIH
VIL
ILi
ILo
VOH
Min
3.14
0.0
2.0
-0.3
-2
-2
-
Typ
3.3
0.0
3.0
0.0
1
1
-
Max
3.6
0.0
VCC+0.3
0.8
2
2
2.4
Units
V
V
V
V
µA
µA
V
VOL
0.4
-
-
V
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Power Supply Current
Power Supply Current
Symbol
Icc1
Icc
Typ
2.0
875
8.5
2.9
1.8
10
2.7
1.8
12
2.7
1.3
15
2.5
1.3
Units
A
A
IccZZ
Icc3
IccK
500
270
900
700
350
1.1
700
350
1.1
700
350
1.0
700
350
1.0
mA
mA
A
Device Selected,No Operation
Snooze Mode
CMOS Standby
Clock Running-Deselect
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Output
Z0
Z0==50Ω
50Ω
Input Pulse Levels
Input and Output Timing Levels
Output Test Equivalencies
50Ω
Vt = 1.5V
1.25V
AC Output Load Equivalent
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
6
I/O
Unit
VSS to 3.0
V
1.25
V
See figure, at left
EDI2CG472256V
BURST ADDRESS TABLE (MODE = NC/V CC)
First
Address
(external)
A..A00
A..A01
A..A10
A..A11
Second
Address
(internal)
A..A01
A..A00
A..A11
A..A10
Third
Address
(internal)
A..A10
A..A11
A..A00
A..A01
BURST ADDRESS TABLE (MODE = V SS )
First
Address
(external)
A..A00
A..A01
A..A10
A..A11
Fourth
Address
(internal)
A..A11
A..A10
A..A01
A..A00
Second
Address
(internal)
A..A01
A..A10
A..A11
A..A00
Third
Address
(internal)
A..A10
A..A11
A..A00
A..A01
Fourth
Address
(internal)
A..A11
A..A00
A..A01
A..A10
READ CYCLE TIMING PARAMETERS
9ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
Sym
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
Min
15
5
5
Max
Min
15
5
5
9
3
4
10ns
Max
5
0
15
5
5
2.5
2.5
1.0
1.0
6
0
5
2.5
2.5
1.0
1.0
15ns
Max
3
4
0
5
Min
20
6
6
12
3
4
5
2.5
2.5
1.0
1.0
12ns
Max
10
3
4
0
Min
15
5
5
5
2.5
2.5
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*TBD
SYNCHRONOUS ONLY READ CYCLE
tKHKH
tKHKL
tKLKH
CLK
tAVKH
Ex\
CE\
ADDR
G\
OE\
Addr 1
Addr 1
tKHAX
tKHQV
tGLQV
tGLQX
GW\
tKHQX
DQ
Addr 2
Q(Addr 1)
Q(Addr 1)
tKHQZ
Q(Addr 2)
tKHQX1
Read Cycle
Back to Back Read
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
SYNCHRONOUS BURST READ CYCLE
tKHKH
tKHKL
tKLKH
CLK
tSPVKH
tKHSPX
ADSP\
tSCVKH
tKHSCX
ADSC\
tAVKH
tKHAX
ADDR
BWx\,
GW\
tEVKH
tKHEX
Ex\
tAVVKH
tKHAVX
ADV\
tGHQX
tKHQV
G\
tGLQV
tGLQX
tGHQZ
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
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8
EDI2CG472256V
WRITE CYCLE TIMING PARAMETERS
9ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
Sym
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Max
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
10ns
Max
Min
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
12ns
Max
Min
20
6
6
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
15ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*TBD
SYNCHRONOUS (NON-BURST) WRITE CYCLE
tKHKH
tKHKL
tAVKH
tKHAX
tKLKH
CLK
Ex\
CE\
ADDR
Addr 1
Addr 1
Addr 2
tKHGWH
tGWLKH
GW\
OE\
G\
tKHGH
DQ
tKHDX
tDVKH
tGHKH
Write Cycle
Back to Back Writes
9
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
SYNCHRONOUS BURST WRITE CYCLE
tKHKH
tKHKL
tKLKH
CLK
ADSP\
ADSC\
tAVKH
tKHAX
ADDR
BWx\,
GW\
tEVKH
tKHEX
Ex\
tAVVKH
tKHAVX
ADV\
G\
tDVKH
tKHQX
DQ
tKHQX
Early Write Cycle
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Burst - Late Write- Cycle
10
EDI2CG472256V
SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
tKHKH
tKHKL
tKLKH
CLK
tAVKH
CE\
Ex\
ADDR
G\
Addr 1
Addr 2
tKHQV
tKHDX
GW\
tKHQX
DQ
Q (Addr 1)
D (Addr 2)
tDVKH
Read Cycle
tKHDX
Write Cycle
Back to Back Cycles
G\ Controlled
11
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472256V
PACKAGE DESCRIPTION
168 LEAD DUAL KEY DIMM
Package No. 406
0.195
MAX.
5.255 MAX.
0.157
(2x)
195
1.500
MAX.
0.700
P1
0.078 (2X)
0.450
0.575
.050 TYP.
0.250
1.450
0.350
0.925
2.150
0.125
(2X)
0.125
1.700
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
EDI2CG472256V9D2*
EDI2CG472256V10D2*
EDI2CG472256V12D2
EDI2CG472256V15D2
Organization
4x256Kx72
4x256Kx72
4x256Kx72
4x256Kx72
Voltage
3.3
3.3
3.3
3.3
Speed (ns)
9
10
12
15
*Consult Factory for Availability
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
12
Package
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
0.225
MIN.