EL7104 ® Data Sheet July 6, 2006 High Speed, Single Channel, Power MOSFET Driver FN7113.2 Features • Industry-standard driver replacement The EL7104 is a matched driver IC that improves the operation of the industry-standard TC-4420/29 clock drivers. The Elantec version is a very high speed driver capable of delivering peak currents of 1A into highly capacitive loads. The high speed performance is achieved by means of a proprietary “Turbo-Driver” circuit that speeds up input stages by tapping the wider voltage swing at the output. Improved speed and drive capability are enhanced by matched rise and fall delay times. These matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and clock skew problems. This improved performance is accompanied by a 10-fold reduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with CMOS drivers. • Improved response times • Matched rise and fall times • Reduced clock skew • Low output impedance • Low input capacitance • High noise immunity • Improved clocking rate • Low supply current • Wide operating range • Separate drain connections The EL7104 is available in 8-pin SO and 8-pin PDIP packages and is specified for operation over the full -40°C to +85°C temperature range. • Pb-Free available (RoHS compliant) Ordering Information • Clock/line drivers PART NUMBER PART MARKING EL7104CN EL7104CN EL7104CNZ TAPE & PACKAGE REEL 8 Ld PDIP PKG. DWG. # Applications • CCD drivers • Ultrasound transducer drivers - MDP0031 • Power MOSFET drivers EL7104CN Z 8 Ld PDIP* - MDP0031 • Switch mode power supplies EL7104CS 7104CS 8 Ld SOIC - MDP0027 • Resonant charging EL7104CS-T7 7104CS 8 Ld SOIC 7” MDP0027 • Cascoded drivers EL7104CS-T13 7104CS 8 Ld SOIC 13” MDP0027 EL7104CSZ (See Note) 7104CSZ 8 Ld SOIC (Pb-free) - MDP0027 EL7104CSZ-T7 (See Note) 7104CSZ 8 Ld SOIC (Pb-free) 7” MDP0027 EL7104CSZ-T13 7104CSZ (See Note) 8 Ld SOIC (Pb-free) 13” MDP0027 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout EL7104 (8-PIN SO, PDIP) TOP VIEW V+ 1 8 V+ IN 2 7 P_OUT NC 3 6 N_OUT GND 4 5 GND *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7104 Absolute Maximum Ratings (TA = 25°C) Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER V+ = 15V, TA = 25°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current VHVS Input Hysteresis 2.4 @V+ V 0.1 @0V 0.1 10 µA 0.8 V 10 µA 0.3 V OUTPUT ROH Pull-Up Resistance IOUT = -100mA 1.5 4 Ω ROL Pull-Down Resistance IOUT = +100mA 2 4 Ω IOUT Output Leakage Current V+/GND 0.2 10 µA IPK Peak Output Current Source/Sink 4.0 IDC Continuous Output Current Source/Sink A 200 mA POWER SUPPLY IS Power Supply Current VS Operating Voltage AC Electrical Specifications PARAMETER Input = V+ 4.5 4.5 7.5 mA 16 V MAX UNIT V = 15V, TA = 25°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V) tR tF Rise Time Fall Time CL = 1000pF 7.5 ns CL = 2000pF 10 CL = 1000pF 10 CL = 2000pF 15 20 ns 20 ns ns tD-ON Turn-On Delay Time See Timing Table 18 25 ns tD-OFF Turn-Off Delay Time See Timing Table 18 25 ns 2 EL7104 Timing Table 5V Input 2.5V 0 Inverted Output EL7114 Non-inverted Output EL7104 90% 10% 90% 10% tF tD1 tD2 tR tF Standard Test Configuration 1 8 2 D.U.T. 4 Simplified Schematic 3 4.7µF 6 7 Input Signal 5 tR Output Signal 2000pF EL7104 Typical Performance Curves MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE PEAK DRIVE vs SUPPLY VOLTAGE INPUT CURRENT vs VOLTAGE QUIESCENT SUPPLY CURRENT 4 “ON” RESISTANCE vs SUPPLY VOLTAGE EL7104 Typical Performance Curves (Continued) AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY RISE/FALL TIME vs SUPPLY VOLTAGE RISE/FALL TIME vs TEMPERATURE 5 RISE/FALL TIME vs LOAD PROPAGATION DELAY vs SUPPLY VOLTAGE RISE/FALL TIME vs TEMPERATURE EL7104 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 6 EL7104 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7