EtronTech EM564081 512K x 8 Low Power SRAM Preliminary, Rev 0.7 01/2001 Features Pin Configuration • Single power supply voltage of 2.3V to 3.6V 36-Ball BGA (CSP), Top View • Power down features using CE1# and CE2 • Low power dissipation • Data retention supply voltage: 1.0V to 3.6V • Direct TTL compatibility for all input and output 1 2 3 4 5 6 A A0 A1 CE2 A3 A6 A8 B DQ4 A2 WE# A4 A7 DQ0 C DQ5 NC A5 D GND VDD E VDD GND F DQ6 G DQ7 H A9 • Wide operating temperature range: -40°C to 85°C • Standby current @ VDD = 3.6 V DQ1 IDDS2 Typical Maximum EM564081BA/BC-70/85 1 µA 10 µA EM564081BA/BC-70E/85E 5 µA 80 µA A18 A17 DQ2 OE# CE1# A16 A15 DQ3 A10 A11 A12 A13 A14 Ordering Information Part Number Speed IDDS2 Package EM564081BC-70 70 ns 10 µA 6x8 BGA EM564081BC-70E 70 ns 80 µA 6x8 BGA EM564081BA-70 70 ns 10 µA 8x10 BGA EM564081BA-70E 70 ns 80 µA 8x10 BGA EM564081BC-85 85 ns 10 µA 6x8 BGA EM564081BC-85E 85 ns 80 µA 6x8 BGA EM564081BA-85 85 ns 10 µA 8x10 BGA EM564081BA-85E 85 ns 80 µA 8x10 BGA Pin Description Symbol Function A0 - A18 DQ0 – DQ7 CE1#, CE2 OE# WE# GND VDD NC Address Inputs Data Inputs / Outputs Chip Enable Inputs Output Enable Read / Write Control Input Ground Power Supply No Connection Overview The EM564081 is a 4,194,304-bit SRAM organized as 512K by 8 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40°C to 85°C, the EM564081 can be used in environments exhibiting extreme temperature conditions. Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM564081 Block Diagram A0 VDD MEMORY CELL ARRAY 512KX8 GND A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SENSE AMP COLUMN ADDRESS DECODER W E# CE1# CE2 OE# POWER DOWN CIRCUIT Preliminary 2 Rev 0.7 January 2001 EtronTech EM564081 Operating Mode Mode CE1# CE2 OE# WE# DQ0~DQ7 Read L H L H DOUT Write L H X L DIN Output Deselect L H H H High-Z H X X X X L X X Standby High-Z Note: X = don't care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD -0.3 to +4.6V Input voltages, VIN -0.3 to +4.6V Input and output voltages, VI/O -0.5 to VDD +0.5V Operating temperature, TOPR -40 to +85°C Storage temperature, TSTRG -55 to +150°C Soldering Temperature (10s), TSOLDER 260°C Power dissipation, PD 0.6 W DC Recommended Operating Conditions (Ta=-40°C to 85°C) Symbol Parameter Min Typ Max VDD Power Supply Voltage 2.3 − 3.6 VIH VIL Input High Voltage 2.2 (2) Input Low Voltage -0.3 VDR Data Retention Supply Voltage Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns (2) Undershoot : -2.0V in case of pulse width ≤ 20ns Preliminary 3 1.0 − VDD + 0.3 Unit V (1) V − 0.6 V − 3.6 V Rev 0.7 January 2001 EtronTech EM564081 DC Characteristics (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) Parameter Symbol Input low current IIL Test Conditions Min Typ* -1 − 1 µA IIN = 0V to VDD Max Unit Output low voltage VOL IOL = 2.1 mA - − 0.4 V Output high voltage VOH IOH = -1.0 mA VDD 0.15 − − V VDD = 3.6 V − 15 25 VDD = 2.7 V − 10 15 VDD = 2.3 V − 7 12 − − 5 − − 0.5 VDD = 3.6 V − 1 10 VDD = 2.7 V VDD = 2.3 V − 0.8 5 − 0.5 3 VDD = 3.6 V − 5 80 CE1# = VIL and IDD1 Operating current Cycle time = min CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL IDD2 IDDS1 Standby current IDDS2** (Note) Cycle time = 1µs CE1# = VIH or CE2 = VIL CE1# = VDD – 0.2V or -70/85 CE2 = 0.2V -70E/85E mA mA µA Notes: * Typical value are measured at Ta = 25°C. ** In standby mode with CE1# ≥ VDD - 0.2V, these limits are assured for the condition CE2 ≥ VDD - 0.2V or CE2 ≤ 0.2V. Capacitance (Ta = 25°C; f = 1 MHz) Parameter Input capacitance Symbol Min Typ Max Unit Test Conditions CIN − − 10 pF VIN = GND COUT 10 pF VOUT = GND − − Notes: This parameter is periodically sampled and is not 100% tested. Output capacitance Preliminary 4 Rev 0.7 January 2001 EtronTech EM564081 AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) Read Cycle EM564081 Symbol -85 Parameter -70 Unit Min Max Min Max tRC Read cycle time 85 − 70 − tAA Address access time − 85 − 70 tCO1 Chip Enable (CE1#) Access Time − 85 − 70 tCO2 Chip Enable (CE2) Access Time − 85 − 70 tOE Output enable access time − 45 − 35 tLZ Chip Enable Low to Output in Low-Z 10 − 10 − tOLZ Output enable Low to Output in Low-Z 3 − 3 − tHZ Chip Enable High to Output in High-Z − 35 − 25 Output Enable High to Output in High-Z − 35 − 25 Output Data Hold Time 10 − 10 − tOHZ tOH ns Write Cycle EM564081 Symbol -85 Parameter -70 Unit Min Max Min Max tWC Write cycle time 85 − 70 − tWP Write pulse width 55 − 55 − tCW Chip Enable to end of write 70 − 60 − tAS Address setup time 0 − 0 − tWR Write Recovery time 0 − 0 − tWHZ WE# Low to Output in High-Z − 35 − 30 tOW WE# High to Output in Low-Z 5 − 5 − tDS Data Setup Time 35 − 30 − tDH Data Hold Time 0 − 0 − ns AC Test Condition • Output load: 50pF + one TTL gate • Input pulse level: 0.4V, 2.4V • Timing measurements: 0.5 x VDD • tR, tF: 5ns Preliminary 5 Rev 0.7 January 2001 EtronTech EM564081 Read Cycle (See Note 1) t RC Ad d r e ss t OH t AA t CO1 CE 1 # CE2 t CO2 t HZ t OE O E# t OHZ t OLZ t LZ DO U T Preliminary VALID DATA OUT 6 Rev 0.7 January 2001 EtronTech EM564081 Write Cycle1 (WE# Controlled)(See Note 4) tW C Address t AS t WP tW R WE# t CW CE1# CE2 t CW t WHZ D OUT t OW (See Note2) (See Note3) t DS D IN Preliminary (See Note 5) VALID DATA IN 7 Rev 0.7 t DH (See Note 5) January 2001 EtronTech EM564081 Write Cycle 2 (CE1# Controlled)(See Note 4) tW C Address t AS tW P tW R W E# t CW CE1# CE2 t CW t W HZ D O UT t LZ t DS D IN Preliminary (See Note 5) t DH VALID DATA IN 8 Rev 0.7 January 2001 EtronTech EM564081 Write Cycle 3 (CE2 Controlled)(See Note 4) tW C Address t AS tW P tW R WE# t CW CE1# CE2 t CW t WHZ D OUT t LZ t DS D IN (See Note 5) t DH VALID DATA IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 9 Rev 0.7 January 2001 EtronTech EM564081 Data Retention Characteristics (Ta = -40°C to 85°C) Symbol Parameter VDR Data Retention Supply Voltage IDR Data Retention Current CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V VDD = 1.0V, CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V tSDR Chip Deselect to Data Retention Mode Time tRDR Recovery Time Min Typ Max Unit 1.0 − 3.6 V − 0.5 3.5 µA 0 − − ns tRC − − ns CE1# Controlled Data Retention Mode (see Note1) V DD V DD DATA RETENTION MODE 2.7V V IH t SDR CE1 V DD - 0.2V t RDR GND CE2 Controlled Data Retention Mode (see Note2) V DD VDD DATA RE TENTI ON MOD E 2. 7V V IH CE 2 t SDR t RD R V IL 0. 2V GN D Note: 1. If CE1# controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2V or CE2 ≥ VDD - 0.2V. 2. In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2V. Preliminary 10 Rev 0.7 January 2001 EtronTech EM564081 Package Diagrams 36-Ball (6mm x 8mm) BGA Units in mm TOP VIEW BOTTOM VIEW 2 C 0.25 S C 0.30 PIN 1 CORNER 1 0.10 S 3 4 5 6 6 5 4 PIN 1 CORNER A B 0.05(48X) 3 2 1 -B0.75 -A- 3.75 0.20(4X) 0.15 -C- Preliminary SEATING PLANE 11 Rev 0.7 January 2001 EtronTech EM564081 Package Diagrams 36-Ball (8mm x 10mm) BGA Units in mm TOP VIEW BOTTOM VIEW 2 C 0.25 S C 0.30 PIN 1 CORNER 1 0.10 S 3 4 5 6 6 5 4 PIN 1 CORNER A B 0.05(48X) 3 2 1 -B0.75 -A- 3.75 0.20(4X) 0.15 -C- Preliminary SEATING PLANE 12 Rev 0.7 January 2001