TC55NEM216ASTV55,70 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55NEM216ASTV is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7 to 5.5 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA standby current (typ) when chip enable ( CE ) is asserted high or chip select (CS) is asserted low. There are three control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55NEM216ASTV can be used in environments exhibiting extreme temperature conditions. The TC55NEM216ASTV is available in a plastic 44-pin thin-small-outline package (TSOP). FEATURES • • • • • • • Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 2.7 to 5.5 V Power down features using CE Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): 20 µA • Access Times (maximum): TC55NEM216ASTV • 55 70 Access Time 55 ns 70 ns CE Access Time 55 ns 70 ns OE Access Time 30 ns 35 ns Package: TSOP II44-P-400-0.80 (Weight: g typ) PIN ASSIGNMENT (TOP VIEW) PIN NAMES 44 PIN TSOP A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 R/W A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 CS A8 A9 A10 A11 A17 A0~A17 Address Inputs CE Chip Enable CS Chip Select R/W Read/Write Control OE Output Enable LB , UB I/O1~I/O16 Data Byte Control Data Inputs/Outputs VDD Power GND Ground NC No Connection 2002-10-30 1/12 TC55NEM216ASTV55,70 BLOCK DIAGRAM I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 ROW ADDRESS DECODER VDD GND MEMORY CELL ARRAY 2,048 × 128 × 16 (4,194,304) DATA OUTPUT BUFFER DATA INPUT BUFFER ROW ADDRESS REGISTER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA INPUT BUFFER SENSE AMP DATA OUTPUT BUFFER A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A17 ROW ADDRESS BUFFER CE COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR CE A0 A1 A2 A3 A4 A5 A16 CS CE CE LB UB R/W OE 2002-10-30 2/12 TC55NEM216ASTV55,70 OPERATING MODE MODE Read Write Output Deselect CS Standby CE CS OE R/W LB UB L H L H L L Output Output IDDO L H L H H L High-Z Output IDDO I/O1~I/O8 I/O9~I/O16 POWER L H L H L H Output High-Z IDDO L H * L L L Input Input IDDO L H * L H L High-Z Input IDDO L H * L L H Input High-Z IDDO L H H H L L High-Z High-Z IDDO L H H H H L High-Z High-Z IDDO L H H H L H High-Z High-Z IDDO * L * * * * High-Z High-Z IDDS H * * * * * High-Z High-Z IDDS * * * * H H High-Z High-Z IDDS Standby * = don't care H = logic high L = logic low MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage −0.3~7.0 V VIN Input Voltage −0.3*~7.0 V VI/O Input/Output Voltage −0.5~VDD + 0.5 V PD Power Dissipation 0.6 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −55~150 °C Topr Operating Temperature −40~85 °C *: −2.0 V when measured at a pulse width of 20ns DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) 5 V ± 10% SYMBOL 2.7 V~5.5 V PARAMETER UNIT MIN TYP MAX MIN TYP MAX 5.5 2.7 5.0 5.5 V VDD + 0.3 V VDD Power Supply Voltage 4.5 5.0 VIH Input High Voltage 2.2 VIL Input Low Voltage −0.3* 0.6 −0.3* 0.2 V VDH Data Retention Supply Voltage 2.0 5.5 2.0 5.5 V VDD + 0.3 VDD − 0.2 *: −2.0V when measured at a pulse width of 20 ns 2002-10-30 3/12 TC55NEM216ASTV55,70 DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 5 V ± 10%) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT ±1.0 µA IIL Input Leakage Current VIN = 0 V~VDD IOH Output High Current VOH = 2.4 V −1.0 mA IOL Output Low Current VOL = 0.4 V 2.1 mA ILO Output Leakage Current CE = VIH or CS = VIL or LB = UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ±1.0 µA MIN 35 1 µs 8 MIN 30 1 µs 3 3 lDDO1 Operating Current lDDO2 CE = VIL and CS = VIH and R/W = VIH, LB = UB = VIL, IOUT = 0 mA, Other Input = VIH/VIL tcycle CE = 0.2 V and CS = VDD − 0.2 V and R/W = VDD − 0.2 V, LB = UB = 0.2 V, IOUT = 0 mA, Other Input = VDD − 0.2 V/0.2 V tcycle mA mA 1) CE = VIH 2) CS= VIL IDDS1 mA 3) LB = UB = VIH Standby Current IDDS2 1) CE = VDD − 0.2 V Ta = 25°C 1 2) CS = 0.2 V Ta = −40~40°C 3 3) LB = UB = VDD − 0.2 V, CE = 0.2 V, CS = VDD − 0.2 V Ta = −40~85°C 20 MIN TYP MAX UNIT ±1.0 µA µA DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 3 V ± 10%) SYMBOL PARAMETER TEST CONDITION IIL Input Leakage Current VIN = 0 V~VDD IOH Output High Current VOH = VDD − 0.2 V −0.1 mA IOL Output Low Current VOL = 0.2 V 0.1 mA ILO Output Leakage Current CE = VIH or CS = VIL or LB = UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ±1.0 µA MIN 30 Operating Current CE = 0.2 V and CS = VDD − 0.2 V and R/W = VDD − 0.2 V, LB = UB = 0.2 V, IOUT = 0 mA, Other Input = VDD − 0.2 V/0.2 V tcycle 1 µs 3 1) CE = VDD − 0.2 V Ta = 25°C 1 2) CS = 0.2 V Ta = −40~40°C 3 3) LB = UB = VDD − 0.2 V, CE = 0.2 V, CS = VDD − 0.2 V Ta = −40~85°C 20 IDDO2 IDDS2 Standby Current mA µA CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2002-10-30 4/12 TC55NEM216ASTV55,70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 5 V ± 10%) READ CYCLE TC55NEM216ASTV SYMBOL PARAMETER 55 UNIT 70 MIN MAX MIN MAX tRC Read Cycle Time 55 70 tACC Address Access Time 55 70 tCO Chip Enable Access Time 55 70 tOE Output Enable Access Time 30 35 tBA Data Byte Control Access Time 55 70 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tBE Data Byte Control Low to Output Active 5 5 tOD Chip Enable High to Output High-Z 25 30 tODO Output Enable High to Output High-Z 25 30 tBD Data Byte Control High to Output High-Z 25 30 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55NEM216ASTV SYMBOL PARAMETER 55 UNIT 70 MIN MAX MIN MAX tWC Write Cycle Time 55 70 tWP Write Pulse Width 40 50 tCW Chip Enable to End of Write 45 55 tBW Data Byte Control to End of Write 45 55 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 25 30 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 25 30 tDH Data Hold Time 0 0 Note: ns tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. AC TEST CONDITIONS PARAMETER Input pulse level TEST CONDITION 0.4 V, 2.4 V tR, tF 5 ns Timing measurements 1.5 V Reference level 1.5 V Output load 100 pF + 1 TTL Gate 2002-10-30 5/12 TC55NEM216ASTV55,70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 5.5 V) READ CYCLE TC55NEM216ASTV SYMBOL PARAMETER 55 UNIT 70 MIN MAX MIN MAX tRC Read Cycle Time 70 85 tACC Address Access Time 70 85 tCO Chip Enable Access Time 70 85 tOE Output Enable Access Time 35 45 tBA Data Byte Control Access Time 70 85 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tBE Data Byte Control Low to Output Active 5 5 tOD Chip Enable High to Output High-Z 30 35 tODO Output Enable High to Output High-Z 30 35 tBD Data Byte Control High to Output High-Z 30 35 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55NEM216ASTV SYMBOL PARAMETER 55 UNIT 70 MIN MAX MIN MAX tWC Write Cycle Time 70 85 tWP Write Pulse Width 50 55 tCW Chip Enable to End of Write 55 60 tBW Data Byte Control to End of Write 55 60 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 30 35 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 30 35 tDH Data Hold Time 0 0 Note: ns tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. AC TEST CONDITIONS PARAMETER Input pulse level TEST CONDITION 0.2 V, VDD − 0.2 V tR, tF 5 ns Timing measurements 1.5 V Reference level 1.5 V Output load 100 pF (Include Jig) 2002-10-30 6/12 TC55NEM216ASTV55,70 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address A0~A17 tACC tOH tCO CE CS tOE tOD OE tBA tODO UB , LB tBE DOUT I/O1~16 tBD tOEE Hi-Z VALID DATA OUT Hi-Z tCOE WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A17 tAS tWP tWR R/W tCW CE CS tBW UB , LB tODW DOUT I/O1~16 (See Note 2) tOEW Hi-Z tDS DIN I/O1~16 (See Note 5) (See Note 3) tDH VALID DATA IN (See Note 5) 2002-10-30 7/12 TC55NEM216ASTV55,70 WRITE CYCLE 2 ( CE CONTROLLED) (See Note 4) tWC Address A0~A17 tAS tWP tWR R/W tCW CE CS tBW UB , LB tBE DOUT I/O1~16 Hi-Z tODW Hi-Z tCOE tDS DIN I/O1~16 (See Note 5) tDH VALID DATA IN WRITE CYCLE 3 ( UB, LB CONTROLLED) (See Note 4) tWC Address A0~A17 tAS tWP tWR R/W tCW CE CS tBW UB , LB tBE DOUT I/O1~16 Hi-Z tODW Hi-Z tCOE tDS DIN I/O1~16 (See Note 5) tDH VALID DATA IN 2002-10-30 8/12 TC55NEM216ASTV55,70 Note: (1) R/W remains HIGH for the read cycle. (2) If CE (or UB or LB ) goes LOW(or CS goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE (or UB or LB ) goes HIGH(or CS goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER VDH Data Retention Supply Voltage IDDS2 Standby Current MIN TYP MAX UNIT 2.0 5.5 V Ta = −40~40°C 3 Ta = −40~85°C 20 µA tCDR Chip Deselect to Data Retention Mode Time 0 ns tR Recovery Time 5 ms CE CONTROLLED DATA RETENTION MODE VDD VDD DATA RETENTION MODE 4.5 V (See Note 1) (See Note 1) VIH tCDR VDD − 0.2 V CE tR GND CS CONTROLLED DATA RETENTION MODE (See Note 2) VDD DATA RETENTION MODE VDD 4.5 V CS VIH VIL tCDR tR 0.2 V GND 2002-10-30 9/12 TC55NEM216ASTV55,70 UB , LB CONTROLLED DATA RETENTION MODE VDD VDD (See Note 3) DATA RETENTION MODE 4.5 V (See Note 4) (See Note 4) VIH tCDR UB , LB VDD − 0.2 V tR GND Note: (1) In CE controlled data retention mode, minimum standby current mode is entered when CS ≤ 0.2 V or CS ≥ VDD − 0.2 V. (2) When CE is operating at the VIH(min.) level(2.2 V), the operating current is given by IDDS1 during the transition of VDD from 4.5 to 2.4 V. (3) In CS controlled data retention mode, minimum standby current mode is entered when CS ≤ 0.2 V. (4) In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE ,CS ≤ 0.2 V or CE ,CS ≥ VDD − 0.2 V. (5) When UB (or LB ) is operating at the VIH(min.) level(2.2 V), the operating current is given by IDDS1 during the transition of VDD from 4.5 to 2.4 V. 2002-10-30 10/12 TC55NEM216ASTV55,70 PACKAGE DIMENSIONS Weight: g (typ) 2002-10-30 11/12 TC55NEM216ASTV55,70 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2002-10-30 12/12