P4C1024L P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM FEATURES VCC Current (Commercial/Industrial) — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70 (Commercial or Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 600 mil DIP —32-Pin 445 mil SOP DESCRIPTION The P4C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory ROW SELECT •• • (9) A 262,144BIT MEMORY ARRAY I/O1 • •• • • • ••• ••• ••• ••• INPUT DATA CONTROL COLUMN I/O I/O2 COLUMN SELECT WE CE1 CE2 ••• CONTROL CIRCUIT A (8) The P4C1024L is packaged in a 32-pin 445 mil SOP as well as a 600 mil PDIP. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM A locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 A0 12 21 CE1 I/O7 I/O0 13 20 I/O6 I/O1 I/O2 14 19 15 16 18 17 I/O5 I/O4 GND ••• A I/O3 DIP (P600), SOP (S12) TOP VIEW OE Means Quality, Service and Speed 1Q97 151 P4C1024L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 4.5V ≤ VCC ≤ 5.5V Industrial (-40°C to 85°C) 4.5 ≤ VCC ≤ 5.5V MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Parameter Min Max Unit VCC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Test Conditions Symbol Parameter VOH Output High Voltage (I/O0 - I/O7) IOH = –1mA, VCC = 4.5V VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current GND ≤ VIN ≤ VCC ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE1 ≥ VIH or CE2 ≤ VIL ISB VCC Current TTL Standby Current (TTL Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V 152 Min Max Unit V 2.4 0.4 V 2.2 VCC + 0.3 V -0.5 0.8 V Ind'l. Com'l. -5 -2 +5 +2 µA Ind'l. Com'l. -5 -2 +5 +2 µA 3 mA 100 µA P4C1024L CAPACITANCES (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Test Conditions Max Unit Input Capacitance VIN = 0V 7 pF Output Capacitance VOUT = 0V 9 pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC * ** Parameter Temperature Range -55 -70 -55 -70 Dynamic Operating Current Commercial Industrial 70 85 70 85 15 25 15 25 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. **As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -70 -55 Max Min Min Max Unit tRC Read Cycle Time tAA Address Access Time 55 70 ns tAC Chip Enable Access Time Output Hold from Address Change 55 70 ns tOH 55 ns 70 5 5 ns 10 10 ns tLZ Chip Enable to Output in Low Z tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 30 35 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 5 5 20 0 ns 25 0 55 153 ns ns 70 ns P4C1024L OE CONTROLLED)(1) READ CYCLE NO. 1 (OE tRC(5) ADDRESS tAA OE tOE tOH tOLZ CE CE2 tAC tOHZ tHZ tLZ DATA OUT Notes: 1. WE is HIGH for READ cycle. 2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. READ CYCLE NO. 2 (ADDRESS CONTROLLED) tRC (5) ADDRESS tAA tOH PREVIOUS DATA VALID DATA OUT DATA VALID CE CONTROLLED) READ CYCLE NO. 3 (CE tRC CE1 CE2 tHZ tAC tLZ DATA OUT DATA VALID HIGH IMPEDANCE ICC VCC SUPPLY CURRENT tPU tPD ISB 154 P4C1024L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -55 -70 Symbol Parameter tWC Write Cycle Time 55 70 ns tCW Chip Enable Time to End of Write 50 60 ns tAW Address Valid to End of Write 50 60 ns tAS Address Set-up Time 0 0 ns tWP Write Pulse Width 40 50 ns tAH Address Hold Time 0 0 ns tDW Data Valid to End of Write 25 30 ns tDH Data Hold Time 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write Min Max Min Max 25 30 5 5 (9) tWC ADDRESS tCW CE1 CE2 tAW tAH WE tAS tDW DATA IN tWZ DATA OUT tDH DATA VALID (7) (4) tOW (4,7) DATA UNDEFINED HIGH IMPEDANCE Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. 155 ns ns WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE tWP Unit P4C1024L CE CONTROLLED)(6) TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE tWC (9) ADDRESS tAS tCW CE1 tAH tAW CE2 tWP WE tDW DATA VALID DATA IN DATA OUT tDH (12) HIGH IMPEDANCE TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels CE1 CE2 OE WE I/O GND to 3.0V Mode Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V 1.5V Standby X L X X High Z Standby DOUT Disabled L H H H High Z Active See Figures 1 and 2 Read L DOUT L L X H Write H H L High Z Active Active Output Timing Reference Level Output Load Power +5V R TH = 638.7 Ω 1800 Ω D OUT DOUT 990 Ω 30pF* (5pF* for t HZ , t LZ , t OHZ , t OLZ t, WZ and t OW ) Figure 1. Output Load VTH = 1.77 V 30pF* (5pF* for t HZ , t LZ , t OHZ, t OLZ , t WZ and t OW ) Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the P4C1024L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. 156 To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). P4C1024L DATA RETENTION Symbol Parameter Test Conditions Min Max Unit 2.0 5.5 V VDR VCC for Data Retention CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICCDR (1) Data Retention Current VDR = 2.0V 30 µA VDR = 3.0V 50 µA tCDR Chip Deselect to Data Retention Time tR Operating Recovery Time See Retention Waveform 0 ns 5 ms 1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 ≤ 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V CE1 CONTROLLED) LOW VCC DATA RETENTION WAVEFORM 1 (CE Data Retention Mode VCC V DR 4.5V tCDR CE1 2.2V 4.5V tR CE 1≥ VDR -0.2V 2.2V LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED) Data Retention Mode V CC V DR 4.5V tCDR CE2 VIL 4.5V tR CE2 ≤ 0.2V 2.2V 157 VIL P4C1024L TEMPERATURE RANGE SUFFIX PACKAGE SUFFIX Package Suffix Temperature Description Range Suffix Description P Plastic DIP, 600 mil wide standard S SOP, 445 mil wide standard C I Commercial Temperature Range, 0˚C to +70˚C Industrial Temperature Range, -40˚C to +85˚C ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 1024L ss p t Temperature Range: C, I Package Code: P, S Speed (Access/Cycle Time): 55, 70 Device Number: 1024L Static RAM Prefix SELECTION GUIDE The P4C1024L is available in the following temperature, speed and package options. Temperature Range Package Speed (ns) -55 -70 Commercial Temperature Plastic DIP 600 Plastic SOP 445 -55PC -55SC -70PC -70SC Industrial Temperature Plastic DIP 600 -55PI -55SI -70PI -70SI Plastic SOP 445 158