EMC EM78P260NKM

EM78P259N/260N
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
June 2005
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes
no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN
Microelectronics makes no commitment to update, or to keep current the information and material contained in
this specification. Such information and material may change to conform to each confirmed order.
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or material.
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may be used or copied only in accordance with the terms of such agreement.
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NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
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No. 12, Innovation Road 1
Hsinchu Science Park
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Tel: +886 3 563-9977
Fax: +886 3 563-9966
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Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information Technology
Group
Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
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Elan Microelectronics Corp.
(Europe)
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai Corporation, Ltd.
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Fax: +86 021 5080-4600
Contents
Contents
1
2
3
General Description .................................................................................................. 1
Features ..................................................................................................................... 1
Pin Configuration (Package) .................................................................................... 2
3.1
4
5
6
EM78P259NP/M Pin Assignment....................................................................... 2
3.2 EM78P260NP/M/KM Pin Assignment ................................................................ 3
Functional Block Diagram........................................................................................ 3
Pin Description.......................................................................................................... 4
5.1
EM78P259NP/M Pin Description ....................................................................... 4
5.2
EM78P260NP/M/KM Pin Description ................................................................. 5
Function Description ................................................................................................ 6
6.1
Operational Registers......................................................................................... 6
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.2
R0 (Indirect Address Register) ............................................................................6
R1 (Time Clock /Counter)....................................................................................6
R2 (Program Counter) and Stack........................................................................6
6.1.3.1 Data Memory Configuration .................................................................8
R3 (Status Register) ............................................................................................9
R4 (RAM Select Register)...................................................................................9
R5 ~ R6 (Port 5 ~ Port 6) ..................................................................................10
R7 (Port 7).........................................................................................................10
R8 (AISR: ADC Input Select Register) ..............................................................11
R9 (ADCON: ADC Control Register).................................................................12
RA (ADOC: ADC Offset Calibration Register) ...................................................13
RB (ADDATA: Converted Value of ADC)...........................................................13
RC (ADDATA1H: Converted Value of ADC)......................................................14
RD (ADDATA1L: Converted Value of ADC) ......................................................14
RE (Interrupt Status 2 & Wake-Up Control Register) ........................................14
RF (Interrupt Status 2 Register) ........................................................................15
R10 ~ R3F .........................................................................................................15
Special Purpose Registers ............................................................................... 16
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
A (Accumulator).................................................................................................16
CONT (Control Register)...................................................................................16
IOC50 ~ IOC70 (I/O Port Control Register) ......................................................17
IOC80 (Comparator and TCCA Control Register).............................................17
IOC90 (TCCB and TCCC Control Register ).....................................................18
IOCA0 (IR and TCCC Scale Control Register) .................................................19
IOCB0 (Pull-Down Control Register).................................................................21
IOCC0 (Open-Drain Control Register) ..............................................................21
Product Specification (V1.0) 06.16.2005
• iii
Contents
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
6.2.16
6.2.17
6.2.18
6.2.19
6.3
TCC/WDT and Prescaler.................................................................................. 28
6.4
I/O Ports ........................................................................................................... 29
6.4.1
6.5
Usage of Port 5 Input Change Wake-up/Interrupt Function..............................32
RESET and Wake-up ....................................................................................... 32
6.5.1
6.5.2
RESET and Wake-up Operation .......................................................................32
6.5.1.1 Wake-Up and Interrupt Modes Operation Summary..........................35
6.5.1.2 Register Initial Values after Reset ......................................................37
6.5.1.3 Controller Reset Block Diagram.........................................................42
The T and P Status under STATUS Register ....................................................42
6.6
Interrupt ............................................................................................................ 42
6.7
Analog-To-Digital Converter (ADC) .................................................................. 45
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.8
6.9
ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ...............................45
6.7.1.1 R8 (AISR: ADC Input Select Register) ...............................................45
6.7.1.2 R9 (ADCON: ADC Control Register)..................................................46
6.7.1.3 RA (ADOC: ADC Offset Calibration Register) ....................................47
ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ...............48
ADC Sampling Time ..........................................................................................48
AD Conversion Time .........................................................................................48
ADC Operation during Sleep Mode...................................................................48
Programming Process/Considerations..............................................................49
6.7.6.1 Programming Process........................................................................49
6.7.6.2 Sample Demo Programs ....................................................................50
Infrared Remote Control Application/PWM Waveform Generation................... 52
6.8.1
6.8.2
6.8.3
Overview ...........................................................................................................52
Function Description..........................................................................................53
Programming the Related Registers ................................................................55
Timer/Counter................................................................................................... 56
6.9.1
6.9.2
6.9.3
iv •
IOCD0 (Pull-high Control Register)...................................................................22
IOCE0 (WDT Control & Interrupt Mask Registers 2) ........................................22
IOCF0 (Interrupt Mask Register).......................................................................23
IOC51 (TCCA Counter) .....................................................................................24
IOC61 (TCCB Counter) .....................................................................................24
IOC71 (TCCBH/MSB Counter) .........................................................................25
IOC81 (TCCC Counter).....................................................................................25
IOC91 (Low-Time Register) ..............................................................................26
IOCA1 (High Time Register) .............................................................................26
IOCB1 High/Low Time Scale Control Register) ................................................26
IOCC1 (TCC Prescaler Counter) ......................................................................27
Overview ...........................................................................................................56
Function Description..........................................................................................56
Programming the Related Registers .................................................................58
Product Specification (V1.0) 06.16.2005
Contents
6.10 Comparator ...................................................................................................... 58
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
External Reference Signal ................................................................................59
Comparator Outputs..........................................................................................60
Using Comparator as an Operation Amplifier....................................................60
Comparator Interrupt .........................................................................................60
Wake-up from SLEEP Mode .............................................................................60
6.11 Oscillator .......................................................................................................... 61
6.11.1
6.11.2
6.11.3
6.11.4
Oscillator Modes................................................................................................61
Crystal Oscillator/Ceramic Resonators (XTAL) .................................................62
External RC Oscillator Mode.............................................................................63
Internal RC Oscillator Mode ..............................................................................64
6.12 Power-on Considerations ................................................................................. 65
6.12.1 Programmable WDT Time-Out Period ..............................................................65
6.12.2 External Power-on Reset Circuit .......................................................................65
6.12.3 Residual Voltage Protection ..............................................................................66
6.13 Code Option ..................................................................................................... 67
6.13.1 Code Option Register (Word 0).........................................................................67
6.13.2 Code Option Register (Word 1).........................................................................68
6.13.3 Customer ID Register (Word 2).........................................................................69
6.14 Instruction Set .................................................................................................. 69
7
8
9
10
Absolute Maximum Ratings ................................................................................... 71
DC Electrical Characteristics ................................................................................. 72
8.1
AD Converter Characteristics........................................................................... 73
8.2
Comparator (OP) Characteristics ..................................................................... 74
8.3
Device Characteristics...................................................................................... 74
AC Electrical Characteristic ................................................................................... 75
Timing Diagrams ..................................................................................................... 76
APPENDIX
A.
B
Package Types Summary ....................................................................................... 77
Packaging Configurations...................................................................................... 77
B.1 18-Lead Plastic Dual in line (PDIP) - 300 mil ................................................... 77
B.2 18-Lead Plastic Small Outline (SOP) - 300 mil ................................................ 78
B.3 20-Lead Plastic Shrink Small Outline (SSOP) - 209 mil ................................... 79
B.4 20-Lead Plastic Dual-in-line (PDIP) - 300 mil ................................................... 80
B.5 20-Lead Plastic Small Outline (SOPP) - 300 mil .............................................. 81
C
Quality Assurance and Reliability ......................................................................... 82
C.1 Address Trap Detect......................................................................................... 82
Product Specification (V1.0) 06.16.2005
•v
Contents
Specification Revision History
Doc. Version
1.0
vi •
Revision Description
Initial official version
Date
2005/06/16
Product Specification (V1.0) 06.16.2005
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
1
General Description
EM78P259N and EM78P260N are 8-bit microprocessors designed and developed with
low-power and high-speed CMOS technology. It is equipped with a 2K*13-bit Electrical
One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature,
it is able to offer a convenient way of developing and verifying your programs. Moreover,
it provides a protect bit to guard against code intrusion, as well as 3 Code Option words
to accommodate your requirements. Furthermore you can take advantage of ELAN
Writer to easily write your development code into the EM78P259N and EM78P260N.
2
Features
Operating voltage range: 2.3V~5.5V
2.5V~5.5V
base on 0°C ~ 70°C (commercial)
base on –40°C ~ 85°C (industrial)
Operating frequency range (base on 2 clocks):
• Crystal mode: DC ~ 20MHz/2clks, 5V; DC ~ 8MHz/2clks, 3V
• RC mode: DC ~ 4MHz/2clks, 5V; DC ~ 4MHz/2clks, 3V
Low power consumption:
• Less than 1.9 mA at 5V/4MHz
• Typically 15 µA, at 3V/32kHz
• Typically 1 µA, during sleep mode
Built-in RC oscillator 4MHz, 8MHz,1MHz, 455kHz (auto calibration)
Programmable WDT time (4.5ms:18ms)
Independent Programmable prescaler of WDT
One configuration register to match your requirements, and user’s ID code for
customer use is provided
80× 8 on chip registers (SRAM, general purpose register)
2K × 13 on-chip ROM
Bi-directional I/O ports
8-level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
8-bit real time clock/counter (TCCA, TCCC) and 16-bit real time clock/counter
(TCCB) with selective signal sources, trigger edges, and overflow interrupt
One pair of comparators (can act as an OP)
4-bit multi-channel Analog-to-Digital Converter with 12-bit resolution
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
•1
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Easily-implemented IR (Infrared remote control) application circuit
Power down (SLEEP) mode
Six interrupt sources:
•
•
•
•
•
•
TCC, TCCA, TCCB, and TCCC overflow interrupt
Input-port status change interrupt (wake-up from sleep mode)
External interrupt
Comparators status change interrupt
IR/PWM interrupt
ADC completion interrupt
Programmable free running watchdog timer
8 programmable pull-high I/O pins
8 programmable open-drain I/O pins
8 programmable pull-down I/O pins.
Two or Four clocks per instruction cycle
Package types:
•
•
•
•
•
18-pin DIP 300mil
: EM78P259NP
18-pin SOP 300mil : EM78P259NM
20-pin DIP 300mil
: EM78P260NP
20-pin SOP 300mil : EM78P260NM
20-pin SSOP 209mil : EM78P260NKM
Power-on voltage detector available (2.0V± 0.1V)
3
Pin Configuration (Package)
3.1
EM78P259NP/M Pin Assignment
1
18
P51/ADC1
P53/ADC3
2
17
P50/ADC0
P54/TCC/VREF
3
16
P55/OSCI
/RESET
4
15
P70/OSCO
Vss
5
14
VDD
P60//INT
6
13
P67/IR OUT
P61/TCCA
7
12
P66/CIN-
P62/TCCB
8
11
P65/CIN+
P63/TCCC
9
10
P64/CO
EM78P259NP
EM78P259NM
P52/ADC2
Fig. 3-1 Pin Assignment – EM78P259NP/M
2•
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
3.2
EM78P260NP/M/KM Pin Assignment
1
20
P57
P52/ADC2
2
19
P51/ADC1
P53/ADC3
3
18
P50/ADC0
P54/TCC/VREF
4
17
P55/OSCI
/RESET
5
16
P70/OSCO
Vss
6
15
VDD
P60//INT
7
14
P67/IR OUT
P61/TCCA
8
13
P66/CIN-
P62/TCCB
9
12
P65/CIN+
P63/TCCC
10
11
P64/CO
EM78P260N
P56
Fig. 3-2 Pin Assignment – EM78P260NP/M/KM
4 Functional Block Diagram
OSCI
TCC
WDT timer
OSCO /RESET
ROM
/INT
STACK 0
R2
STACK 1
STACK 2
STACK 3
Oscillator Timing
STACK 4
Control
Prescaler
STACK 5
Interrupt
Controller
Instruction
STACK 6
Register
STACK 7
RAM
Built-in
OSC
ALU
R1 (TCC)
Instruction
Decoder
R4
R3
ACC
DATA & CONTROL BUS
ADC0/P50
ADC1/P51
ADC2/P52
ADC3/P53
VREF/TCC/P54
OSCI/P55
P56
P57
I/O
PORT5
IOC5
R5
COUNTER
IOC6/7
I/O
PORT6/7
R6/7
P60/INT
P61/TCCA
P62/TCCB
P63/TCCC
P64/CO
P65/CIN+
P66/CINP67/IR OUT
P70/OSCO
Fig. 4-1 EM78P259N/260N Functional Block Diagram
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
•3
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
5
Pin Description
5.1
EM78P259NP/M Pin Description
Symbol
Pin No.
Type
VDD
14
–
OSCI
16
I
OSCO
15
I/O
Function
Power supply
■ XTAL type Crystal input terminal or external clock input pin
■ RC type:
RC oscillator input pin
■ XTAL type: Output terminal for crystal oscillator or external
clock input pin
■ RC type:
Clock output with a duration one instruction cycle
■ External clock signal input
P70
15
I/O
6 ~ 13
I/O
■ General-purpose I/O pin
■ Default value at power-on reset
■ General-purpose I/O pin
P60 ~ P67
■ Open drain
■ Default value at power-on reset
■ General-purpose I/O pin
P50 ~ P55
1~3
16 ~ 18
I/O
■ Pull-high/pull-down
■ Wake up from sleep mode when the status of the pin changes
■ Default value at power-on reset
12, 11
I
10
O
IR OUT
13
O
VREF
3
I
/INT
6
I
CIN–, CIN+
CO
■ “–“ → the input pin of Vin– of a comparator
■ “+” → the input pin of Vin+ of a comparator
■ Pin CO is the output of the comparator
■ Defined by IOC80 <4:3>
■ IR mode output pin. Capable of driving and sinking
current = 20mA when the output voltage drops to 0.7Vdd and
rise to 0.3Vdd at Vdd = 5V.
■ External reference voltage for ADC
■ Defined by ADCON (R9)<7>
■ External interrupt pin triggered by falling or rising edge
■ Defined by CONT <7>
TCC, TCCA,
3, 7,
TCCB, TCCC
8, 9
■ External Counter input
■ TCC defined by CONT<5>
I
■ TCCA defined by IOC80 <1>
■ TCCB defined by IOC90 <5>
■ TCCC defined by IOC90 <1>
ADC0 ~ ADC3
1, 2,
17, 18
I
■ Analog to Digital Converter
■ Defined by ADCON (R9)<1:0>
■ If it remains at logic low, the device will be reset
4•
/RESET
4
I
VSS
5
–
■ Wake-up from sleep mode when pin status changes
■ Voltage on /RESET/Vpp must not exceed Vdd during normal
mode
Ground
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
5.2
EM78P260NP/M/KM Pin Description
Symbol
Pin No.
Type
VDD
15
–
OSCI
17
I
Function
Power supply.
■ XTAL type Crystal input terminal or external clock input pin
■ RC type:
RC oscillator input pin
■ XTAL type: Output terminal for crystal oscillator or external
clock input pin
OSCO
16
I/O
P70
16
I/O
■ RC type:
Clock output with a time period of one instruction
cycle.
■ External clock signal input
■ General-purpose I/O pin
■ Default value at power-on reset
■ General-purpose I/O pin
P60 ~ P67
7 ~ 14
I/O
■ Open-drain
■ Default value at power-on reset
■ General-purpose I/O pin
P50 ~ P57
1~4
17 ~ 20
I/O
■ Pull-high/pull-down
■ Wake up from sleep mode when the status of the pin changes
■ Default value at power-on reset
CIN–, CIN+
13, 12
I
CO
11
O
IR OUT
14
O
VREF
4
I
/INT
7
I
■ “–“→ the input pin of Vin– of a comparator
■ “+”→ the input pin of Vin+ of a comparator
■ Pin CO is the output of the comparator
■ Defined by IOC80 <4:3>
■ IR mode output pin. Capable of driving and sinking
current = 20mA when the output voltage drops to 0.7Vdd and
rise to 0.3Vdd at Vdd = 5V.
■ External reference voltage for ADC
■ Defined by ADCON (R9)<7>
■ External interrupt pin triggered by falling or rising edge.
■ Defined by CONT <7>
TCC, TCCA,
4, 8,
TCCB, TCCC
9, 10
■ External Counter input
■ TCC defined by CONT<5>
I
■ TCCA defined by IOC80 <1>
■ TCCB defined by IOC90 <5>
■ TCCC defined by IOC90 <1>
ADC0 ~ ADC3
2, 3,
18, 19
I
■ Analog to Digital Converter
■ Defined by ADCON (R9)<1:0>
■ If it remains at logic low, the device will be reset
/RESET
5
I
VSS
6
–
■ Wake-up from sleep mode when pin status changes
■ Voltage on /RESET/Vpp must not exceed Vdd during normal
mode
Ground
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
•5
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6
Function Description
6.1
Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge which is defined by the TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers
The TCC prescaler counter (IOCC1) is assigned to TCC
The contents of the IOCC1 register is cleared whenever –
• a value is written to TCC register.
• a value is written to TCC prescaler bits (Bit3, 2, 1, 0 of the CONT register)
• during power on reset, /RESET, or WDT time out reset.
6.1.3 R2 (Program Counter) and Stack
R3
A10
A9 A8
A7
~
A0
Hardware Interrupt Vector
01 PAGE1 0400~07FF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
On-chip Program
000H
003H
~
01EH
3FEH
Memory
User Memory
Space
CALL
RET
RETL
RETI
00 PAGE0 0000~03FF
Reset Vector
7FFH
Fig. 5-2 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table
under Section 6.1.3.1, Data Memory Configuration (next page).
Generates 2K×13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a RESET condition occurs.
6•
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top of stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6",⋅⋅⋅⋅⋅) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain
unchanged.
In the case of EM78P259N/260N, the most significant bit (A10) will be loaded with
the content of PS0 in the status register (R3) upon execution of a "JMP", "CALL", or
any other instructions set which write to R2.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the
instructions that are written to R2. Note that these instructions need one or two
instructions cycle as determined by Code Option Register CYES bit.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
•7
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.3.1 Data Memory Configuration
Address
IOCX0 PAGE registers
IOCX1 PAGE registers
Reserve
00
R0
(Indirect Addressing Register)
01
R1
(Time Clock Counter)
02
R2
(Program Counter)
Reserve
Reserve
03
R3
(Status Register)
Reserve
Reserve
04
R4
(RAM Select Register)
Reserve
Reserve
05
R5
(Port5)
IOC50 (I/O Port Control Register)
IOC51
(TCCA Counter)
06
R6
(Port6)
IOC60 (I/O Port Control Register)
IOC61
(TCCB LSB Counter)
07
R7
(Port7)
IOC70 (I/O Port Control Register)
IOC71
(TCCB HSB Counter)
08
R8
(ADC Input Select Register
IOC81
(TCCC Counter)
09
R9
(ADC Control Register)
IOC91
(Low-Time Register)
0A
RA
IOCA1
(High-Time Register)
0B
RB
IOCB1
(High-Time and Low-Time
Scale control Register)
0C
RC
IOCC1
(TCC Prescaler Control)
0D
RD
0E
RE
(ADC Offset Calibration
Register)
(The converted value
AD11~AD4 of ADC)
(The converted value
AD11~AD8 of ADC)
(The converted value
AD7~AD0 of ADC)
(Interrupt Status 2 and
Wake-Up Control Register
0F
RF
10
︰
1F
20
：
3F
8•
R PAGE registers
(Interrupt Status Register 1)
Reserve
CONT (Control Register)
(Comparator and TCCA
Control Register)
(TCCB
and TCCC
IOC90
Control Register)
(IR and TCCC Scale
IOCA0 Control Register)
IOC80
IOCB0 (Pull-down Control
Register)
IOCC0 (Open-drain Control
Register)
Reserve
IOCD0 (Pull-high Control Register)
Reserve
IOCE0 (WDT Control Register and
Interrupt Mask Register 2)
Reserve
IOCF0 (Interrupt Mask Register 1)
Reserve
General Registers
Bank0
Bank1
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
RST
IOCS
PS0
T
P
Z
DC
C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from sleep on pin change, comparator status
change, or AD conversion completed. Set to “0” if wake-up from other
reset types
Bit 6 (IOCS): Select the Segment of IO control register
0 = Segment 0 (IOC50 ~ IOCF0) selected
1 = Segment 1 (IOC51 ~ IOCC1) selected
Bit 5 (PS0): Page select bits. PS0 is used to select a program memory page. When
executing a "JMP," "CALL," or other instructions which cause the
program counter to change (e.g., MOV R2, A), PS0 is loaded into the
11th bit of the program counter where it selects one of the available
program memory pages. Note that RET (RETL, RETI) instruction does
not change the PS0 bit. That is, the return will always be back to the
page from where the subroutine was called, regardless of the current
PS0 bit setting.
PS0
Program Memory Page [Address]
0
Page 0 [000-3FF]
1
Page 1 [400-7FF]
Bit 4 (T):
Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power on; and reset to “0” by WDT time-out (see Section 6.5.2, The T
and P Status under STATUS Register for more details).
Bit 3 (P):
Power-down bit. Set to “1” during power-on or by a "WDTC" command
and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P
Status under STATUS Register for more details).
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC):
Auxiliary carry flag
Bit 0 (C):
Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7:
Set to “0” all the time
Bit 6:
Used to select Bank 0 or Bank 1 of register
Bits 5~0:
Used to select a register (address: 00~0F, 10~3F) in the indirect
addressing mode
See the table under Section 6.1.3.1, Data Memory Configuration for data memory
configuration.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
•9
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 & R6 are I/O registers
The upper 2 bits of R5 are fixed to “0” (if EM78P259N is selected).
Only the lower 6 bits of R5 are available (this applies to EM78P259N only as
EM78P260N can use all the bits)
6.1.7 R7 (Port 7)
Bit
7
6
5
4
3
2
1
0
EM78P259N/260N
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
I/O
ICE259N
C3
C2
C1
C0
RCM1
RCM0
‘0’
I/O
NOTE
R7 is an I/O register
For EM78P259N/260N, only the lower 1 bit of R7 is available.
Bit 7 ~ Bit 2:
[With EM78P259N/260N]: Unimplemented, read as ‘0’.
[With Simulator (C3~C0, RCM1, & RCM0)]: are IRC calibration bits in IRC oscillator
mode. Under IRC oscillator mode of ICE259N simulator,
these are the IRC mode selection bits and IRC calibration bits.
Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode
C3
C2
C1
C0
Frequency (MHz)
0
0
0
0
0
0
0
1
(1-36%) x F
(1-31.5%) x F
0
0
1
0
(1-27%) x F
0
0
1
1
(1-22.5%) x F
0
1
0
0
(1-18%) x F
0
1
0
1
(1-13.5%) x F
0
0
1
1
1
1
0
1
(1-9%) x F
(1-4.5%) x F
1
1
1
1
F (default)
1
1
1
0
(1+4.5%) x F
1
1
0
1
(1+9%) x F
1
1
0
0
(1+135%) x F
1
1
0
0
1
1
1
0
(1+18%) x F
(1+22.5%) x F
1
0
0
1
(1+27%) x F
1
0
0
0
(1+31.5%) x F
1. Frequency values shown are theoretical and taken at an instance of
a high frequency mode. Hence, frequency values are shown for
reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable to low frequency mode.
10 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 3 & Bit 2 ( RCM1, RCM0): IRC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
4 (default)
1
0
8
0
1
1
0
0
455kHz
6.1.8 R8 (AISR: ADC Input Select Register)
The AISR register defines the pins of Port 5 as analog inputs or as digital I/O,
individually.
7
6
5
4
3
2
1
0
–
–
–
–
ADE3
ADE2
ADE1
ADE0
Bit 7 ~ Bit 4:
Not used
Bit 3 (ADE3 ): AD converter enable bit of P53 pin
0 = Disable ADC3, P53 acts as I/O pin
1 = Enable ADC3, acts as analog input pin
Bit 2 (ADE2 ): AD converter enable bit of P52 pin
0 = Disable ADC2, P52 acts as I/O pin
1 = Enable ADC2, acts as analog input pin
Bit 1 (ADE1 ): AD converter enable bit of P51 pin
0 = Disable ADC1, P51 acts as I/O pin
1 = Enable ADC1, acts as analog input pin
Bit 0 (ADE0 ): AD converter enable bit of P50 pin.
0 = Disable ADC0, P50 acts as I/O pin
1 = Enable ADC0, acts as analog input pin
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 11
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.9 R9 (ADCON: ADC Control Register)
7
6
5
4
3
2
1
0
VREFS
CKR1
CKR0
ADRUN
ADPD
–
ADIS1
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC
0 = The Vref of the ADC is connected to Vdd (default value), and the
P54/VREF pin carries out the function of P54
1 = The Vref of the ADC is connected to P54/VREF
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.
If P53/TCC/VREF acts as VREF analog input pin, then CONT Bit 5 “TS” must be
“0.”
The P54/TCC/VREF pin priority is as follows:
P53/TCC/VREF Pin Priority
High
Medium
Low
VREF
TCC
P54
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of oscillator clock rate of ADC
00 = 1: 4 (default value)
01 = 1: 16
10 = 1: 64
11 = 1: WDT ring oscillator frequency
CKR0:CKR1
Operation Mode
Max. Operation Frequency
00
Fsco/4
1 MHz
01
Fsco/16
4 MHz
10
Fsco/64
16MHz
11
Internal RC
–
Bit 4 (ADRUN): ADC starts to RUN.
1 = an AD conversion is started. This bit can be set by software
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
Bit 3 (ADPD):
ADC Power-down mode
1 = ADC is operating
0 = Switch off the resistor reference to save power even while the
CPU is operating
Bit 2:
12 •
Not used
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 1 ~ Bit 0 (ADIS1 ~ADIS0): Analog Input Select
00 = ADIN0/P50
01 = ADIN1/P51
10 = ADIN2/P52
11 = ADIN3/P53
These bits can only be changed when the ADIF bit (see Section
6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) and the
ADRUN bit are both LOW.
6.1.10 RA (ADOC: ADC Offset Calibration Register)
7
6
5
4
3
2
1
0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI):
Calibration enable bit for ADC offset
0 = Calibration disable
1 = Calibration enable
Bit 6 (SIGN):
Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
EM78P259N/260N
Bit 2 ~ Bit 0:
ICE259N
0
0
0
0LSB
0LSB
0
0
1
2LSB
1LSB
0
0
1
1
0
1
4LSB
6LSB
2LSB
3LSB
1
0
0
8LSB
4LSB
1
0
1
10LSB
5LSB
1
1
0
12LSB
6LSB
1
1
1
14LSB
7LSB
Unimplemented, read as ‘0’
6.1.11 RB (ADDATA: Converted Value of ADC)
7
6
5
4
3
2
1
0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RB is read only.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 13
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.12 RC (ADDATA1H: Converted Value of ADC)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RC is read only
6.1.13 RD (ADDATA1L: Converted Value of ADC)
7
6
5
4
3
2
1
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RD is read only
6.1.14
RE (Interrupt Status 2 & Wake-Up Control Register)
7
6
5
4
3
2
1
0
–
–
ADIF
CMPIF
ADWE
CMPWE
ICWE
-
NOTE
■ RE <5,4> can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 & Bit 6:
Not used
Bit 5 (ADIF):
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software
0 = no interrupt occurs
1 = interrupt request
Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 3 (ADWE):
ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
When AD Conversion enters sleep mode, this bit must be set to
“Enable“.
14 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When Comparator enters sleep mode, this bit must be set to “Enable.“
Bit 1 (ICWE):
Port 5 input change to wake-up status enable bit
0 = Disable Port 5 input change to wake-up status
1 = Enable Port 5 input change to wake-up status
When Port 5 change enters sleep mode, this bit must be set to
“Enable.“
Bit 0:
6.1.15
Not implemented, read as ‘0’
RF (Interrupt Status 2 Register)
7
6
5
4
3
2
1
0
LPWTIF
HPWTIF
TCCCIF
TCCBIF
TCCAIF
EXIF
ICIF
TCIF
NOTE
■ “1” means interrupt request; “0” means no interrupt occurs.
■ RF can be cleared by instruction but cannot be set.
■ IOCF0 is the relative interrupt mask register.
■ Reading RF will result to "logic AND" of RF and IOCF0.
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 2 (EXIF):
External interrupt flag. Set by falling edge on /INT pin. Reset by
software.
Bit 1 (ICIF):
Port 5 input status change interrupt flag. Set when Port 5 input
changes. Reset by software.
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
6.1.16 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 15
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.2
Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It cannot be addressed.
6.2.2 CONT (Control Register)
7
6
5
4
3
2
1
0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
NOTE
■ The CONT register is both readable and writable.
■ Bit 6 is read only.
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT pin
1 = interrupt occurs at the falling edge on the INT pin
Bit 6 (INT):
Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
TCC signal source
0 = internal instruction cycle clock. P54 is bi-directional I/O pin.
1 = transition on the TCC pin
Bit 4 (TE):
TCC signal edge
0 = increment if the transition from low to high takes place on the TCC
pin
1 = increment if the transition from high to low takes place on the TCC
pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1.
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
16 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
1:2
0
0
0
1
1
0
1:4
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
NOTE
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)]
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O
pin as output.
Only the lower 6 bits of IOC50 can be defined (this applies to EM78P259N only as
EM78P260N can use all the bits).
Only the lower 1 bits of IOC70 can be defined, the others bits are not available.
IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (Comparator and TCCA Control Register)
7
6
5
4
3
2
1
0
–
–
CMPOUT
COS1
COS0
TCCAEN
TCCATS
TCCATE
NOTE
■ Bits 4 ~ 0 of the IOC80 register are both readable and writable.
■ Bit5 of the IOC80 register is readable only.
Bit 7 & Bit 6:
Not used
Bit 5 (CMPOUT):
The result of the comparator output
This bit is readable only
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 17
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 4 & Bit 3 (COS1 & COS0): Comparator/OP Select bits
COS1
COS0
0
0
0
1
1
0
1
1
Bit 2 (TCCAEN):
Function Description
Comparator and OP not used. P64, P65, and P66 act as
normal I/O pin
Acts as Comparator and P64 acts as normal I/O pin
Acts as Comparator and P64 acts as Comparator output
pin (CO)
Acts as OP and P64 acts as OP output pin (CO)
TCCA enable bit
0 = disable TCCA
1 = enable TCCA as a counter
Bit 1 (TCCATS):
TCCA signal source
0 =: internal instruction cycle clock. P61 is a bi-directional I/O pin.
1 = transit through the TCCA pin
Bit 0 (TCCATE):
TCCA signal edge
0 = increment if transition from low to high takes place on the
TCCA pin
1 = increment if transition from high to low takes place on the
TCCA pin
6.2.5 IOC90 (TCCB and TCCC Control Register)
7
6
5
4
3
2
1
0
TCCBHE
TCCBEN
TCCBTS
TCCBTE
–
TCCCEN
TCCCTS
TCCCTE
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of counter
1 = Enable the most significant byte of TCCBH
TCCB is a 16-bit counter
0 = Disable the most significant byte of TCCBH (default value)
TCCB is an 8-bit counter
Bit 6 (TCCBEN): TCCB enable bit
0 = disable TCCB
1 = enable TCCB as a counter
Bit 5 (TCCBTS) TCCB signal source
0 = internal instruction cycle clock. P62 is a bi-directional I/O pin.
1 = transit through the TCCB pin
18 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 4 (TCCBTE): TCCB signal edge
0 = increment if the transition from low to high takes place on the
TCCB pin
1 = increment if the transition from high to low takes place on the
TCCB pin
Bit 3:
Not used.
Bit 2 (TCCCEN): TCCC enable bit
0 = disable TCCC
1 = enable TCCC as a counter
Bit 1 (TCCCTS) TCCC signal source
0 = internal instruction cycle clock. P63 is a bi-directional I/O pin.
1 = transit through the TCCC pin
Bit 0 (TCCCTE): TCCC signal edge
0 = increment if the transition from low to high takes place on the
TCCC pin
1 = increment if the transition from high to low takes place on the
TCCC pin
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
7
6
5
4
3
2
1
0
TCCCSE
TCCCS2
TCCCS1
TCCCS0
IRE
HF
LGP
IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC
An 8-bit counter is provided as scale for TCCC and IR-Mode. When
in IR-Mode, TCCC counter scale uses the low-time segments of the
pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description).
0 = scale disable bit, TCCC rate is 1:1
1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 19
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits
The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to
determine the scale ratio of TCCC as shown below:
Bit 3 (IRE):
TCCCS2
TCCCS1
TCCCS0
TCCC Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Infrared Remote Enable bit
0 = Disable IRE, i.e., disable H/W Modulator Function. IROUT pin
fixed to high level and the TCCC is UP Counter.
1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67
defined as IROUT. If HP=1, the TCCC counter scale uses the
low-time segments of the pulse generated by Fcarrier frequency
modulation (see Fig. 6-11 in Section 6.8.2, Function
Description). When HP=0, the TCCC is UP Counter.
Bit 2 (HF):
High Frequency bit
0 = PWM application. IROUT waveform is achieved according to
high-pulse width timer and low-pulse width timer which
determine the high time width and low time width respectively
1 = IR application mode. The low-time segments of the pulse
generated by Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description)
Bit 1 (LGP):
Long Pulse.
0 = The high-time register and low-time register is valid
1 = The high-time register is ignored. A single pulse is generated
Bit 0 (IROUTE): Control bit to define the P67 (IROUT) pin function
0 = P67 defined as bi-directional I/O pin
1 = P67 defined as IROUT. Under this condition, the I/O control bit
of P67 (Bit 7 of IOC60) must be set to “0”
20 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.2.7 IOCB0 (Pull-Down Control Register)
7
6
5
4
3
2
1
0
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
NOTE
IOCB0 register is both readable and writable
Bit 7 (/PD57): Control bit is used to enable the pull-down of the P57 pin
(applicable to EM78P260N only)
0 = Enable internal pull-down
1 = Disable internal pull-down
Bit 6 (/PD56): Control bit is used to enable the pull-down of the P56 pin
(applicable to EM78P260N only)
Bit 5 (/PD55): Control bit is used to enable the pull-down of the P55 pin
Bit 4 (/PD54): Control bit is used to enable the pull-down of the P54 pin
Bit 3 (/PD53): Control bit is used to enable the pull-down of the P53 pin
Bit 2 (/PD52): Control bit is used to enable the pull-down of the P52 pin
Bit 1 (/PD51): Control bit is used to enable the pull-down of the P51 pin
Bit 0 (/PD50): Control bit is used to enable the pull-down of the P50 pin.
6.2.8 IOCC0 (Open-Drain Control Register)
7
6
5
4
3
2
1
0
/OD67
/OD66
/OD65
/OD64
/OD63
/OD62
/OD61
/OD60
NOTE
The IOCC0 register is both readable and writable
Bit 7 (/OD67): Control bit is used to enable the open-drain of the P67 pin
0 = Enable open-drain output
1 = Disable open-drain output
Bit 6 (/OD66): Control bit is used to enable the open-drain of the P66 pin
Bit 5 (/OD65): Control bit is used to enable the open-drain of the P65 pin
Bit 4 (/OD64): Control bit is used to enable the open-drain of the P64 pin
Bit 3 (/OD63): Control bit is used to enable the open-drain of the P63 pin
Bit 2 (/OD62): Control bit is used to enable the open-drain of the P62 pin
Bit 1 (/OD61): Control bit is used to enable the open-drain of the P61 pin
Bit 0 (/OD60): Control bit is used to enable the open-drain of the P60 pin
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 21
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.2.9 IOCD0 (Pull-high Control Register)
7
6
5
4
3
2
1
0
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
NOTE
The IOCD0 register is both readable and writable
Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to
EM78P260N only).
0 = Enable internal pull-high;
1 = Disable internal pull-high.
Bit 6 (/PH56): Control bit is used to enable the pull-high of the P56 pin (applicable to
EM78P260N only).
Bit 5 (/PH55): Control bit is used to enable the pull-high of the P55 pin.
Bit 4 (/PH54): Control bit is used to enable the pull-high of the P54 pin.
Bit 3 (/PH53): Control bit is used to enable the pull-high of the P53 pin.
Bit 2 (/PH52): Control bit is used to enable the pull-high of the P52 pin.
Bit 1 (/PH51): Control bit is used to enable the pull-high of the P51 pin.
Bit 0 (/PH50): Control bit is used to enable the pull-high of the P50 pin.
6.2.10
IOCE0 (WDT Control & Interrupt Mask Registers 2)
7
6
5
4
3
2
1
0
WDTE
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable
Bit 6 (EIS):
Control bit is used to define the function of the P60 (/INT) pin
0 = P60, bi-directional I/O pin
1 = /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC60) must be set to "1"
NOTE
■ When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin
can also be read by way of reading Port 6 (R6). Refer to Fig. 6-3 (I/O Port and I/O
Control Register Circuit for P60(/INT)) under Section 6.4 (I/O Ports).
■ EIS is both readable and writable.
22 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 5 (ADIE): ADIF interrupt enable bit
0 = disable ADIF interrupt
1 = enable ADIF interrupt
Bit 4 (CMPIE): CMPIF interrupt enable bit.
0 = disable CMPIF interrupt
1 = enable CMPIF interrupt
Bit 3 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit, WDT rate is 1:1
1 = prescaler enable bit, WDT rate is set as Bit2 ~ Bit0
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
6.2.11
PSW2
PSW1
PSW0
WDT Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
IOCF0 (Interrupt Mask Register)
7
6
5
4
3
2
1
0
LPWTIE
HPWTIE
TCCCIE
TCCBIE
TCCAIE
EXIE
ICIE
TCIE
NOTE
■ The IOCF0 register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in
IOCE0 Bit 4 & 5 to "1".
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LPWTIE): LPWTIF interrupt enable bit
0 = Disable LPWTIF interrupt
1 = Enable LPWTIF interrupt
Bit 6 (HPWTIE): HPWTIF interrupt enable bit
0 = Disable HPWTIF interrupt
1 = Enable HPWTIF interrupt
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 23
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 5 (TCCCIE): TCCCIF interrupt enable bit
0 = Disable TCCCIF interrupt
1 = Enable TCCCIF interrupt
Bit 4 (TCCBIE): TCCBIF interrupt enable bit
0 = Disable TCCBIF interrupt
1 = Enable TCCBIF interrupt
Bit 3 (TCCAIE): TCCAIF interrupt enable bit
0 = Disable TCCAIF interrupt
1 = Enable TCCAIF interrupt
Bit 2 (EXIE):
EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
Bit 1 (ICIE):
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
Bit 0 (TCIE):
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any
reset condition and is an UP Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
6.2.13 IOC61 (TCCB Counter)
An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can be read,
written, and cleared on any reset condition and is an UP Counter.
24 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.2.14 IOC71 (TCCBH/MSB Counter)
An 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be
read, written, and cleared on any reset condition.
When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then
TCCB is a 16-bit length counter.
NOTE
When TCCBH is Disabled:
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1(CLK=2)]
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2(CLK=4)]
When TCCBH is Enabled:
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1(CLK=2)}
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2(CLK=4)}
6.2.15 IOC81 (TCCC Counter)
IOC81 (TCCC) is an 8-bit clock counter that can be extended to 16-bit counter. It can
be read, written, and cleared on any reset condition.
If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the
low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig.
6-11 in Section 6.8.2, Function Description). Then TCCC value will be TCCC predict
value.
When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE
Under TCCC UP Counter mode:
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)]
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, TCCC counter scale uses the low-time segments of the
pulse generated by Fcarrier frequency modulation.
NOTE
Under IR mode:
■ Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) }
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 25
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.2.16 IOC91 (Low-Time Register)
The 8-bit Low-time register controls the active or Low segment of the pulse.
The decimal value of its contents determines the number of oscillator cycles and
verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as
follows:
NOTE
■ Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } / FT
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
When an interrupt is generated by the Low time down counter underflow (when
enabled), the next instruction will be fetched from address 015H (Low time).
6.2.17
IOCA1 (High Time Register)
The 8-bit High-time register controls the inactive or High period of the pulse.
The decimal value of its contents determines the number of oscillator cycles and
verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated
as follows:
NOTE
■ High time width = {[1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } / FT
■ FT is system clock: FT=Fosc/1(CLK=2)
FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when
enabled), the next instruction will be fetched from address 012H (High time).
6.2.18
IOCB1 High/Low Time Scale Control Register)
7
6
5
4
3
2
1
0
HTSE
HTS2
HTS1
HTS0
LTSE
LTS2
LTS1
LTS0
Bit 7 (HTSE):
High-time scale enable bit.
0 = scale disable bit, High-time rate is 1:1
1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.
26 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2
HTS1
HTS0
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
0
1
0
1:16
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit 3 (LTSE):
High-time rate
Low-time scale enable bit.
0 = scale disable bit, Low-time rate is 1:1
1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0.
Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2
LTS1
LTS0
Low-time rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
0
1
0
1:16
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.2.19 IOCC1 (TCC Prescaler Counter)
TCC prescaler counter can be read and written:
Bit 1
Bit 0
TCC
Rate
-
-
V
1:2
-
V
V
1:4
V
V
V
V
V
V
V
1:8
1:16
V
V
V
V
V
1:32
V
V
V
V
V
V
1:64
V
V
V
V
V
V
1:128
V
V
V
V
V
V
1:256
PST2
PST1
PST0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
0
0
-
-
-
-
-
0
0
1
-
-
-
-
-
0
0
1
1
0
1
-
-
-
-
1
0
0
-
-
-
1
0
1
-
-
1
1
0
-
V
1
1
1
V
V
V = valid value
The TCC prescaler counter is assigned to TCC (R1).
The contents of the IOCC1 register are cleared when one of the following occurs:
a value is written to TCC register
a value is written to TCC prescaler bits (Bit 3,2,1,0 of CONT)
power on reset, /RESET
WDT time out reset
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 27
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.3
TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers that can be extended to 16-bit
counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT
register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0
bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler
counter is cleared by the instructions each time such instructions are written into TCC.
The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Fig.
6-1 (next page) depicts the block diagram of TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or
external signal input (edge selectable from the TCC pin). If TCC signal source is from
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 6-1, CLK=Fosc/2 or CLK=Fosc/4 is dependent to the CODE Option bit
<CLKS>. CLK=Fosc/2 if the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit is "1." If
TCC signal source is from external clock input, TCC will increase by 1 at every falling
edge or rising edge of the TCC pin. TCC pin input time length (kept in High or Low
level) must be greater than 1CLK.
NOTE
The internal TCC will stop running when sleep mode occurs. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is
enabled, the TCC will keep on running
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal mode
through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10
IOCE0 (WDT Control & Interrupt Mask Registers 2). With no prescaler, the WDT
time-out period is approximately 18ms1 or or 4.5ms2.
1
2
28 •
VDD=5V, WDT time-out period = 16.5ms ± 30%
VDD=3V, WDT time-out period = 18ms ± 30%
VDD=5V, WDT time-out period = 4.2ms ± 30%
VDD=3V, WDT time-out period = 4.5ms ± 30%
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
CLK (Fosc/2 or Fosc/4)
Data Bus
0
TCC Pin
1
8-Bit Counter (IOCC1)
MUX
8 to 1 MUX
TE (CONT)
Prescaler
TS (CONT)
WDT
WDTE
(IOCE0)
8-Bit counter
8 to 1 MUX
WDT Time out
SYNC
2 cycles
TCC (R1)
TCC overflow
interrupt
PSR2~0
(CONT)
Prescaler
PSW2~0
(IOCE0)
Fig. 6-1 TCC and WDT Block Diagram
6.4
I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bi-directional tri-state I/O ports. Port 5
is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain
output through software. Port 5 features an input status changed interrupt (or wake-up)
function. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable
and writable. The I/O interface circuits for Port 5, Port 6, and Port7 are illustrated in
Figures 6-2, 6-3, 6-4, & 6-5 (see next page).
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 29
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
PCRD
PORT
Q
P
R
_
Q
C
L
Q
P
R
_
Q
C
L
D
CLK
PCWR
IOD
D
CLK
PDWR
PDRD
0
1
M
U
X
NOTE: Open-drain is not shown in the figure.
Fig. 6-2 I/O Port and I/O Control Register Circuit for Port 6 and Port7
PCRD
Q P
R D
_ CLK
Q C
L
Q P
R D
_ CLK
Q C
L
PORT
Bit 6 of IOCE
D P
R Q
CLK _
C Q
L
0
1
PCWR
IOD
PDWR
M
U
X
PDRD
INT
NOTE: Open-drain is not shown in the figure.
Fig. 6-3 I/O Port and I/O Control Register Circuit for P60 (/INT)
30 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
PCRD
Q
P
R
D
_
CLK
Q
C
L
PCWR
P50 ~ P57
Q
PORT
0
P
R
IOD
D
_
CLK
Q
C
L
PDWR
M
U
X
1
PDRD
TI n
D
P
R
CLK
C
L
Q
_
Q
NOTE: Pull-high (down) is not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 50 ~ P57
I O C F.1
R F.1
TI 0
TI 1
….
TI 8
Fig. 6-5 Port 5 Block Diagram with Input Change Interrupt/Wake-up
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 31
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up
(2) Wake-up and Interrupt
(a) Before SLEEP
(a) Before SLEEP
1. Disable WDT
1. Disable WDT
2. Read I/O Port 5 (MOV R5,R5)
2. Read I/O Port 5 (MOV R5,R5)
3. Execute "ENI" or "DISI"
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE ICWE =1)
4. Enable wake-up bit (Set RE ICWE =1)
5. Execute "SLEP" instruction
5. Enable interrupt (Set IOCF0 ICIE =1)
(b) After wake-up
6. Execute "SLEP" instruction
→ Next instruction
(b) After wake-up
1. IF "ENI" → Interrupt vector (006H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 5 pin change
1. Read I/O Port 5 (MOV R5,R5)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF0 ICIE =1)
(b) After Port 5 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (006H)
2. IF "DISI" → Next instruction
6.5
RESET and Wake-up
6.5.1 RESET and Wake-up Operation
A RESET is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled).
The device is kept under RESET condition for a period of approximately 18ms3 (except
in LXT mode) after the reset is detected. When in LXT mode, the reset time is 500ms.
Two choices (18ms3 or 4.5ms4) are available for WDT-time out period. Once RESET
occurs, the following functions are performed (the initial address is 000h):
The oscillator continues running, or will be started (if under sleep mode)
The Program Counter (R2) is set to all "0"
3
4
32 •
VDD=5V, WDT Time-out period = 16.5ms ± 30%.
VDD=3V, WDT Time-out period = 18ms ± 30%.
VDD=5V, WDT Time-out period = 4.2ms ± 30%.
VDD=3V, WDT Time-out period = 4.5ms ± 30%.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared
When power is switched on, the upper 3 bits of R3 is cleared
The CONT register bits are set to all "1" except for Bit 6 (INT flag)
The IOCB0 register bits are set to all "1"
The IOCC0 register bits are set to all "1"
The IOCD0 register bits are set to all "1"
Bits 7, 5, and 4 of IOCE0 register is cleared
Bit 5 and 4 of RE register is cleared
RF and IOCF0 registers are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode. While
entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped.
The WDT (if enabled) is cleared but keeps on running.
During AD conversion, when “SLEP” instruction I set; the Oscillator, TCC, TCCA,
TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on
running.
The controller can be awakened by:
Case 1
External reset input on /RESET pin
Case 2
WDT time-out (if enabled)
Case 3
Port 5 input status changes (if ICWE is enabled)
Case 4
Comparator output status changes (if CMPWE is enabled)
Case 5
AD conversion completed (if ADWE enable)
The first two cases (1 & 2) will cause the EM78P260N to reset. The T and P flags of R3
can be used to determine the source of the reset (wake-up). Cases 3, 4, & 5 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from address 0x06 (Case 3), 0x0F (Case 4), and 0x0C (Case 5) after wake-up.
If DISI is executed before SLEP, the execution will restart from the instruction next to
SLEP after wake-up.
Only one of Cases 1 to 5 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P259N/260N can be awakened only with Case 1 or Case 2. Refer to
the section on Interrupt (Section 6.6 below) for further details.
Case [b] If Port 5 Input Status Change is used to wake -up EM78P259N/260N and the
ICWE bit of RE register is enabled before SLEP, WDT must be disabled.
Hence, the EM78P259N/260N can be awakened only with Case 3. Wake-up
time is dependent on oscillator mode. Under RC mode the reset time is 32
clocks (for oscillator stables). In High XTAL mode, reset time is 2ms and
32clocks (for oscillator stables) ; and in low XTAL mode, the reset time is
500ms.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 33
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Case [c] If Comparator output status change is used to wake-up the EM78P259N/
260N and CMPWE bit of the RE register is enabled before SLEP, WDT must
be disabled by software. Hence, the EM78P259N/260N can be awakened
only with Case 4. Wake-up time is dependent on oscillator mode. Under RC
mode the reset time is 32 clocks (for oscillator stables). In High XTAL mode,
reset time is 2ms and 32clocks (for oscillator stables); and in low XTAL mode,
the reset time is 500ms.
Case [d] If AD conversion completed is used to wake-up the EM78P259N/260N and
ADWE bit of RE register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P259N/260N can be awakened only with Case 5.
The wake-up time is 15 TAD (ADC clock period).
If Port 5 Input Status Change Interrupt is used to wake up the EM78P259N/260N (as in
Case [b] above), the following instructions must be executed before SLEP:
BC
R3, 7
MOV
A, @00xx1110b
IOW
IOCE0
WDTC
MOV
R5, R5
ENI (or DISI)
MOV
A, @xxxxxx1xb
MOV
RE
MOV
A, @xxxxxx1xb
IOW
IOCF0
SLEP
; Select Segment 0
; Select WDT prescaler and Disable WDT
;
;
;
;
Clear WDT and prescaler
Read Port 5
Enable (or disable) global interrupt
Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt
; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P259N/260N (as in
Case [c] above), the following instructions must be executed before SLEP:
BC
MOV
R3, 7
A, @xxx10XXXb
IOW
MOV
IOC80
A, @00x11110b
IOW
IOCE0
WDTC
ENI (or DISI)
MOV
A, @xxx0x1xxb
MOV
SLEP
34 •
; Select Segment 0
; Select a comparator and P64 act as CO
pin
; Select WDT prescaler and Disable WDT,
and enable comparator output status
change interrupt
; Clear WDT and prescaler
; Enable (or disable) global interrupt
; Enable comparator output status change
wake-up bit
RE
; Sleep
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.5.1.1 Wake-Up and Interrupt Modes Operation Summary
All categories under Wake-up and Interrupt modes are summarized below.
Signal
Sleep Mode
Normal Mode
DISI + IOCF0 (EXIE) bit2=1
INT Pin
N/A
Next Instruction + Set RF (EXIF)=1
ENI + IOCF0 (EXIE) bit2=1
Interrupt Vector (003H) + Set RF (EXIF)=1
RE (ICWE) bit1=0, IOCF0 (ICIE) bit1=0
Oscillator, TCC, TCCX and IR/PWM are stopped.
Port5 input status changed wake-up is invalid.
IOCF0 (ICIE) bit1=0
Port5 input status change interrupted is invalid
RE (ICWE) bit1=0, IOCF0 (ICIE) bit1=1
N/A
Set RF (ICIF)=1,
N/A
Oscillator, TCC, TCCX and IR/PWM are stopped.
Port5 input status changed wake-up is invalid.
Port5 Input
Status Change
RE (ICWE) bit1=1, IOCF0 (ICIE) bit1=0
N/A
Wake-up + Next Instruction
N/A
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (ICWE) bit1=1, DISI + IOCF0 (ICIE) bit1=1
Wake-up + Next Instruction + Set RF (ICIF)=1
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (ICWE) bit1=1, ENI + IOCF0 (ICIE) bit1=1
Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1
Oscillator, TCC, TCCX and IR/PWM are stopped.
DISI + IOCF0 (ICIE) bit1=1
Next Instruction + Set RF (ICIF)=1
ENI + IOCF0 (ICIE) bit1=1
Interrupt Vector(006H)+ Set RF (ICIF)=1
DISI + IOCF0 (TCIE) bit0=1
TCC Over Flow
N/A
Next Instruction + Set RF (TCIF)=1
ENI + IOCF0 (TCIE) bit0=1
Interrupt Vector (009H) + Set RF (TCIF)=1
RE (ADWE) bit3=0, IOCE0 (ADIE) bit5=0
IOCE0 (ADIE) bit5=0
Clear R9 (ADRUN)=0, ADC is stopped,
AD conversion wake-up is invalid.
AD conversion interrupted is invalid
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (ADWE) bit3=0, IOCE0 (ADIE) bit5=1
N/A
Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped,
AD conversion wake-up is invalid.
N/A
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (ADWE) bit3=1, IOCE0 (ADIE) bit5=0
AD Conversion
N/A
Wake-up + Next Instruction,
Oscillator, TCC, TCCX and IR/PWM keep on running.
N/A
Wake-up when ADC completed.
RE (ADWE) bit3=1, DISI + IOCE0 (ADIE) bit5=1
DISI + IOCE0 (ADIE) bit5=1
Wake-up + Next Instruction + RE (ADIF)=1,
Oscillator, TCC, TCCX and IR/PWM keep on running.
Next Instruction + RE (ADIF)=1
Wake-up when ADC completed.
RE (ADWE) bit3=1, ENI + IOCE0 (ADIE) bit5=1
ENI + IOCE0 (ADIE) bit5=1
Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1,
Oscillator, TCC, TCCX and IR/PWM keep on running.
Interrupt Vector (00CH) + Set RE (ADIF)=1
Wake-up when ADC completed.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 35
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
RE (CMPWE) bit2=0, IOCE0 (CMPIE) bit4=0
Comparator output status changed wake-up is
invalid.
Oscillator, TCC, TCCX and IR/PWM are stopped.
IOCF0 (CMPIE) bit4=0
Comparator output status change interrupted is
invalid.
RE (CMPWE) bit2=0, IOCE0 (CMPIE) bit4=1
N/A
Set RE (CMPIF)=1,
Comparator output status changed wake-up is
invalid.
Comparator
(Comparator Output
Status Change)
N/A
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (CMPWE) bit2=1, IOCE0 (CMPIE) bit4=0
N/A
Wake-up + Next Instruction,
N/A
Oscillator, TCC, TCCX and IR/PWM are stopped.
RE (CMPWE) bit2=1, DISI + IOCE0 (CMPIE)
bit4=1
Wake-up + Next Instruction + Set RE (CMPIF)=1,
Oscillator, TCC, TCCX and IR/PWM are stopped.
DISI + IOCE0 (CMPIE) bit4=1
Next Instruction + Set RE (CMPIF)=1
RE (CMPWE) bit2=1, ENI + IOCE0 (CMPIE) bit4=1 ENI + IOCE0 (CMPIE) bit4=1
Wake-up + Interrupt Vector (00FH) + Set RE
(CMPIF)=1,Oscillator, TCC, TCCX and IR/PWM
are stopped.
Interrupt Vector (00FH) + Set RE (CMPIF)=1
DISI + IOCF0 (HPWTIF) bit6=1
IR/PWM underflow
interrupt
N/A
Next Instruction + Set RF (HPWTIE)=1
(High-pulse width timer
underflow interrupt)
ENI + IOCF0 (HPWTIF) bit6 =1
IR/PWM underflow
DISI + IOCF0 (LPWTIF) bit7=1
Interrupt Vector (012H) + Set RF (HPWTIE)=1
interrupt
N/A
(Low-pulse width timer
underflow interrupt)
Next Instruction + Set RF (LPWTIE)=1
ENI + IOCF0 (LPWTIF) bit7 =1
Interrupt Vector (015H) + Set RF (LPWTIE)=1
DISI + IOCF0 (TCCAIE) bit3=1
TCCA Over Flow
N/A
Next Instruction + Set RF (TCCAIF)=1
ENI + IOCF0 (TCCAIE) bit3=1
Interrupt Vector (018H) + Set RF (TCCAIF)=1
DISI + IOCF0 (TCCBIE) bit4=1
TCCB Over Flow
N/A
Next Instruction + Set RF (TCCBIF)=1
ENI + IOCF0 (TCCBIE) bit4=1
Interrupt Vector (01BH) + Set RF (TCCBIF)=1
DISI + IOCF0 (TCCCIE) bit5=1
TCCC Over Flow
N/A
Next Instruction + Set RF (TCCCIF)=1
ENI + IOCF0 (TCCCIE) bit5=1
Interrupt Vector (01EH) + Set RF (TCCCIF)=1
WDT Time Out
IOCE (WDTE) bit7=1
36 •
Wake-up + Reset (address 0x00)
Reset (address 0x00)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.5.1.2 Register Initial Values after Reset
The following summarizes the initialized values for registers.
Address
Name
Reset Type
Bit Name
Type
N/A
N/A
N/A
N/A
IOC50
IOC60
IOC70
IOC80
IOC90
N/A
N/A
IOCA0
(IR CR)
IOCB0
(PDCR)
IOCC0
(ODCR)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C57
C56
C55
C54
C53
C52
C51
C50
–
–
–
–
–
–
259 260 259 260
N
N
N
N
0
1
0
1
1
1
1
1
1
1
/RESET and WDT
0
1
0
1
1
1
1
1
1
1
Wake-Up from Pin
Change
0
P
0
P
P
P
P
P
P
P
Bit Name
C67
C66
C65
C64
C63
C62
C61
C60
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
X
X
X
X
X
X
X
C70
Power-On
0
0
0
0
0
0
0
1
/RESET and WDT
0
0
0
0
0
0
0
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
X
X
CMPOUT
COS1
COS0
TCCAEN TCCATS TCCATE
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
TCCBHE TCCBEN TCCBTS TCCBTE
X
TCCCEN TCCCTS TCCCTE
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
IRE
HF
LGP
IROUTE
Bit Name
N/A
Bit 6
Power-On
Bit Name
N/A
Bit 7
TCCCSE TCCCS2 TCCCS1 TCCCS0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/OD67
/OD66
/OD65
/OD64
/OD63
/OD62
/OD61
/OD60
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 37
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Address
N/A
N/A
Name
IOCD0
(PHCR)
IOCE0
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
WDTC
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
EXIE
ICIE
TCIE
Bit Name
N/A
N/A
N/A
IOCF0
IOC51
(TCCA)
IOC61
(TCCB)
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TCCA7
TCCA6
TCCA5
TCCA4
TCCA3
TCCA2
TCCA1
TCCA0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TCCB7
TCCB6
TCCB5
TCCB4
TCCB3
TCCB2
TCCB1
TCCB0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
N/A
N/A
N/A
38 •
IOC71
(TCCBH)
IOC81
(TCCC)
IOC91
(LTR)
LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE
TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TCCC7
TCCC6
TCCC5
TCCC4
TCCC3
TCCC2
TCCC1
TCCC0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
LTR7
LTR6
LTR5
LTR4
LTR3
LTR2
LTR1
LTR0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name
N/A
N/A
IOCA1
(HTR)
IOCB1
(HLTS)
N/A
0x00
0x01
0x02
IOCC1
(TCCPC)
CONT
R0(IAR)
R1(TCC)
R2(PC)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HTR7
HTR6
HTR5
HTR4
HTR3
HTR2
HTR1
HTR0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HTSE
HTS2
HTS1
HTS0
LTSE
LTS2
LTS1
LTS0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
N/A
Bit 7
TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1 TCCPC0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Power-On
1
0
1
1
0
0
0
0
/RESET and WDT
1
0
1
1
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
00
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
0x03
R3(SR)
Jump to address 0x06 or continue to execute next instruction
Bit Name
RST
IOCS
PS0
T
P
Z
DC
C
Power-On
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
T
t
P
P
P
Wake-Up from Pin
Change
P
P
P
T
t
P
P
P
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 39
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Address
0x04
0x05
0x06
0x7
0x8
0x9
0xA
Name
R4(RSR)
R5
R6
R7
R8
(AISR)
R9
(ADCON)
RA
(ADOC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Reset Type
X
BS
X
X
X
X
X
X
Power-On
0
0
U
U
U
U
U
U
/RESET and WDT
0
0
P
P
P
P
P
P
Wake-Up from Pin
Change
0
P
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
P70
Power-On
0
0
0
0
0
0
0
1
/RESET and WDT
0
0
0
0
0
0
0
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
ADE3
ADE2
ADE1
ADE0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
0
0
0
0
P
P
P
P
Bit Name
VREFS
CKR1
CKR0
ADRUN
ADPD
–
ADIS1
ADIS0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
0
P
P
Bit Name
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
–
–
–
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
Bit Name
0XB
40 •
RB
Power-On
(ADDATA) /RESET and WDT
Wake-Up from Pin
Change
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Address
0XC
Name
Reset Type
RC
(ADDATA1H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
Power-On
0
0
0
0
U
U
U
U
/RESET and WDT
0
0
0
0
U
U
U
U
Wake-Up from Pin
Change
0
0
0
0
P
P
P
P
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Bit Name
0XD
0xE
Power-On
RD
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
Bit Name
–-
–
ADIF
CMPIF
ADWE
CMPWE
ICWE
–
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
EXIF
ICIF
TCIF
(ADDATA1L0) /RESET and WDT
Wake-Up from Pin
Change
RE
(ISR2)
Bit Name
0xF
0x10~0x3F
RF
(ISR1)
R10~R3F
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Legend: X: not used
P: previous value before reset
U: unknown or don’t care.
t: check table under Section 6.5.2
6.5.1.3 Controller Reset Block Diagram
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-On Reset
Voltage Detector
ENWDTB
WDT Timeout
WDT
Setup time
Reset
/RESET
Fig. 6-6 Controller Reset Block Diagram
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 41
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.5.2 The T and P Status under STATUS (R3) Register
A RESET condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled).
The values of RST, T, and P as listed in the table below, are used to check how the
processor wakes up.
Reset Type
RST
T
P
Power-on
0
1
1
/RESET during Operating mode
0
*P
*P
/RESET wake-up during SLEEP mode
WDT during Operating mode
0
0
1
0
0
1
WDT wake-up during SLEEP mode
0
0
0
Wake-up on pin change during SLEEP mode
1
1
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
RST
T
P
Power-on
0
1
1
WDTC instruction
*P
1
1
WDT time-out
0
0
*P
SLEP instruction
*P
1
0
Wake-up on pin changed during SLEEP mode
1
1
0
*P: Previous value before reset
6.6
Interrupt
The EM78P259N/260N has six interrupts as listed below:
1. TCC, TCCA, TCCB, TCCC overflow interrupt
2. Port 5 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin]
4. Analog to Digital conversion completed
5. IR/PWM underflow interrupt
6. When the comparators status changes
Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV
R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The
Port 5 Input Status Change Interrupt will wake-up the EM78P259N/260N from the
sleep mode if it is enabled prior to going into the sleep mode by executing SLEP
instruction. When wake-up occurs, the controller will continue to execute program
in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to
the interrupt vector 006H.
42 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
External interrupt equipped with digital noise rejection circuit (input pulse less than 8
system clocks time) is eliminated as noise. However, under Low XTAL oscillator (LXT)
mode the noise rejection circuit will be disabled. Edge selection is possible with INTE
of CONT. When an interrupt is generated by the External interrupt (when enabled), the
next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8
(Section 6.14.2, Code Option Register (Word1)) for digital noise rejection definition
RF and RE are the interrupt status register that records the interrupt requests in the
relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of
the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0
(refer to figure below). The RETI instruction ends the interrupt routine and enables the
global interrupt (the ENI execution).
When an interrupt is generated by the Timer clock/counter (when enabled), the next
instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB,
and TCCC respectively).
When an interrupt generated by the AD conversion is completed (when enabled), the
next instruction will be fetched from Address 00CH.
When an interrupt is generated by the High time / Low time down counter underflow
(when enabled), the next instruction will be fetched from Address 012 and 015H (High
time and Low time respectively).
When an interrupt is generated by the Comparators (when enabled), the next
instruction will be fetched from Address) 00FH (Comparator interrupt).
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After the interrupt service routine is completed,
the ACC, R3, and R4 registers are restored.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 43
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
VCC
P
R
CLK
C
L
RF
D
/IRQn
Q
IRQn
INT
_
Q
IRQm
RFRD
ENI/DISI
P
R
Q
IOCF
_
Q
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 6.7 Interrupt Input Circuit
Interrupt sources
ACC
Interrupt
occurs
STACKACC
ENI/DISI
R3
RETI
R4
STACKR3
STACKR4
Fig. 6.8 Interrupt Backup Diagram
In EM78P259N/260N, each individual interrupt source has its own interrupt vector as
depicted in the table below.
Interrupt Vector
Interrupt Status
Priority*
003H
External interrupt
1
006H
Port 5 pin change
2
009H
TCC overflow interrupt
3
00CH
AD conversion complete interrupt
4
00FH
Comparator interrupt
5
012H
High-pulse width timer underflow interrupt
6
015H
Low-pulse width timer underflow interrupt
7
018H
TCCA overflow interrupt
8
01BH
TCCB overflow interrupt
9
01EH
TCCC overflow interrupt
10
*Priority: 1 = highest ; 10 = lowest priority
44 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.7
Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control
registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB,
ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the
functional block diagram below. The analog reference voltage (Vref) and the analog
ground are connected via separate input pins.
The ADC module utilizes successive approximation to convert the unknown analog
signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and
ADDATA1L. Input channels are selected by the analog input multiplexer via the
ADCON register Bits ADIS1 and ADIS0.
Vref
h
c
t
i
w
S
g
o
l
a
n
A
1
8
ADC3
ADC2
ADC1
ADC0
Power-Down
ADC
( successive approximation )
Start to Convert
Fsco
4-1
MUX
Internal RC
7 ~ 0
AISR
1
0
ADCON
6
3
5
ADCON
11 10
RF
9
8
ADDATA1H
7
6
4
5
3
2
0
1
4
3
ADCON
ADDATA1L
DATA BUS
Fig. 6-9 Analog-to-Digital Conversion Functional Block Diagram
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1 R8 (AISR: ADC Input Select Register)
7
6
5
4
3
2
1
0
–
–
–
–
ADE3
ADE2
ADE1
ADE0
AISR register defines the Port 5 pins as analog inputs or as digital I/O, individually.
Bit 7 ~ 4:
Not used
Bit 3 (ADE3 ): AD converter enable bit of P53 pin
0 = Disable ADC3, P53 acts as I/O pin
1 = Enable ADC3 acts as analog input pin
Bit 2 (ADE2 ): AD converter enable bit of P52 pin
0 = Disable ADC2, P53 acts as I/O pin
1 = Enable ADC2 acts as analog input pin
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 45
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 1 (ADE1 ): AD converter enable bit of P51 pin
0 = Disable ADC1, P51 acts as I/O pin
1 = Enable ADC1 acts as analog input pin
Bit 0 (ADE0 ): AD converter enable bit of P50 pin
0 = Disable ADC0, P50 acts as I/O pin
1 = Enable ADC0 acts as analog input pin
6.7.1.2 R9 (ADCON: AD Control Register)
7
6
5
4
3
2
1
0
VREFS
CKR1
CKR0
ADRUN
ADPD
-
ADIS1
ADIS0
ADCON register controls the operation of the AD conversion and decides which pin
should be currently active.
Bit 7(VREFS): The input source of the ADC Vref
0 = The ADC Vref is connected to Vdd (default value), and the
P54/VREF pin carries out the P54 function
1 = The ADC Vref is connected to P54/VREF
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. IF
P54/TCC/VREF acts as VREF analog input pin, then CONT Bit 5 (TS) must be “0”.
The P54/TCC/VREF pin priority is as follows:
P54/TCC/VREF Pin Priority
High
Medium
Low
VREF
TCC
P54
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The ADC prescaler oscillator clock rate
00 = 1: 4 (default value)
01 = 1: 16
10 = 1: 64
11 = 1: WDT ring oscillator frequency
CKR0:CKR1 Operation Mode Max. Operation Frequency
46 •
00
Fsco/4
1 MHz
01
Fsco/16
4 MHz
10
Fsco/64
16MHz
11
Internal RC
–
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 4 (ADRUN):
ADC starts to RUN.
1 = an AD conversion is started. This bit can be set by
software.
0 = reset on completion of the conversion. This bit
cannot be reset though software.
Bit 3 (ADPD):
ADC Power-down mode.
1 = ADC is operating
0 = switch off the resistor reference to save power even
while the CPU is operating.
Bit 2:
Not used
Bit 1 ~ Bit 0 (ADIS1 ~ ADIS0): Analog Input Select
00 = ADIN0/P50
01 = ADIN1/P51
10 = ADIN2/P52
11 = ADIN3/P53
These bits can only be changed when the ADIF bit and
the ADRUN bit are both LOW.
6.7.1.3 RA (ADOC: AD Offset Calibration Register)
7
6
5
4
3
2
1
0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
–
–
–
Bit 7 (CALI): Calibration enable bit for ADC offset
0 = Calibration disable
1 = Calibration enable
Bit 6 (SIGN): Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits.
VOF[2]
VOF[1]
VOF[0]
EM78P259N/260N
ICE259N
0
0
0
0LSB
0LSB
0
0
1
2LSB
1LSB
0
1
0
4LSB
2LSB
0
1
1
6LSB
3LSB
1
1
0
0
0
1
8LSB
10LSB
4LSB
5LSB
1
1
0
12LSB
6LSB
1
1
1
14LSB
7LSB
Bit 2 ~ Bit 0: Unimplemented, read as ‘0’.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 47
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC,
ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H
and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are
dependent on the properties of the ADC and the comparator. The source impedance
and the internal sampling impedance directly affect the time required to charge the
sample holding capacitor. The application program controls the length of the sample
time to meet the specified accuracy. Generally speaking, the program should wait for
2µs for each KΩ of the analog source impedance and at least 2µs for the
low-impedance source. The maximum recommended impedance for analog source is
10KΩ at Vdd=5V. After the analog input channel is selected, this acquisition time must
be done before the conversion is started.
6.7.4 AD Conversion Time
CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This
allows the MCU to run at a maximum frequency without sacrificing the AD conversion
accuracy. For the EM78P259N/260N, the conversion time per bit is about 4µs. The
table below shows the relationship between Tct and the maximum operating
frequencies.
CKR0:CKR1 Operation Mode
Max. Operation
Frequency
Max. Conversion
Rate/Bit
Max. Conversion Rate
00
Fsco/4
1 MHz
250kHz (4us)
15*4us=60us(16.7kHz)
01
Fsco/16
4MHz
250kHz (4us)
15*4us=60us(16.7kHz)
10
Fsco/64
16MHz
250kHz( 4us)
15*4us=60us(16.7kHz)
11
Internal RC
–
14Kkz (71us)
15*71us=1065us(0.938kHz)
NOTE
■ Pin not used as an analog input pin can be used as a regular input or output pin.
■ During conversion, do not perform output instruction to maintain precision for all of
the pins.
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA,
TCCB, TCCC and AD conversion.
The AD Conversion is considered completed as determined by:
1. ADRUN bit of R9 register is cleared (“0” value).
2. ADIF bit of RE register is set to “1”.
48 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
3. ADWE bit of the RE register is set to “1.” Wake-up from ADC conversion (where it
remains in operation during sleep mode).
4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the
“DISI” instruction is executed.
5. Wake-up and enters into Interrupt vector (address 0x00C) if ADIE bit of IOCE0 is
enabled and the “ENI” instruction is executed.
6. Enters into Interrupt vector (address 0x00C) if ADIE bit of IOCE0 is enabled and the
“ENI” instruction is executed.
The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the
conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise,
the AD conversion will be shut off, no matter what the status of ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1 Programming Process
Follow these steps to obtain data from the ADC:
1. Write to the four bits (ADE3:ADE0) on the R8 (AISR) register to define the
characteristics of R5 (digital I/O, analog channels, or voltage reference pin)
2. Write to the R9/ADCON register to configure the AD module:
a) Select the ADC input channel (ADIS1:ADIS0)
b) Define the AD conversion clock rate (CKR1:CKR0)
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to 1 to begin sampling
3. Set the ADWE bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
6. Set the ADRUN bit to 1
7. Write “SLEP” instruction or Polling.
8. Wait for wake-up, ADRUN bit is cleared (“0” value), interrupt flag (ADIF) to be set
“1,” or the ADC interrupt to occur.
9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the
ADC input channel changes at this time, the ADDATA, ADDATA1H, and
ADDATA1L values can be cleared to ‘0’.
10. Clear the interrupt flag bit (ADIF)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 49
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
11. For the next conversion, go to Step 1 or Step 2 as required. At least 2 Tct is
required before the next acquisition starts.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition
on the I/O pins during AD conversion.
6.7.6.2 Sample Demo Programs
A. Define a General Register
R_0 == 0
PSW == 3
PORT5 == 5
PORT6 == 6
R_E== 0XE
; Indirect addressing register
; Status register
; Interrupt status register
B. Define a Control Register
IOC50 == 0X5
IOC60 == 0X6
C_INT== 0XF
; Control Register of Port 5
; Control Register of Port 6
; Interrupt Control Register
C. ADC Control Register
ADDATA == 0xB
AISR == 0x08
ADCON == 0x9
; The contents are the results of ADC
; ADC input select register
; 7
6
5
4
3
2
1
0
; VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
E. Program Starts
ORG 0
JMP INITIAL
; Initial address
;
ORG 0x0C
; Interrupt vector
JMP CLRRE
;
;
;(User program section)
;
;
CLRRE:
MOV A,RE
AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application
MOV RE,A
BS ADCON, ADRUN
; To start to execute the next AD conversion
if necessary
RETI
INITIAL:
50 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
MOV A,@0B00000001
MOV AISR,A
MOV A,@0B00001000
MOV ADCON,A
; To define P50 as an analog input
; To select P50 as an analog input channel, and
AD power on
; To define P50 as an input pin and set clock
rate at fosc/16
En_ADC:
MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others
IOW PORT5
; are dependent on applications
MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X”
by application
MOV RE,A
MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC,
“X” by application
IOW C_INT
ENI
; Enable the interrupt function
BS ADCON, ADRUN
; Start to run the ADC
; If the interrupt function is employed, the following three lines
may be ignored
;If Sleep:
SLEP
;
;(User program section)
;
or
;If Polling:
POLLING:
JBC ADCON, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
is completed
;
;(User program section)
;
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 51
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.8
Infrared Remote Control Application/PWM Waveform
Generation
6.8.1 Overview
This LSI can easily output infrared carrier or PWM standard waveform. As illustrated
below, the IR and PWM waveform generation function include an 8-bit down count
timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is
determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate,
low-time rate control register), IOC81 (TCCC counter), IOCA1 (high-time register), and
IOC91 (low-time register).
FT:CLK(Fosc)
8 Bit counter
8 Bit counter
8-to-1 MUX
8-to-1 MUX
8bit binary
down counter
8bit binary
down counter
8 Bit counter
Scale
(IOCA0)
Scale
(IOCB1)
Scale
(IOCB1)
8-to-1 MUX
Auto-reload buffer
(High-time)(IOCA1)
8
8
Fcarrier
8
Auto-reload buffer
(Low-time)(IOC91)
8
8bit binary
down counter
H/W Modulator
8
Auto-reload buffer
(TCCC)(IOC81)
HF
LG
IR
IROUT
Underflow Interrupt
HPWTIF
LPWTIF
Fig. 6-10 IR/PWM System Block Diagram
NOTE
Details of the Fcarrier high time width and low time width are explained below:
Fcarrier =
FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC
Scale(IOCA0) }
High time width = { [1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } /
FT
Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } /
FT
Where FT is the system clock FT=Fosc/1(CLK=2)
FT=Fosc/2(CLK=4)
52 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
When an interrupt is generated by the High time down counter underflow (when
enabled), the next instruction will be fetched from address 018 and 01BH (High time
and Low time respectively).
6.8.2 Function Description
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the
Fcarrier waveform at low-time segments of the pulse.
Fcarrier
low time width high time width
HF
low time width
high time width
start
IRE
IROUT
Fig. 6-11a LGP=0, HF=1, IROUT Pin Output Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate
the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is
determined by the high time width and low time width instead. This mode can produce
standard PWM waveform
Fcarrier
low time width
high time width
low time width
high time width
HF
start
IRE
IROUT
Fig. 6-11b LGP=0, HF=0, IROUT Pin Output Waveform
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 53
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the
Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high,
the output waveform of IROUT will keep transmitting till high-time interrupt occurs.
Fcarrier
low time width high time width low time width
HF
high time width
start
IR disable
IRE
IROUT
Always high- level
Fig. 6-11c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate
the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is
determined by high time width and low time width. This mode can produce standard
PWM waveform when IRE goes low from high. The output waveform of IROUT will
keep on transmitting till high-time interrupt occurs.
Fcarrier
HF
low time width high time width low time width
high time width
start
IR disable
IRE
IROUT
Always high-level
Fig. 6-11d LGP=0, HF=0, When IRE goes Low from High, Irout Pin Output Waveform
54 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=1 and HF=1. When this bit is set to high level, the
high-time segment of the pulse is ignored. So, IROUT waveform output is determined
by low-time width.
Fcarrier
low time width
HF
low time width
low time width
high time width
start
IR disable
IRE
IROUT
Always high-level
Fig. 6-11e LGP=1 and HP=1, IROUT Pin Output Waveform
6.8.3
Programming the Related Registers
When defining IR/PWM, refer to the operation of the related registers as shown in the
tables below.
IR/PWM Related Control Registers
Address
Name
Bit 7
0x09
IOC90
TCCBHE
TCCBEN/0 TCCBTS/0 TCCBTE/0
/0
0
0X0A
IR CR
/IOCA0
TCCCSE
TCCCS2/0 TCCCS1/0 TCCCS0/0
/0
IRE/0
0x0F
IMR
/IOCF0
LPWTIE
HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
/0
0X0B
HLTS
/IOCB1
HTSE
/0
Bit 6
HTS2/0
Bit 5
HTS1/0
Bit 4
HTS0/0
Bit 3
Bit 2
Bit 1
Bit 0
TCCCEN/0TCCCTS/0 TCCCTE/0
HF/0
LGP/0
IROUTE/0
EXIE/0
ICIE/0
TCIE/0
LTSE/0
LTS2/0
LTS1/0
LTS0/0
Bit 3
Bit 2
Bit 1
Bit 0
EXIF/0
ICIF/0
TCIF/0
IR/PWM Related Status/Data Registers
Address
Name
Bit 7
Bit 6
Bit 5
0x0F
ISR/RF
LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
0x06
TCCC
/IOC81
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
0X09
LTR
/IOC91
LTR7/0
LTR6/0
LTR5/0
LTR4/0
LTR3/0
LTR2/0
LTR1/0
LTR0/0
0X0A
HTR
/IOCA1
HTR7/0
HTR6/0
HTR5/0
HTR4/0
HTR3/0
HTR2/0
HTR1/0
HTR0/0
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
Bit 4
• 55
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.9
Timer/Counter
6.9.1 Overview
TimerA (TCCA) is an 8-bit clock counter. TimerB (TCCB) is a 16-bit clock counter.
TimerC (TCCC) is an 8-bit clock counter that can be extended to 16-bit clock counter
with programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and
are cleared at every reset condition.
6.9.2 Function Description
Set predict value
Set predict value
Set predict value
TCCC
TCCB
TCCA
Set TCCCIF
Set TCCBIF
Set TCCAIF
Overflow
Overflow
Overflow
System clock or
External input
TCCCEN
TCCBEN
TCCAEN
System clock or
External input
8-to-1 MUX
TCCCS1 ~ TCCCS0
8 Bit
counter
System clock or
External input
Fig. 6.12 TIMER Block Diagram
Each signal and block of the above TIMER block diagram is described as follows:
TCCX: Timer A~C register. TCCX increases until it matches with zero, and then
reload the predicted value. When writing a value to TCCX, the predicted value
and TCCX value become the set value. When reading from TCCX, the value
will be the TCCX direct value. When TCCXEN is enabled, the reload of the
predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at the
same time. It is an up counter.
Under TCCA Counter (IOC51):
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on
any reset condition and is an UP Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
Under TCCB Counter (IOC61):
An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can
be read, written, and cleared on any reset condition and is an UP Counter.
56 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Under TCCBH / MSB Counter (IOC71):
An 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It
can be read, written, and cleared on any reset condition.
When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,”
then TCCB is a 16-bit length counter.
NOTE
When TCCBH is Disabled:
TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1(CLK=2)]
TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2(CLK=4)]
When TCCBH is Enabled:
TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1(CLK=2)}
TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2(CLK=4)}
Under TCCC Counter (IOC81):
IOC81 (TCCC) is an 8-bit clock counter. It can be read, written, and cleared on
any reset condition.
If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale
uses the low-time segments of the pulse generated by Fcarrier frequency
modulation (see Fig. 6-11 in Section 6.8.2, Function Description). Then the
TCCC value will be the TCCC predicted value.
When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE
Under TCCC UP Counter mode:
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)]
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, the TCCC counter scale uses the low-time
segments of the pulse generated by Fcarrier frequency modulation.
NOTE
Under IR mode:
■ Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) }
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 57
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.9.3 Programming the Related Registers
When defining TCCX, refer to the operation of its related registers as shown in the
tables below.
TCCX Related Control Registers:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x08
IOC80
0
0
CPOUT/0
COS1/0
COS0/0
TCCAEN TCCATS TCCATE
/0
/0
/0
0x09
IOC90
TCCBHE TCCBEN TCCBTS TCCBTE
/0
/0
/0
/0
0
TCCCEN TCCCTS TCCCTE
/0
/0
/0
0x0A
IR CR
/IOCA0
TCCCSE TCCCS2 TCCCS1/ TCCCS0
/0
/0
0
/0
IRE/0
0x0F
IMR
/IOCF0
LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
HF/0
LGP/0
IROUTE/0
EXIE/0
ICIE/0
TCIE/0
Bit 2
Bit 1
Bit 0
EXIF/0
ICIF/0
TCIF/0
Related TCCX Status/Data Registers:
Address
Name
Bit 7
Bit 6
0x0F
ISR/RF
LPWTF/0 HPWTF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
0x05
TCCA
/IOC51
TCCA7/0 TCCA6/0 TCCA5/0 TCCA4/0 TCCA3/0 TCCA2/0 TCCA1/0 TCCA0/0
0x06
TCCB
/IOC61
TCCB7/0 TCCB6/0 TCCB5/0 TCCB4/0 TCCB3/0 TCCB2/0 TCCB1/0 TCCB0/0
0x07
TCCBH
/IOC71
TCCBH7
/0
0x08
TCCC
/IOC81
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
TCCBH6
/0
Bit 5
Bit 4
TCCBH5
/0
Bit 3
TCCBH4
/0
TCCBH3
/0
TCCBH2
/0
TCCBH1 TCCBH0
/0
/0
6.10 Comparator
EM78P259N/260N has
one comparator which
has two analog inputs and
one output. The
comparator can be
employed to wake-up
from the sleep mode.
Figure below shows the
circuit of the comparator.
Cin CMP
+
Cin+
CO
CinCin+
Output
30mV
Fig. 6.13 Comparator Operating Mode
58 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.10.1 External Reference Signal
The analog signal that is presented at Cin– compares to the signal at Cin+. The digital
output (CO) of the comparator is adjusted accordingly by taking the following notes into
considerations:
NOTE
■ The reference signal must be between Vss and Vdd.
■ The reference voltage can be applied to either pin of the comparator.
■ Threshold detector applications may be of the same reference.
■ The comparator can operate from the same or different reference sources.
6.10.2 Comparator Outputs
The compared result is stored in the CMPOUT of IOC80.
The comparator outputs are sent to CO (P64) through programming Bit 4 &
Bit 3<COS1, COS0> of the IOC80 register to <1,0>. See table under Section 6.2.4,
IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits
function description.
The following figure shows the Comparator Output block diagram.
To C0
From OP I/O
CMRD
EN
Q
EN
D
Q
D
To CMPOUT
RESET
To CPIF
CMRD
From other
comparator
Fig. 6-14 The Output Configuration of a Comparator
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 59
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.10.3 Using a Comparator as an Operation Amplifier
The comparator can be used as an operation amplifier if a feedback resistor is
externally connected from the input to the output. In this case, the Schmitt trigger can
be disabled for power saving purposes, by setting Bit 4, Bit 3<COS1, COS0> of the
IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA
Control Registers) for Comparator/OP select bits function description.
NOTE
Under Operation Amplifier:
■ The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid.
■ The comparator interrupt is invalid.
■ The comparator wake-up is invalid.
6.10.4 Comparator Interrupt
CMPIE (IOCE0.4) must be enabled for the “ENI” instruction to take effect
Interrupt is triggered whenever a change occurs on the comparator output pin
The actual change on the pin can be determined by reading the Bit CMPOUT,
IOC80<5>.
CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software
6.10.5 Wake-up from SLEEP Mode
If the CMPWE bit of the RE register is set to “1,” the comparator remains active and
the interrupt remains functional, even under SLEEP mode.
If a mismatch occurs, the change will wake up the device from SLEEP mode.
The power consumption should be taken into consideration for the benefit of energy
conservation.
If the function is unemployed during SLEEP mode, turn off the comparator before
entering into sleep mode.
The Comparator is considered completed as determined by:
1. COS1 and COS0 bits of IOC80 register setting selects Comparator.
2. CMPIF bit of RE register is set to “1”.
3. CMPWE bit of RE register is set to “1”. Wakes-up from Comparator (where it
remains in operation during sleep mode)
4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and
the “DISI” instruction is executed.
5. Wake-up and enters into Interrupt vector (address 0x00F), if ADIE bit of IOCE0 is
enabled and the “ENI” instruction is executed
6. Enters into Interrupt vector (address 0x00F), if CMPIE bit of IOCE0 is enabled and
the “ENI” instruction is executed.
60 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.11 Oscillator
6.11.1 Oscillator Modes
The EM78P259N/260N can be operated in four different oscillator modes, such as High
XTAL oscillator mode (HXT), Low XTAL oscillator mode (LXT), External RC oscillator
mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). You can
select one of them by programming the OSC2, OCS1, and OSC0 in the CODE Option
register.
The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
Oscillator Modes
OSC2
OSC1
OSC0
1
0
0
0
1
0
0
1
0
1
0
ERC (External RC oscillator mode); P70/OSCO acts as P70
ERC (External RC oscillator mode); P70/OSCO acts as OSCO
2
IRC (Internal RC oscillator mode); P70/OSCO acts as P70
2
0
1
1
3
1
1
0
1
1
1
IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO
LXT (Low XTAL oscillator mode)
3
HXT High XTAL oscillator mode) (default)
1
Under ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code
option WORD0 Bit6 ~ Bit4.
2
Under IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code
option WORD0 Bit6 ~ Bit4.
3
Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These
pins cannot and should not be defined as normal I/O pins.
NOTE
The transient point of the system frequency between HXT and LXY is around 400kHz.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as
follows:
Conditions
Two clocks
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
VDD
Max. Freq. (MHz)
2.3
4
3.0
8
5.0
20
• 61
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.11.2 Crystal Oscillator/Ceramic Resonators (XTAL)
The EM78P259N/260N can be driven by an external clock signal through the OSCI pin
as illustrated below.
OSCI
EM78P259N
EM78P260N
OSCO
Fig. 6-15 External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 6-16 below depicts such circuit. The
same applies to the HXT mode and the LXT mode.
C1
OSCI
EM78P259N
EM78P260N
XTAL
OSCO
RS
C2
Fig. 6-16 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each
resonator has its own attribute, you should refer to the resonator specifications for the
appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut
crystal or low frequency mode.
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Frequency Mode
Ceramic Resonators
HXT
LXT
Crystal Oscillator
HXT
62 •
Frequency
C1(pF)
C2(pF)
455kHz
100~150
100~150
2.0 MHz
20~40
20~40
4.0 MHz
10~30
10~30
32.768kHz
25
15
100kHz
25
25
200kHz
25
25
455kHz
20~40
20~150
1.0 MHz
15~30
15~30
2.0 MHz
15
15
4.0 MHz
15
15
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330
330
C
OSCI
7404
7404
EM78P259N
EM78P260N
7404
XTAL
Fig. 6-17 Serial Mode Crystal/Resonator Circuit Diagram
4.7K
7404
10K
Vdd
O SC I
EM 78P259N
EM 78P260N
10K
7404
XTAL
C1
10K
C2
Fig. 6-18 Parallel Mode Crystal/Resonator Circuit Diagram
6.11.3 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
oscillator (Fig. 6-19 right) could offer you
with effective cost savings. Nevertheless,
it should be noted that the frequency of
the RC oscillator is influenced by the
supply voltage, the values of the resistor
(Rext), the capacitor (Cext), and even by
the operation temperature. Moreover, the
frequency also changes slightly from one
chip to another due to the manufacturing
process variation.
Vcc
Rext
OSCI
EM78P259N
EM78P260N
Cext
Fig. 6-19 External RC Oscillator Mode Circuit
In order to maintain a stable system frequency, the values of the Cext should be no less
than 20pF, and that of Rext should be no greater than 1MΩ. If the frequency cannot be
kept within this range, the frequency can be affected easily by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become
unstable because the NMOS cannot discharge the capacitance current correctly.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 63
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Based on the above reasons, it must be kept in mind that all supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the way the PCB is layout, have certain effect on the system frequency.
The RC Oscillator frequencies:
Cext
20 pF
100 pF
300 pF
Rext
Average Fosc 5V,25°C
Average Fosc 3V,25°C
3.3k
3.5 MHz
3.2 MHz
5.1k
2.5 MHz
2.3 MHz
10k
1.30 MHz
1.25 MHz
100k
140 KHz
140kHz
3.3k
1.27 MHz
1.21 MHz
5.1k
850kHz
820kHz
10k
450kHz
450kHz
100k
48kHz
50kHz
3.3k
560kHz
540kHz
5.1k
370kHz
360kHz
10k
196kHz
192kHz
100k
20kHz
20kHz
NOTE: 1. Measured on DIP packages
2. Design reference only
3. The frequency drift is about ±30%
6.11.4 Internal RC Oscillator Mode
EM78P259N/260N offers a versatile internal RC mode with default frequency value of
4MHz. Internal RC oscillator mode has other frequencies (1MHz, 8MHz, and 455kHz)
that can be set by CODE OPTION (WORD1), RCM1, and RCM0. The Table below
describes the EM78P259N/260N internal RC drift with voltage, temperature, and
process variation.
Internal RC Drift Rate (Ta=25℃, VDD=5V±5%, VSS=0V)
Internal
RC Frequency
Drift Rate
Temperature
(-40℃~+80℃)
Voltage
(2.3V~5.5V)
Process
Total
4MHz
±10%
±5%
±4%
±19%
8MHz
±10%
±6%
±4%
±20%
1MHz
±10%
±5%
±4%
±19%
455MHz
±10%
±5%
±4%
±19%
Theoretical values, for reference only. Actual values may vary depending on the actual process.
64 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.12 Power-On Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in steady state. The EM78P259N/260N POR voltage range is 1.9 ~ 2.1V.
Under customer application, when power is switched OFF, Vdd must drop below 1.9V
and remains at OFF state for 10µs before power can be switched ON again.
Subsequently, the EM78P259N/260N will reset and work normally. The extra external
reset circuit will work well if Vdd rises fast enough (50ms or less). However, under
critical applications, extra devices are still required to assist in solving power-on
problems.
6.12.1 Programmable WDT Time-Out Period
The Option word (WDTPS) is used to define the WDT time-out period (18ms5 or
4.5ms6). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic
resonators, the lower the operation frequency is, the longer is the required set-up time.
6.12.2 External Power-on Reset Circuit
The circuit shown in the following figure implements an external RC to produce a reset
pulse. The pulse width (time constant) should be kept long enough to allow Vdd to
reach the minimum operating voltage. This circuit is used when the power supply has a
slow power rise time. Because the current leakage from the /RESET pin is about ±5µA,
it is recommended that R should not be greater than 40 K. This way, the voltage at Pin
/RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The
“C” capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents
high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
Vdd
R
EM78P259N
EM78P260N
D
/RESET
Rin
C
Fig. 6-20 External Power-on Reset Circuit
5
VDD=5V, WDT time-out period = 16.5ms ± 30%.
VDD=3V, WDT time-out period = 18ms ± 30%.
6
VDD=5V, WDT time-out period = 4.2ms ± 30%.
VDD=3V, WDT time-out period = 4.5ms ± 30%.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 65
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.12.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but the residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Fig. 6-21 and Fig. 6-22 show how to
create a protection circuit against residual voltage.
Vdd
Vdd
EM78P259N
EM78P260N
33K
Q1
10K
/RESET
100K
1N4684
Fig. 6-21 Residual Voltage Protection Circuit 1
Vdd
Vdd
EM78P259N
EM78P260N
R1
Q1
/RESET
R3
R2
Fig. 6-22 Residual Voltage Protection Circuit 2
66 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.13 Code Option
EM78P259N/260N has two CODE option words and one Customer ID word that are
not part of the normal program memory.
Word 0
Word1
Word 2
Bit12 ~ Bit0
Bit12 ~ Bit0
Bit12 ~ Bit0
6.13.1 Code Option Register (Word 0)
WORD 0
Bit 12 Bit 11 Bit 10
–
–
–
Bit 9
Bit 8
Bit 7
TYPE
CLKS
ENWDTB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSC2 OSC1 OSC0
HLP
PR2
PR1
PR0
Bit 12 ~ 10:
Not used (reserved). These bits are set to “1” all the time
Bit 9 (TYPE):
Type selection for EM78P259N or EM78P260N
0 = EM78P260N
1 = EM78P259N (default)
Bit 8 (CLKS):
Instruction period option bit
0 = two oscillator periods
1 = four oscillator periods (default)
Refer to Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Bit 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits
Oscillator Modes
1
ERC (External RC oscillator mode); P70/OSCO acts as P70
1
ERC (External RC oscillator mode); P70/OSCO acts as OSCO
OSC2
OSC1
OSC0
0
0
0
0
0
1
2
0
1
0
2
0
1
1
3
1
1
0
1
1
1
IRC (Internal RC oscillator mode); P70/OSCO acts as P70
IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO
LXT (Low XTAL oscillator mode)
3
HXT High XTAL oscillator mode) (default)
1
Under ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code
option WORD0 Bit6 ~ Bit4.
2
Under IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code
option WORD0 Bit6 ~ Bit4.
3
Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These
pins cannot and should not be defined as normal I/O pins.
NOTE
The transient point of the system frequency between HXT and LXY is around 400kHz.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 67
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 3 (HLP):
Power consumption selection
0 = Low power consumption, applies to working frequency
at or below 4MHz
1 = High power consumption, applies to working frequency
above 4MHz
Bit 2 ~ 0 (PR2 ~ PR0):
Protect Bits
PR2 ~ PR0 are protect bits. Each protect status is as
follows:
PR2
PR1
PR0
Protect
0
0
0
Enable
0
0
1
Enable
0
1
0
Enable
0
1
1
Enable
1
0
0
Enable
1
0
1
Enable
1
1
0
Enable
1
1
1
Disable
6.13.2 Code Option Register (Word 1)
WORD 1
Bit 12 Bit 11 Bit 10
-
-
Bit 9
Bit 8
RCOUT NRHL
NRE
Bit 7
Bit 6
WDTPS CYES
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C3
C2
C1
C0
RCM1
RCM0
Bits 12 ~ 11:
Not used (reserved). These bits are set to “1” all the time
Bit 10 (RCOUT):
System clock output enable bit in IRC or ERC mode
0 = OSCO pin is open drain
1 = OSCO output system clock
Bit 9 (NRHL):
Noise rejection high/low pulses define bit. INT pin is falling edge
trigger
0 = Pulses equal to 8/fc [s] is regarded as signal
1 = Pulses equal to 32/fc [s] is regarded as signal (default)
NOTE
The noise rejection function is turned off under the LXT and sleep mode.
Bit 8 (NRE):
Noise rejection enable
0 = disable noise rejection
1 = enable noise rejection (default), but under Low XTAL oscillator
(LXT) mode, the noise rejection circuit is always disabled.
68 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 7 (WDTPS):
WDT Time-out Period Selection bit
WDT Time
Watch-Dog Time*
1
18 ms
0
4.5 ms
*Theoretical values, for reference only
Bit 6 (CYES):
Instruction cycle selection bit
0 = one instruction cycle.
1 = two instructions cycle (default)
Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode
C3, C2, C1, & C0 must be set to “1” only (auto-calibration).
Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
4
1
0
8
0
1
1
0
0
455kHz
6.13.3 Customer ID Register (Word 2)
WORD 2
Bit 12 Bit 11 Bit 10
X
X
X
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
X
X
Bit 12 ~ 0 : Customer’s ID code
6.14 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
these instructions need one or two instruction cycles as determined by Code Option
Register CYES bit.
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 69
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
The symbol "R" represents a register designator that specifies which of the registers
(including operational registers and general-purpose registers) is to be utilized by the
instruction. The symbol "b" represents a bit field designator that selects the value for
the bit located in the register "R" that is affected by the operation. The symbol "k"
represents an 8 or 10-bit constant or literal value.
The following are the EM78P259N/260N instruction set
Instruction Binary HEX Mnemonic
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
70 •
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0110
0110
0110
0110
0111
0111
0111
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
0011
0100
rrrr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
06rr
06rr
06rr
07rr
07rr
07rr
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
RRC R
RLCA R
RLC R
SWAPA R
SWAP R
JZA R
Operation
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable Interrupt
CONT → A
IOCR → A
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),R(0) → C, C → A(7)
R(n) → R(n-1),R(0) → C, C → R(7)
R(n) → A(n+1),R(7) → C, C → A(0)
R(n) → R(n+1),R(7) → C, C → R(0)
R(0-3) → A(4-7),R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
Status Affected
None
C
None
T,P
T,P
1
None
None
None
None
None
None
1
None
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Instruction Binary HEX Mnemonic
0
0
0
0
0
1
1
1
1
1
1
1
1
1
7
0111
100b
101b
110b
111b
00kk
01kk
1000
1001
1010
1011
1100
1101
1111
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
rrrr
rrrr
rrrr
rrrr
rrrr
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1Fkk
Operation
Status Affected
JZ R
R+1 → R, skip if zero
None
2
BC R,b
0 → R(b)
None
3
BS R,b
1 → R(b)
None
JBC R,b
if R(b)=0, skip
None
JBS R,b
if R(b)=1, skip
None
CALL k
PC+1 → [SP],(Page, k) → PC
None
JMP k
(Page, k) → PC
None
MOV A,k
k→A
None
OR A,k
A∨k→A
Z
AND A,k
A&k→A
Z
XOR A,k
A⊕k→A
Z
RETL k
k → A,[Top of Stack] → PC
None
SUB A,k
k-A → A
Z,C,DC
ADD A,k
k+A → A
Z,C,DC
1
This instruction is applicable to IOC50 ~ IOCF0, IOC51 ~ IOCC1 only.
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
Absolute Maximum Ratings
Items
Rating
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
Working Voltage
2.5V
to
5.5V
Working Frequency
DC
to
20MHz
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 71
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
8
DC Electrical Characteristics
(Ta=25 °C, VDD=5.0V±5%, VSS=0V)
Symbol
Parameter
XTAL: VDD to 5V
Fxt
XTAL: VDD to 3V
Condition
Min
Two cycle with two clocks
Typ
Max
Unit
DC
20
MHz
DC
8
MHz
ERC: VDD to 5V
R: 5.1KΩ, C: 100 pF
F±30%
830
F±30%
kHz
IRC: VDD to 5 V
8MHz,4MHz, 1MHz, 455kHz
F±30%
F
F±30%
Hz
IRC1
IRC:VDD to 5V
RCM0:RCM1=1:1
3.84
4.0
4.16
MHz
IRC2
IRC:VDD to 5V
RCM0:RCM1=1:0
7.68
8.0
8.32
MHz
IRC3
IRC:VDD to 5V
RCM0:RCM1=0:1
0.96
1.0
1.06
MHz
IRC4
436.8
455
473.2
kHz
IRC:VDD to 5V
RCM0:RCM1=0:0
Input High Threshold
VIHRC
Voltage (Schmitt trigger )
OSCI in RC mode
3.5
V
VILRC
Input Low Threshold
Voltage (Schmitt trigger )
OSCI in RC mode
1.5
V
IIL
Input Leakage Current for
input pins
VIN = VDD, VSS
VIH1
Input High Voltage
(Schmitt trigger )
Ports 5, 6, 7
3.75
V
VIL1
Input Low Voltage (Schmitt
Ports 5, 6, 7
trigger )
1.25
V
VIHT1
Input High Threshold
Voltage (Schmitt trigger )
/RESET
2.0
V
VILT1
Input Low Threshold
Voltage (Schmitt trigger )
/RESET
1.0
V
VIHT2
Input High Threshold
Voltage (Schmitt trigger )
TCC,INT
3.75
V
VILT2
Input Low Threshold
Voltage (Schmitt trigger )
TCC,INT
1.25
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
3.5
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
1.5
V
IOH1
Output High Voltage
(Ports 5, P60~66,P70)
VOH = VDD-0.5V
-3.7
mA
IOH2
Output High Voltage
(IR OUT (Port67))
VOH = VDD-0.5V
-10
mA
IOL1
Output Low Voltage
(Ports 5, P60~66,P70)
VOL = GND+0.5V
10
mA
IOL2
Output Low Voltage
(IR OUT (Port67))
VOL = GND+0.5V
15
mA
IPH
Pull-high current
Pull-high active, input pin at VSS
-70
-75
-80
µA
IPL
Pull-low current
Pull-low active, input pin at Vdd
35
40
45
µA
ISB1
Power down current
All input and I/O pins at VDD,
output pin floating, WDT disabled
1.0
2.0
µA
ISB2
Power down current
All input and I/O pins at VDD,
output pin floating, WDT enabled
6.0
10
µA
ICC1
Operating supply current
at two clocks (VDD to 3V)
/RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), output
pin floating, WDT disabled
15
20
µA
72 •
-1
0
1
µA
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
ICC2
Operating supply current
at two clocks (VDD to 3V)
/RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), output
pin floating, WDT enabled
15
25
µA
ICC3
Operating supply current
at two clocks
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
1.9
2.2
mA
ICC4
Operating supply current
at two clocks
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"), output
pin floating, WDT enabled
3.0
3.5
mA
NOTE:
8.1
1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical
results at 25℃. These data are for design reference only.
AD Converter Characteristics
(Vdd=2.5V to 5.5V, Vss=0V, Ta=25℃)
Symbol
VAREF
VASS
VAI
Analog reference voltage
Condition
VAREF - VASS≧2.5V
Analog input voltage
–
Min.
Typ.
Max.
Unit
2.5
–
Vdd
V
Vss
–
Vss
V
VASS
–
VAREF
V
Analog supply current
Vdd=VAREF=5.0V, VASS =0.0V
(V referenced from Vdd)
750
850
1000
uA
–10
0
+10
uA
Analog supply current
Vdd=VAREF=5.0V, VASS=0.0V
(V referenced from VREF)
500
600
820
uA
200
250
300
uA
IOP
OP current
Vdd=5.0V, OP used
Output voltage swing 0.2V to
4.8V
450
550
650
uA
RN
Resolution
Vdd=VAREF=5.0V, VASS =0.0V
10
11
–
Bits
LN
Linearity error
Vdd = 2.5 to 5.5V Ta=25℃
0
±4
±8
LSB
DNL
Differential nonlinear error
Vdd = 2.5 to 5.5V Ta=25℃
0
±0.5
±0.9
LSB
FSE
Full scale error
Vdd=VAREF=5.0V, VASS =0.0V
±0
±4
±8
LSB
OE
Offset error
Vdd=VAREF=5.0V, VASS =0.0V
±0
±2
±4
LSB
ZAI
Recommended impedance of
analog voltage source
0
8
10
KΩ
TAD
ADC clock period
Vdd=VAREF=5.0V, VASS =0.0V
4
–
–
us
TCN
AD conversion time
Vdd=VAREF=5.0V, VASS =0.0V
15
–
15
TAD
ADIV
ADC OP input voltage range
Vdd=VAREF=5.0V, VASS =0.0V
0
–
VAREF
V
ADOV
ADC OP output voltage swing
Vdd=VAREF=5.0V, VASS =0.0V,
RL=10KΩ
0
0.2
0.3
4.7
4.8
5
ADSR
ADC OP slew rate
Vdd=VAREF=5.0V, VASS =0.0V
0.1
0.3
–
V/us
Power Supply Rejection
Vdd=5.0V±0.5V
±0
–
±2
LSB
IAI1
IAI2
Ivdd
Parameter
Ivref
Ivdd
IVref
PSR
NOTE:
–
V
1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. There is no current consumption when ADC is off other than minor leakage current.
3. AD conversion result will not decrease when an increase of input voltage and no missing code will
result.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 73
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
8.2
Comparator (OP) Characteristics
(Vdd = 5.0V, Vss=0V, Ta=25℃)
Symbol
Parameter
Condition
SR
Slew rate
IVR
Input voltage range
Vdd =5.0V, VSS =0.0V
OVS
Output voltage swing
Vd =5.0V, VSS =0.0V, RL=10KΩ
Iop
Supply current of OP
Ico
Supply current of Comparator
PSR
R
Vs
Power-supply Rejection
Ration for OP
8.3
Typ.
0.1
0.2
0
Max.
Vdd= 5.0V, VSS =0.0V
0
0.2
0.3
4.7
4.8
5
250
350
500
50
60
2.5
Unit
V/us
5
300
Operating range
NOTE:
Min.
V
V
uA
uA
70
dB
5.5
V
These parameters are hypothetical (not tested) and are provided for design reference only.
Device Characteristics
The graphs below were derived based on a limited number of samples and they are
provided for reference only. Hence, the device characteristic shown herein cannot be
guaranteed as fully accurate. In these graphs, the data maybe out of the specified
operating warranted range.
IRC OSC Frequency (VDD=3V)
9
Frequency (M Hz)
8
7
6
5
4
3
2
1
0
-40
-20
0
25
50
70
85
Temperature (℃)
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
74 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
IRC OSC Frequency (VDD=5V)
10
9
Frequency (M Hz)
8
7
6
5
4
3
2
1
0
-40
-20
0
25
50
70
85
Temperature (℃)
Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V
9
AC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
45
50
55
%
Dclk
Input CLK duty cycle
Tins
Instruction cycle time
(CLKS="0")
Ttcc
TCC input period
Tdrh
Device reset hold time
Ta = 25°C
11.3
Trst
/RESET pulse width
Ta = 25°C
2000
Twdt
Watchdog timer period
Ta = 25°C
11.3
Tset
Input pin setup time
Thold
Input pin hold time
Tdelay
Output pin delay time
Tdrc
ERC delay time
NOTE:
Crystal type
100
DC
ns
RC type
500
DC
ns
(Tins+20)/N*
ns
16.2
21.6
ms
ns
16.2
21.6
0
ms
ns
15
20
25
ns
Cload=20pF
45
50
55
ns
Ta = 25°C
1
3
5
ns
1. N = selected prescaler ratio
2. Twdt1: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout
length is the same as set-up time (18ms).
3. Twdt2: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout
length is the same as set-up time (4.5ms).
4. These parameters are hypothetical (not tested) and are provided for design reference only.
5. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical
results at 25℃. These data are for design reference use only.
6. The Watchdog timer duration is determined by code option Word1 (WDTPS).
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 75
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75VDD
0.25VDD
TEST POINTS
0.75VDD
0.25VDD
GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing
measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
76 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
APPENDIX
A. Package Types Summary
OTP MCU
Package Type
Pin Count
Package Size
EM78P259NP
DIP
18
300mil
EM78P259NM
SOP
18
300mil
EM78P260NP
DIP
20
300mil
EM78P260NM
SOP
20
300mil
SSOP
20
209mil
EM78P260NKM
B Packaging Configurations
B.1 18-Lead Plastic Dual in line (PDIP) — 300 mil
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 77
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
B.2 18-Lead Plastic Small Outline (SOP) — 300 mil
78 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
B.3 20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 79
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
B.4 20-Lead Plastic Dual-in-line (PDIP) — 300 mil
80 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
B.5 20-Lead Plastic Small Outline (SOPP) — 300 mil
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
• 81
EM78P259N/260N
8-Bit Microprocessor with OTP ROM
C Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=245±5℃, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
Step 1: TCT, 65℃ (15mins)~150℃ (15mins), 10 cycles
Step 2: Bake at 125℃, TD (durance)=24 hrs
Step 3: Soak at 30°C/60%，TD (durance)=192 hrs
Pre-condition
For SMD IC (such as
SOP, QFP, SOJ, etc)
Step 4: IR flow 3 cycles
(Pkg thickness≧2.5mm or
Pkg volume≧350mm3 ----225±5℃)
(Pkg thickness≦2.5mm or
Pkg volume≦350mm3 ----240±5℃ )
Temperature cycle test
-65℃ (15mins)~150℃ (15mins), 200 cycles
Pressure cooker test
TA =121℃, RH=100%, pressure=2 atm,
TD (durance)= 96 hrs
High temperature /
High humidity test
TA=85℃ , RH=85%，TD (durance)=168 , 500 hrs
High-temperature
storage life
TA=150℃, TD (durance)=500, 1000 hrs
High-temperature
operating life
TA=125℃, VCC=Max. operating voltage,
TD (durance) =168, 500, 1000 hrs
Latch-up
TA=25℃, VCC=Max. operating voltage, 150mA/20V
ESD (HBM)
TA=25℃, ≧∣± 3KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (MM)
TA=25℃, ≧∣± 300V∣
VDD-VSS(+),VDD_VSS
(-)mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise caused address error is detected, the MCU will repeat execution of the program
until the noise is eliminated. The MCU will then continue to execute the next program.
82 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)