EM78F734N 8-Bit Microcontroller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. May 2014 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2014 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, TAIWAN 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 [email protected] http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 Elan Information Technology Group (U.S.A.) PO Box 601 Cupertino, CA 95015 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8225 Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 8A Floor, Microprofit Building Gaoxin South Road 6 Shenzhen Hi-tech Industrial Park South Area, Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 [email protected] 6F, Ke Yuan Building No. 5 Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-0273 [email protected] Contents Contents 1 General Description .................................................................................................. 1 2 Features ..................................................................................................................... 1 3 Pin Assignment ......................................................................................................... 2 4 Pin Description.......................................................................................................... 3 5 Block Diagram ........................................................................................................... 5 6 Functional Description ............................................................................................. 6 6.1 Operational Registers ........................................................................................ 6 6.2 Special Function Registers ................................................................................. 25 6.3 TCC/WDT and Prescaler ................................................................................. 30 6.4 I/O Ports ........................................................................................................... 31 6.5 Reset and Wake-up.......................................................................................... 34 6.6 Interrupt............................................................................................................ 44 6.7 Data EEPROM ................................................................................................. 46 6.7.1 Data EEPROM Control Register ..........................................................................46 6.7.1.1 RB (EEPROM Control Register) ........................................................46 6.7.1.2 RC (128 Bytes EEPROM Address)....................................................47 6.7.1.3 RD (256 Bytes EEPROM Data) .........................................................47 6.7.2 Programming Step / Example Demonstration ......................................................47 6.7.2.1 Programming Step .............................................................................47 6.7.2.2 Example Demonstration Programs ....................................................48 6.8 Analog-to-Digital Converter (ADC) ................................................................... 48 6.8.1 ADC Control Register (AISR/R5, ADCON/R6, ADOC/R7) ...................................49 6.8.2 Bank 2 R5 AISR (ADC Input Select Register)......................................................49 6.8.3 Bank 2 R6 ADCON (A/D Control Register) ..........................................................50 6.8.4 Bank 2 R7 ADOC (A/D Offset Calibration Register).............................................51 6.8.5 ADC Data Buffer (ADDH, ADDL/R8, R9)..............................................................51 6.8.6 A/D Sampling Time...............................................................................................51 6.8.7 A/D Conversion Time............................................................................................52 6.8.8 A/D Operation during Sleep Mode .......................................................................52 6.8.9 Programming Steps/Considerations.....................................................................53 6.8.9.1 Programming Steps............................................................................53 6.8.9.2 Sample Demonstration Programs......................................................53 6.9 Timer/Counter 1 ............................................................................................... 55 6.10 Timer/Counter 3 ............................................................................................... 56 6.12 Oscillator .......................................................................................................... 58 6.12.1 Oscillator Modes.................................................................................................58 6.12.2 Internal RC Oscillator Mode ...............................................................................61 Product Specification (V1.0) 05.13.2014 • iii Contents 6.13 Code Option Register....................................................................................... 61 6.13.1 Code Option Register (Word 0)..........................................................................61 6.13.2 Code Option Register (Word 1)..........................................................................63 6.13.3 Customer ID Register (Word 2)..........................................................................64 6.14 Power-on Considerations................................................................................. 65 6.15 External Power-on Reset Circuit ...................................................................... 65 6.16 Residue-Voltage Protection.............................................................................. 66 6.17 Instruction Set .................................................................................................. 67 7 Timing Diagrams ..................................................................................................... 70 8 Absolute Maximum Ratings ................................................................................... 71 9 DC Electrical Characteristics ................................................................................. 72 9.1 Data EEPROM Electrical Characteristics......................................................... 73 9.2 Program Flash Memory Electrical Characteristics ........................................... 74 9.3 A/D Converter Characteristics.......................................................................... 74 10 AC Electrical Characteristics ................................................................................. 76 A Package Type........................................................................................................... 77 B Package Information............................................................................................... 78 B.1 EM78F734ND16 300mil................................................................................... 78 B.2 EM78F734NSO16 300mil ................................................................................ 79 B.3 EM78F734NSS16 150mil................................................................................. 80 B.4 EM78F734ND18 300mil................................................................................... 81 B.5 EM78F734NSO18 300mil ................................................................................ 82 B.6 EM78F734ND20 300mil................................................................................... 83 B.7 EM78F734NSO20 300mil ................................................................................ 84 C Quality Assurance and Reliability ......................................................................... 85 C.1 Address Trap Detect ........................................................................................ 85 Specification Revision History Doc. Version 1.0 iv • Revision Description Initial version Date 2014/05/13 Product Specification (V1.0) 05.13.2014 EM78F734N 8-Bit Microcontroller 1 General Description The EM78F734N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology and high noise immunity. It has an on-chip 4K×13-bit Electrical Flash Memory and 128×8-bit In-system programmable EEPROM. It provides three protection bits to prevent intrusion of user’s Flash memory code. With its enhanced Flash-ROM feature, the EM78F734N provides a convenient way of developing and verifying user’s programs. Moreover, this Flash-ROM device offers the advantages of easy and effective program updates, using development and programming tools. Users can avail of the ELAN Writer to easily program their development codes. 2 Features • 4K×13 bits Flash memory • 144×8 bits on-chip registers (SRAM) • 128 bytes In-system programmable EEPROM 8-level stacks for subroutine nesting I/O Port Configuration Internal interrupt: 4 External interrupt: 4 Seven channels Analog-to-Digital Converter with 12-bit resolution Peripheral Configuration • • Three bidirectional I/O ports • Wake-up port : P6 • 12 Programmable pull-down I/O pins • 8 programmable pull-high I/O pins • overflow interrupt Power down (Sleep) mode • 4 programmable open-drain I/O pins • Four programmable Level Voltage Reset (LVR) • External interrupt : P60 • Three security registers to prevent intrusion of 8-bit real Timer Clock/Counter (TCC) with selective signal sources, trigger edges, and (LVR) : 3.3V, 3.0V, 2.6V, and 2.0V (POR) Operating Voltage Range: • 2.2V~5.5V @ – 40°C ~85°C (Industrial) • 2.2V~5.5V @ 0°C ~70°C (Commercial) Flash memory codes • One configuration register to accommodate • Two clocks per instruction cycle user’s requirements Operating frequency range (base on two clocks): IRC Drift Rate (Vdd @ 3.3V) Internal RC Frequency Drift Rate • High EFT immunity • Two sub-frequencies; 128kHz and 16kHz, Temperature (-10°C+40°C) Process Total ±1% ±1% ±2% Single instruction cycle commands Five Crystal Range in Oscillator Mode 455kHz the 16kHz is provided by dividing the 128kHz 1 MHz ±1% ±1% ±2% 4 MHz ±1% ±1% ±2% Crystal Range 8 MHz ±1% ±1% ±2% 20 MHz ~ 12 MHz HXT2 12 MHz~6 MHz HXT1 6 MHz ~ 1 MHz XT 1 MHz ~ 100kHz LXT1 • IRC Drift Rate (Temperature: -10°C+40°C) Internal RC Frequency Drift Rate Oscillator Mode Voltage (3.0~3.6V) Process Total 455kHz ±1% ±1% ±2% 1 MHz ±1% ±1% ±2% • 16-pin DIP 300mil : EM78F734ND16 4 MHz ±1% ±1% ±2% • 16-pin SOP 300mil : EM78F734NSO16 8 MHz ±1% ±1% ±2% One 16-bit Timer/Counter • Eight available interrupts: • • • • CPU Configuration TC1 : Timer/Counter/Capture One 8-bit Timer/Counter • TC3 : Timer/Counter/PDO (Programmable Divider Output) / PWM (Pulse Width Modulation) Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) Programmable free running Watchdog Timer Package Type: • 16-pin SSOP 150mil : EM78F734NSS16 • 18-pin DIP 300mil : EM78F734ND18 EM78F734NSO18 • 18-pin SOP 300mil : • 20-pin DIP 300 mil : EM78F734ND20 • 20-pin SOP 300mil : EM78F734NSO20 Note: These are Green Products which do not contain hazardous substances. •1 EM78F734N 8-Bit Microcontroller 3 Pin Assignment Figure 3-1 EM78F734ND16/SO16/SS16 Figure 3-2 EM78F734ND18/SO18 Figure 3-3 EM78F734ND20/SO20 2• Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 4 Pin Description Table 1 EM78F734N Pin Description Legend: CMOS: ST: Schmitt Trigger input CMOS output AN: analog pin XTAL: Oscillation pin for crystal / resonator Input Type Output Type P50 ST CMOS VREF AN − P51 P51 ST CMOS Bidirectional I/O pin with programmable pull-down P52 P52 ST CMOS Bidirectional I/O pin with programmable pull-down P53 P53 ST CMOS Bidirectional I/O pin with programmable pull-down P54 ST CMOS Bidirectional I/O pin XTAL − − CMOS Name Function P50/VREF P54/OSCI/RCOUT OSCI RCOUT Description Bidirectional I/O pin with programmable pull-down ADC external voltage reference External clock crystal resonator oscillator input pin Clock output of internal RC oscillator Clock output of external RC oscillator (open-drain) P55 ST CMOS Bidirectional I/O pin − XTAL Clock output from crystal oscillator P57 ST CMOS Bidirectional I/O pin TC3 ST − P55/OSCO OSCO P57/TC3/AD7 Timer 3 input (Counter/Capture/Window) Timer 3 output (PDO/PWM/Buzzer) PDO − CMOS AD7 AN − P60 ST CMOS Programmable divider output ADC Input 7 Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wake-up P60/AD0//INT AD0 AN − ADC Input 0 /INT ST − External interrupt pin P61 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wake-up P61/AD1 AD1 AN Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) − ADC Input 1 •3 EM78F734N 8-Bit Microcontroller (Continuation) Name Function Input Type Output Type P62 ST CMOS Description Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wake-up P62/AD2 AD2 AN − P63 ST CMOS ADC Input 2 Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wake-up P63/AD3 AD3 AN − P70 ST CMOS Bidirectional I/O pin, pull-high (DATA) ST CMOS DATA pin for Writer programming P71 ST CMOS Bidirectional I/O pin, pull-high (CLK) ST − P72 ST CMOS Bidirectional I/O pin, pull-high P73 ST CMOS Bidirectional I/O pin, pull-high AD4 AN − P74 ST CMOS TC1 ST − P77 ST CMOS TCC ST − Real Time Clock/Counter clock input AD5 AN − ADC Input 5 P83 ST CMOS /RESET ST − Internal pull-high reset pin (/RESET) ST − /RESET pin for Writer programming VDD (VDD) VDD Power − Power VDD Power − VDD for Writer programming VSS (VSS) VSS Power − Ground VSS Power − VSS for Writer programming P70 (DATA) P71 (CLK) P72 P73/AD4 P74/TC1 P77/TCC/AD5 P83//RESET (/RESET) 4• ADC Input 3 CLOCK pin for Writer programming ADC Input 4 Bidirectional I/O pin Timer 1 input (Counter/Capture) Bidirectional I/O pin Bidirectional I/O pin Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 5 Block Diagram ROM P8 Instruction register P83 Sub IRC PC 8 level stack P7 IRC Reset Oscillator generator TCC TCC TC1 TC1 TC3 TC3 LVR Crystal Instruction decoder P77 P74 P73 WDT ADC ADC 0~5, 7 EEPROM P72 P71 P70 MUX Interrupt control reg. RAM Interrupt circuit ALU P6 R4 P63 P62 P61 P60 P5 P57 P55 P54 P53 P52 P51 P50 ACC Status reg. Ext INT Figure 5-1 EM78F734N Functional Block Diagram Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) •5 EM78F734N 8-Bit Microcontroller 6 Functional Description 6.1 Operational Registers 6.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 6.1.2 R1 (Timer Clock/Counter) R1 is incremented by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. It is writable and readable as any other registers. It is defined by resetting PSTE (CONT-3). The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The contents of the prescaler counter are cleared only when the TCC register is written with a value. 6.1.3 R2 (Program Counter) and Stack Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Figure 6-1. The configuration structure generates 4K×13 bits on-chip Flash ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all “0”s when under a reset condition. “JMP” instruction allows direct loading of the lower 10 program counter bits. Thus, “JMP” allows PC to go to any location within a page (1K). “CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. “LJMP” instruction allows direct loading of the program counter bits (A0~A11). Thus, “LJMP” allows the PC to go to any location within 4K (212). “LCALL” instruction loads the program counter bits (A0~A11), and PC+1 are pushed onto the stack. Thus, the subroutine entry address can be located anywhere within 4K (212). “RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents of the top-level stack. “ADD R2, A” allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. 6• Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller “MOV R2, A” allows loading an address from the “A” register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC remain unchanged. Any instruction except “ADD R2,A” that is written to R2 (e.g. “MOV R2, A”, “BC R2, 6”) will cause the ninth bit and the tenth bit (A8~A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2) except for the instructions that would change the contents of R2 and “LCALL”, “LJMP”, “TBRD” instruction. The “LCALL”, “LJMP” and “TBRD” instructions need two instruction cycles. User Memory Space Figure 6-1 Program Counter Organization Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) •7 EM78F734N 8-Bit Microcontroller Figure 6-2 Data Memory Configuration 8• Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − T P Z DC C Bit 7 ~ 5: Not used, set to “0” at all time Bit 4 (T): Time-out bit Set to “1” with the “SLEP” and “WDTC” commands, or during power up and reset to “0” by WDT time-out. Bit 3 (P): Power down bit Set to “1” during power on or by a “WDTC” command and reset to “0” by a “SLEP” command. Bit 2 (Z): Zero flag Set to “1” if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 6.1.5 R4 (RAM Select Register) Bits 7 ~ 6: Used to select Bank 0 ~ Bank 3 Bits 5 ~ 0: Used to select registers (Address: 00~3F) in indirect addressing mode. See the data memory configuration in Figure 6-2. 6.1.6 Bank 0 R5 ~ R8 (Port 5 ~ Port 8) R5 ~ R7 are I/O registers. 6.1.7 Bank 0 R9 TBPTL (Low byte of Table Pointer Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBit 7 RBit 6 RBit 5 RBit 4 RBit 3 RBit 2 RBit 1 RBit 0 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) •9 EM78F734N 8-Bit Microcontroller 6.1.8 Bank 0 RA (Wake- up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - ICWE ADWE EXWE - - − − Bit 7: Not used, set to “0” at all time Bit 6 (ICWE): Port 6 input status change wake-up enable bit 0 : Disable Port 6 input status change wake-up 1 : Enable Port 6 input status change wake-up Bit 5 (ADWE): ADC wake-up enable bit 0 : Disable ADC wake-up 1 : Enable ADC wake-up When ADC completed status is used to enter the interrupt vector or to wake up the EM78F734N from sleep, with A/D conversion running, the ADWE bit must be set to “Enable“. Bit 4 (EXWE): External wake-up enable bit 0 : Disable External /INT pin wake-up 1 : Enable External /INT pin wake-up Bits 3 ~ 0: Not used, set to “0” at all time 10 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.9 Bank 0 RB (EEPROM Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD WR EEWE EEDF EEPC - - - Bit 7 (RD): Read control register 0 : Does not execute EEPROM read 1 : Read EEPROM content, (RD can be set by software, RD is cleared by hardware after Read instruction is completed) Bit 6 (WR): Write control register 0 : Write cycle to the EEPROM is completed. 1 : Initiate a write cycle, (WR can be set by software, WR is cleared by hardware after Write cycle is completed) Bit 5 (EEWE): EEPROM Write Enable bit. 0 : Prohibit write to the EEPROM 1 : Allows EEPROM write cycles Bit 4 (EEDF): EEPROM Detective Flag 0 : Write cycle is completed 1 : Write cycle is unfinished Bit 3 (EEPC): EEPROM power-down control bit 0 : Switch off the EEPROM 1 : EEPROM is operating Bits 2 ~ 0: Not used, set to “0” at all time 6.1.10 Bank 0 RC (EEPROM Address) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - EE_A6 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0 Bits 6 ~ 0: EEPROM address 6.1.11 Bank 0 RD (EEPROM Data) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0 Bits 7 ~ 0: EEPROM data Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 11 EM78F734N 8-Bit Microcontroller 6.1.12 Bank 0 RE (CPU Operating Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - TIMERSC CPUS IDLE- - Bit 7: Bit 2 Bit 1 Bit 0 Not used, set to “0” at all time Bit 6 (TIMERSC): TCC, TC1, TC3 clock source select 0 : Fs. Fs: sub frequency for WDT internal RC time base 1 : Fm. Fm: main-oscillator clock Bit 5 (CPUS): CPU Oscillator Source Select 0 = Sub-oscillator (fs) 1 = Main oscillator (fosc) When CPUS=0, the CPU oscillator selects a sub-oscillator and the main oscillator is stopped. Bit 4 (IDLE): Idle Mode Enable Bit. This bit determines the Idle mode status under SLEP instruction. 0 : IDLE=”0”+SLEP instruction → Sleep mode 1 : IDLE=”1”+SLEP instruction → Idle mode CPU Operation Mode Figure 6-3 CPU Operation Mode Bits 3 ~ 0: Not used, set to “0” at all time 12 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.13 Bank 0 RF (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − ADIF - - - EXIF ICIF TCIF Note: “ 1 ” means with interrupt request “ 0 ” means no interrupt occurs Bit 7: Not used, set to “0” at all time Bit 6 (ADIF): Interrupt flag for analog to digital conversion. Set when AD conversion is completed, reset by software. Bits 5 ~ 3: Not used, set to “0” at all time Bit 2 (EXIF): External interrupt flag. Set by a falling edge on /INT pin, reset by software. Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes,reset by software. Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows, reset by software. Bank 0 RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. NOTE The result of reading Bank 0 RF is the "logic AND" of Bank 0 RF and IOCF. 6.1.14 R10 ~ R3F These are all 8-bit general-purpose registers. 6.1.15 Bank 1 R5 TC1CR (Timer 1 Control) Bit 7 Bit 6 Bit 5 Bit 4 TC1CAP TC1S TC1M TC1ES Bit 3 Bit 2 TC1MOD TCK1CK2 Bit 1 Bit 0 TC1CK1 TC1CK0 Bit 7 (TC1CAP): Software capture control 0 : Software capture disable 1 : Software capture enable Bit 6 (TC1S): Timer/Counter 1 start control 0 : Stop and clear the counter 1 : Start Timer/Counter 1 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 13 EM78F734N 8-Bit Microcontroller Bit 5 (TC1M): Timer/Counter 1 mode select 0 : Timer/Counter 1 mode 1 : Capture mode Bit 4 (TC1ES): TC1 signal edge 0 : increment if the transition from low to high (rising edge) takes place on the TC1 pin. 1 : increment if the transition from high to low (falling edge) takes place on TC1 pin. Bit 3 (TC1MOD): Timer Operation Mode Selection Bit 0: Two 8-bit timers 1: Timer 1 and 2 are cascaded as one 16-bit timer. The corresponding control register of 16-bit timer is from timer 1. TC1DA and TC1DB are low byte. TC2DA and TC2DB are high byte. Bit 2 ~ Bit 0 (TC1CK2 ~ TC1CK0): Timer/Counter 1 clock source select TC1CK2 0 0 0 0 TC1CK1 0 0 1 1 Clock Source Resolution 8 MHz Max. time Normal 0 FC/223 1 13 8 3 2 TC1CK0 0 1 FC/2 FC/2 FC/2 Max. time 8 MHz Resolution 16kHz FC=8M FC=8M FC=16K FC=16K 1.05s 19.1hr 145hr 9544hr 1.024ms 67.11s 512ms 33554.432s 32µs 2.097s 16ms 1048.576s 1µs 65.536ms 0.5ms 32768ms 16kHz 1 0 0 FC/2 0.5µs 32.768ms 0.25ms 16384ms 1 0 1 FC/2 0.25µs 16.384ms 125µs 8192ms 1 1 0 FC 125ns 8.192ms 0.0625ms 4096ms 1 1 1 External clock (TC1 pin) - - - - Bits 1 ~ 0: Not used, set to “0” at all time. 14 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Figure 6-4 Timer/Counter 1 Configuration In Timer mode, counting up is performed using the internal clock. When the contents of the up-counter matched with the TC1DA, interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into TC1DB by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after capture. The timer mode will operate with 16bits by setting TC1MOD to “1” In Counter mode, counting up is performed using the external clock input pin (TC1 pin) and either rising or falling edge can be selected by TC1ES, but both edges cannot be used. When the contents of the up-counter matched with the TC1DA, interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into the TC1DB by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after capture. The counter mode will operate with 16 bits by setting TC1MOD to “1”. In Capture mode, the pulse width, period and duty of the TC1 input pin are measured in this mode, which can be used to decode the remote control signal. The counter is set as free running by the internal clock. On a rising (falling) edge of TC1 pin input, the contents of the counter is loaded into TC1DA, then the counter is cleared and interrupt is generated. On a falling (rising) edge of the TC1 pin input, the contents of the counter are loaded into TC1DB. The counter is still counting, on the next rising edge of the TC1 pin input, the contents of the counter are loaded into TC1DA, the counter is cleared and interrupt is generated again. If an overflow occurs before an edge is detected, the FFH is loaded into TC1DA and the overflow interrupt is generated. During interrupt processing, it can be determined whether there is an overflow by checking if the TC1DA value is FFH. After an interrupt (capture to TC1DA or overflow detection) is generated, capture and overflow detection are halted until TC1DA is read out. The capture mode will operate with 16 bits by setting TC1MOD to “1”. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 15 EM78F734N 8-Bit Microcontroller Clock source Up-counter K-2 K-1 K 0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF0 1 2 3 TC1 pin input TC1DA K TC1DB n FF (overflow) m FE capture TC1 interrupt overflow capture Reading TC1DA Figure 6-5 (a) Timing Chart of 8 bits Capture Mode Figure 6-5 (b) Timing Chart of 16 bits Capture Mode 6.1.16 Bank 1 R6 TC1DA (Timer 1 Data Buffer A) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0 Bit 7 ~ Bit 0 (TC1DA7 ~ TC1DA0): Data buffer of 8-bit Timer/Counter 1. 6.1.17 Bank 1 R7 TC1DB (Timer 1 Data Buffer B) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0 Bit 7 ~ Bit 0 (TC1DB7 ~ TC1DB0): Data buffer of 8-bit Timer/Counter 1. 16 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.18 Bank 1 R8 OSCR (Oscillator Control) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCM1 RCM0 − − − − − − Bit 7 ~and Bit 6 (RCM1, RCM0): IRC mode select bits Writer Trim IRC 4 MHz 1 MHz 8 MHz 455kHz Bank1 R8<7,6> RCM1 RCM0 Frequency 0 0 4 MHz 0 1 1 MHz 1 0 8 MHz 1 1 455kHz 0 0 4 MHz 0 1 1 MHz 1 0 8 MHz 1 1 455kHz 0 0 4 MHz 0 1 1 MHz 1 0 8 MHz 1 1 455kHz 0 0 4 MHz 0 1 1 MHz 1 0 8 MHz 1 1 455kHz NOTE Bank 1 R8<7,6 > of the initialized values are kept the same as Word 1<3,2>. After A Frequency switches to B Frequency, EM78F734N needs to hold some stable time on B frequency. Ex: Writer trim IRC 4 MHz → Bank 1 R8<7,6> set to “10” → holds 3 µs → EM78F734N works on 8 MHz ± 10%. Code Option Word 1 COBS=0: The R8<7,6 > of the initialized values will remain the same as Word 1<3,2>. The R8<7,6 > cannot change frequency. Code Option Word 1 COBS=1: The R8<7,6 > of the initialized values will remain the same Word as 1<3,2>. The R8<7,6> can change when user wants to work on other IRC frequency. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 17 EM78F734N 8-Bit Microcontroller 6.1.19 Bank 1 R9 TC2DA (Timer 2 Data Buffer A) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1 TC2DA0 Bits 7~0 (TC2DA7~ TC2DA0): Data buffer of 8-bit Timer/Counter 2. 6.1.20 Bank 1 RA TC2DB (Timer 2 Data Buffer B) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1 TC2DB0 Bit 7 ~ Bit 0 (TC2DB7 ~ TC2DB0): Data buffer of 8-bit Timer/Counter 2. 6.1.21 Bank 1 RB ~RE These are reserved registers. 6.1.22 Bank 1 RF (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - TCIF3 − TCIF1 - - - Note: “ 1 ” means with interrupt request “ 0 ” means no interrupt occurs Bits 7~6: Not used, set to “0” at all time Bit 5 (TCIF3): 8-bit Timer/Counter 3 interrupt flag. The Interrupt flag is cleared by software. Bit 4: Not used, set to “0” at all time Bit 3 (TCIF1): 8-bit Timer/Counter 1 interrupt flag. The Interrupt flag is cleared by software. Bits 2~0: Not used, set to “0” at all time Bank 1 RF can be cleared by instruction but cannot be set. IOCE is the interrupt mask register. NOTE The result of reading Bank 1 RF is the "Logic AND" of Bank 1 RF and IOCE. 18 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.23 Bank 2 R5 AISR (ADC Input Select Register) The AISR register for ADC pins act as analog input or digital I/O. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE7 − ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bit 7 (ADE7): AD converter enable bit of P57 pin. 0 : Disable ADC7, P57 functions as I/O pin. 1 : Enable ADC7 to function as analog input pin Bit 6: Not used, set to “0” at all time Bit 5 (ADE5): AD converter enable bit of P77 pin 0 : Disable ADC5, P77 functions as I/O pin 1 : Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P73 pin 0 : Disable ADC4, P73 functions as I/O pin 1 : Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P63 pin. 0 : Disable ADC3, P63 functions as I/O pin 1 : Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P62 pin. 0 : Disable ADC2, P62 functions as I/O pin 1 : Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P61 pin 0 : Disable ADC1, P61 functions as I/O pin 1 : Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P60 pin 0 : Disable ADC0, P60 functions as I/O pin 1 : Enable ADC0 to function as analog input pin The following table shows the priority of P60/AD1//INT. P60/AD0//INT Pin Priority High Medium Low /INT AD0 P60 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 19 EM78F734N 8-Bit Microcontroller 6.1.24 Bank 2 R6 ADCON (A/D Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Bit 7 (VREFS): The input source of the Vref of the ADC. 0 : Vref of the ADC is connected to the Internal reference which is selected by Bank 2 R9<5,4>(default value), and the P50/VREF pin carries out the function of P50 1 : Vref of the ADC is connected to P50/VREF Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The oscillator clock rate of ADC CKR1/CKR0 Operation Mode Max. Operation Frequency 00 FOSC/4 4 MHz 01 FOSC 1 MHz 10 FOSC/16 8 MHz 11 FOSC/2 1 MHz RCM[1:0]* Frequency (MHz) Sample and Hold Timing 00 4 8 x TAD 01 1 4 x TAD 10 8 12 x TAD 11 455k 2 x TAD *When using XT, LXT1, HXT1, HXT2 mode can also modify RCM[1:0] at Code Option Word 1 to set the Sample and Hold time. Bit 4 (ADRUN): ADC starts to run 0 : Reset upon completion of AD conversion. This bit cannot be reset by software. 1 : A/D conversion is started. This bit can be set by software. Bit 3 (ADPD): ADC Power-down mode 0 : Switch off the resistor reference to save power even while the CPU is operating. 1 : ADC is operating 20 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Bits 2~0 (ADIS2~ADIS0): AD Input Select Bits ADIS2 ADIS1 ADIS0 AD Input Pin 0 0 0 AD0 0 0 1 AD1 0 1 0 AD2 0 1 1 AD3 1 0 0 AD4 1 0 1 AD5 1 1 0 Reserve 1 1 1 AD7 6.1.25 Bank 2 R7 ADOC (A/D Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − − PDE − − Bits 7~3: Not used, set to “0” at all time Bit 2 (PDE): 1/2 VDD Power Detect Enable bit 0 : Disable Power Detect (Default) 1 : Enable Power Detect PDE 1 0 ADIS2 − × ADIS1 − × ADIS0 − × AD Input Select 1/2VDD ADx Bits 1~0: Not used, set to “0” at all time 6.1.26 Bank 2 R8 ADDH (AD High 8-Bit Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 When the A/D conversion is completed, the result which is high 8-bit is loaded into the ADDH. The ADRUN bit is cleared, and the ADIF is set. R8 is read only. 6.1.27 Bank 2 R9 ADDL (AD Low 4-Bit Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - IRVS1 IRVS0 ADD3 ADD2 ADD1 ADD0 Bits 7 ~ 6: Not used, set to “0” at all time Bits 5 ~ 4 (IRVS1~IRVS0): Internal Reference Voltage Selection. IRVS[1:0] 00 01 10 11 Bits 3 ~ 0: Reference Voltage AVDD 4V 3V 2.5 V AD low 4-bit data buffer. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 21 EM78F734N 8-Bit Microcontroller 6.1.28 Bank 2 RA ~ RE These are reserved registers. 6.1.29 Bank 2 RF (Pull-high Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - /PH73 /PH72 /PH71 /PH70 Bits 7 ~ 4: Not used, set to “0” at all time. Bit 3 (/PH73): Control bit used to enable pull-high of the P73 pin 0 : Enable internal pull-high 1 : Disable internal pull-high Bit 2 (/PH72): Control bit used to enable pull-high of the P72 pin. Bit 1 (/PH71): Control bit used to enable pull-high of the P71 pin. Bit 0 (/PH70): Control bit used to enable pull-high of the P70 pin. The RF Register is both readable and writable. 6.1.30 Bank 3 R5 Reserved Register 6.1.31 Bank 3 R6 TBPTH (High Byte of Table Pointer Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLB 0 0 0 RBit 11 RBit 10 RBit 9 RBit 8 Bit 7 (MLB): Take MSB or LSB at machine code. Bits 6 ~ 4: Not used. Set to “0” at all time. Bits 3 ~ 0: Table Pointer Address Bits 11~8. 6.1.32 Bank 3 R7~RC Reserved Registers 6.1.33 Bank 3 RD TC3CR (Timer 3 Control) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC3FF1 TC3FF0 TC3S TC3CK2 TC3CK1 TC3CK0 TC3M1 TC3M0 Bit 7 ~ Bit 6 (TC3FF1 ~ TC3FF0): Timer/Counter 3 flip-flop control 22 • TC3FF1 TC3FF0 Operating Mode 0 0 Clear 0 1 Toggle 1 0 Set 1 1 Reserved Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Bit 5 (TC3S): Timer/Counter 3 start control 0 : Stop and clear the counter 1 : Start Timer/Counter 3 Bit 4 ~ Bit 2 (TC3CK2 ~ TC3CK0): Timer/Counter 3 Clock Source select TC3CK2 0 TC3CK1 TC3CK0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 Clock Source Resolution Max. Time Normal Fc=8M Fc=8M 250 µs 64 ms 16 µs 4 ms 4 µs 1 ms 1 µs 255 µs 500 ns 127.5 µs 11 Fc/2 7 Fc/2 5 Fc/2 3 Fc/2 2 Fc/2 1 1 0 1 Fc/2 250 ns 63.8 µs 1 1 0 Fc 125 ns 31.9 µs 1 1 1 External clock (TC3 pin) - - Bit 1 ~ Bit 0 (TC3M1 ~ TC3M0): Timer/Counter 3 operating mode select TC3M1 TC3M0 Operating Mode 0 0 Timer/Counter 0 1 Reserved 1 0 Programmable Divider output 1 1 Pulse Width Modulation output Figure 6-6 Timer / Counter 3 Configuration In Timer mode, counting up is performed using internal clock (rising edge trigger). When the contents of the up-counter match the TCR3, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 23 EM78F734N 8-Bit Microcontroller In Counter mode, counting up is performed using external clock input pin (TC3 pin). When the contents of the up-counter match the TCR3, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. In Programmable Divider Output (PDO) mode, counting up is performed using the internal clock. The contents of TCR3 are compared with the contents of the up-counter. The F/F output is toggled and the counter is cleared each time a match is found. The F/F output is inverted and output to /PDO pin. This mode can generate 50% duty pulse output. The F/F can be initialized by the program and it is initialized to “0” during reset. A TC3 interrupt is generated each time the /PDO output is toggled. Source clock Up-counter 0 TCR3 1 2 3 n-1 n 0 1 n-1 n 0 1 n n-1 0 1 2 n F/F /PDO Pin TC3 Interrupt Figure 6-7 PDO Mode Timing Chart In Pulse Width Modulation (PWM) Output mode, counting up is performed using internal clock. The contents of TCR3 are compared with the contents of the up-counter and TCR3 should be greater than 1(including 1) . The F/F is toggled when a match is found. The counter continues counting, the F/F is toggled again when the counter overflows, after which the counter is cleared. The F/F output is inverted and output to /PWM pin. A TC3 interrupt is generated each time an overflow occurs. TCR3 is configured as a 2-stage shift register and, during output, will not switch until one output cycle is completed even if TCR3 is overwritten. Therefore, the output can be changed continuously. Also, the first time, TRC3 is shifted by setting TC3S to “1” after data is loaded to TCR3. Source Clock Up-counter TCR3 0 1 n n-1 FE n/n FF 0 n n-1 n+1 n+2 FE n/m match F/F n+1 n+2 overflow match overwrite FF 0 1 m-1 m m/m overflow Shift /PWM TC3 Interrupt 1 period Figure 6-8 PWM Mode Timing Chart 24 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.1.34 Bank 3 RE TC3D (Timer 3 Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC3D7 TC3D6 TC3D5 TC3D4 TC3D3 TC3D2 TC3D1 TC3D0 Bit 7 ~ Bit 0 (TC3D7 ~ TC3D0): Data Buffer of 8-bit Timer/Counter 3 6.1.35 Bank 3 RF (Pull-down Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - /PD73 /PD72 /PD71 /PD70 Bit 7~ Bit 4: Not used, set to “0” at all time Bit 3 (/PD73): Control bit used to enable the P73 pull-down pin 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 2 (/PD72): Control bit used to enable the P72 pull-down pin Bit 1 (/PD71): Control bit used to enable the P71 pull-down pin Bit 0 (/PD70): Control bit used to enable the P70 pull-down pin The RF Register is both readable and writable. 6.2 Special Function Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 6.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTE /INT TS TE PSTE PST2 PST1 PST0 Bit 7 (INTE): INT signal edge 0 : interrupt occurs at the rising edge of the INT pin 1 : interrupt occurs at the falling edge of the INT pin Bit 6 (/INT): Interrupt Enable flag 0 : masked by DISI or hardware interrupt 1 : enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source 0 : internal instruction cycle clock 1 : transition on the TCC pin Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 25 EM78F734N 8-Bit Microcontroller Bit 4 (TE): TCC signal edge 0 : increment if a transition from low to high takes place on the TCC pin 1 : increment if a transition from high to low takes place on the TCC pin Bit 3 (PSTE): Prescaler enable bit for TCC 0 : prescaler disable bit, TCC rate is 1:1 1 : prescaler enable bit, TCC rate is set at Bit 2~Bit 0 Bit 2 ~ Bit 0 (PST 2 ~ PST0): TCC prescaler bits PST2 PST1 PST0 TCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 The CONT register is both readable and writable. 6.2.3 IOC5 ~ IOC8 (I/O Port Control Register) A value of "1" sets the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. IOC5, IOC6 IOC7 and IOC8 registers are both readable and writable. 6.2.4 IOC9 Reserved registers 6.2.5 IOCA (WDT Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS - - PSWE PSW2 PSW1 PSW0 Bit 7 (WDTE): Control bit used to enable the Watchdog timer 0 : Disable WDT 1 : Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit used to define the function of P60 (INT) pin 0 : P60, bidirectional I/O pin 1 : INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1". 26 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). EIS is both readable and writable. Bits 5~4: Not used, set to “0” at all time Bit 3 (PSWE): Prescaler enable bit for WDT 0 : prescaler disable bit, WDT rate is 1:1 1 : prescaler enable bit, WDT rate is set at Bit 0~Bit 2 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits PSW2 PSW1 PSW0 WDT Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.2.6 IOCB (Pull-down Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0 Bit 7 (/PD7): Control bit used to enable pull-down of the of P63 pin 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 6 (/PD6): Control bit used to enable pull-down of the P62 pin Bit 5 (/PD5): Control bit used to enable pull-down of the P61 pin Bit 4 (/PD4): Control bit used to enable pull-down of the P60 pin Bit 3 (/PD3): Control bit used to enable pull-down of the P53 pin Bit 2 (/PD2): Control bit used to enable pull-down of the P52 pin Bit 1 (/PD1): Control bit used to enable pull-down of the P51 pin Bit 0 (/PD0): Control bit used to enable pull-down of the P50 pin The IOCB Register is both readable and writable. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 27 EM78F734N 8-Bit Microcontroller 6.2.7 IOCC (Open-drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − OD3 OD2 OD1 OD0 Bits 7 ~ 4: Not used, set to “0” at all time Bit 3 (OD3): Control bit used to enable the open-drain output of P63 pin 0 : Disable open-drain output 1 : Enable open-drain output Bit 2 (OD2): Control bit used to enable the open-drain output of P62 pin Bit 1 (OD1): Control bit used to enable the open-drain output of P61 pin Bit 0 (OD0): Control bit used to enable the open-drain output of P60 pin The IOCC Register is both readable and writable. 6.2.8 IOCD (Pull-high Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − /PH3 /PH2 /PH1 /PH0 Bits 7~4: Not used, set to “0” at all time Bit 3 (/PH3): Control bit used to enable pull-high of the P63 pin. 0 : Enable internal pull-high 1 : Disable internal pull-high Bit 2 (/PH2): Control bit used to enable pull-high of the P62 pin. Bit 1 (/PH1): Control bit used to enable pull-high of the P61 pin. Bit 0 (/PH0): Control bit used to enable pull-high of the P60 pin. The IOCD Register is both readable and writable. 6.2.9 IOCE (Interrupt Mask Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − TCIE3 − TCIE1 − − − Bits 7~6: Not used, set to “0” at all time Bit 5 (TCIE3): Interrupt enable bit 0 : Disable TCIF3 interrupt 1 : Enable TCIF3 interrupt Bit 4: 28 • Not used, set to “0” at all time Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Bit 3 (TCIE1): Interrupt enable bit 0: Disable TCIF1 interrupt 1: Enable TCIF1 interrupt Bits 2~0: Not used, set to “0” at all time 6.2.10 IOCF (Interrupt Mask Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − ADIE − − − EXIE ICIE TCIE Bit 7: Not used, set to “0” at all time Bit 6 (ADIE): ADIF interrupt enable bit 0 : Disable ADIF interrupt 1 : Enable ADIF interrupt When the ADC Complete is used to enter an interrupt vector or enter the next instruction, the ADIE bit must be set to “Enable“. Bits 5 ~ 3: Not used, set to “0” at all time Bit 2 (EXIE): EXIF interrupt enable bit 0 : Disable EXIF interrupt 1 : Enable EXIF interrupt Perform the following steps from the EXINT, First set EXIE, and then set the EIS. EXINT internal comparison value defaults to "0". Then set the rising edge and the INT pin to high, since doing EXINT setting will cause immediate trigger signal and generate an interrupt. Bit 1 (ICIE): ICIF interrupt enable bit 0 : Disable ICIF interrupt 1 : Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit 0 : Disable TCIF interrupt 1 : Enable TCIF interrupt Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. The IOCF register is both readable and writable. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 29 EM78F734N 8-Bit Microcontroller 6.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PST0~PST2 bits of the CONT register are used to determine the ratio of the prescaler of TCC. Likewise, the PSW0~PSW2 bits of the IOCA register are used to determine the WDT prescaler. The prescaler counter will be cleared by the instructions each time they are written into TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure 6-9 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be the internal clock or the external signal input (edge selectable from the TCC pin). If TCC signal source is from the internal clock, TCC will be incremented by 1 at Fc clock (without prescaler). As illustrated in Figure 6-9, selection of Fc depends on the bank 0 RE.6 <TIMERSC>. If TCC signal source is from external clock input, TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. TCC pin input time length (kept in High or low level) must be greater than 1CLK. The TCC will stop running when sleep mode occurs. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during normal mode by software programming. Refer to WDTE bit of IOCA register. With no prescaler, the WDT time-out period is approximately 16.5 ms1 (one oscillator start-up timer period). Figure 6-9 TCC and WDT Block Diagram 1 30 • VDD=5V, WDT time-out period = 16.5ms ± 5% VDD=3V WDT time-out period = 16.5ms ± 5%. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.4 I/O Ports The I/O registers, Ports 5, 6, 7 and 8, are bidirectional tri-state I/O ports. Port 6 / 7 can be pulled high internally by software. In addition, Port 6 can also have open-drain output by software. Input status change interrupt (or wake-up) function on Port 6 P50 ~ P53 and P60 ~ P63 and Port 7 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC8). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, Port 7 and Port 8 are shown in the following Figures 6-10, 6-11 (a), 6-11 (b), and Figure 6-12. PCRD Q _ Q PORT P R C L Q P R _ Q C L D CLK PCWR IOD D CLK PDWR PDRD 0 1 M U X Note: Pull-down is not shown in the figure. Figure 6-10 I/O Port and I/O Control Register Circuit for Ports 5, 6, 7 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 31 EM78F734N 8-Bit Microcontroller Note: Pull-high (down) and Open-drain are not shown in the figure. Figure 6-11 (a) I/O Port and I/O Control Register Circuit for P60 (INT) Note: Pull-high (down) and Open-drain are not shown in the figure. Figure 6-11 (b) I/O Port and I/O Control Register Circuit for P61~P63, P83 32 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller IOCE.1 D P R Q Interrupt CLK C L _ Q RE.1 ENI Instruction P D R Q T10 T11 CLK _ C Q L P Q R D CLK _ Q C L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Figure 6-12 Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up Table 6-1 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 Input Status Changed Wake-up/Interrupt (I) Wake-up Input Status Change (a) Before Sleep (II) Interrupt Input Status Change 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT2 (use this very carefully) 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF=1) 3 a. Enable interrupt (Set IOCF=1), after wake-up if “ENI” switch to interrupt vector (006H), if “DISI” excute next instruction 4. IF Port 6 change (interrupt) → Interrupt vector (006H) 3 b. Disable interrupt (Set IOCF=1). Always execute next instruction 4. Enable wake-up bit (Set RA=6) 5. Execute "SLEP" instruction (b) After Wake-up 1. IF "ENI" → Interrupt vector (006H) 2. IF "DISI" → Next instruction 2 Software disables WDT (watchdog timer) but hardware must be enabled before applying Port 6 Change Wake-up function (Code Option Register Word 0 Bit 6 (ENWDTB) is set to “1”). 3 Vdd = 5V, set up time period = 16.5ms ± 5% Vdd = 3V, set up time period = 16.5ms ± 5% Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 33 EM78F734N 8-Bit Microcontroller 6.5 Reset and Wake-up 6.5.1 Reset A reset is initiated by one of the following events: (1) Power-on reset (2) /RESET pin input "low" (3) WDT time-out (if enabled) The device is kept in a reset condition for a period of approximately 18ms3 (one oscillator start-up timer period) after the reset is detected. Once a reset occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. When power is switched on, the upper three bits of R3 are cleared. The bits of the RB, RC, RD, RD, RE registers are set to their previous status. The bits of the CONT register are set to all "0" except for Bit 6 (INT flag). The bits of the Pull-high, Pull-down. Bank 0 RF, IOCF registers are cleared. Sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. After a wake-up, in RC mode the wake-up time is 16 clocks. The controller can be awakened by: (1) External reset input on /RESET pin (2) WDT time-out (if enabled) (3) Port 6 input status changes (if enabled) (4) External (P60 / INT) pin changes (if EXWE is enabled) (5) A/D conversion completed (if ADWE is enabled) 3 34 • Vdd = 5V, set up time period = 16.5ms ± 5% Vdd = 3V, set up time period = 16.5ms ± 5% Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller The first two events (1 & 2) will cause the EM78F734N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Events 3, 4, and 5 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from address 0x3, 0x6 0xF, 0x15 or 0X30, after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction right next to SLEP after wake-up. All throughout the sleep mode, wake-up time is150 µs, no matter what oscillation mode (except low Crystal mode). In low Crystal 2 mode, wake-up time is 500ms. One or more of the above Events 3 to 6 can be enabled before entering into sleep mode but is awakened only by one of the events. [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78F734N can be awakened only by Event 1 or 2. Refer to Section 6.6 Interrupt for further details. [b] If Port 6 Input Status Change is used to wake up the EM78F734N and the ICWE bit of the RA register is enabled before SLEP, WDT must be disabled. Hence, the EM78F734N can be awakened only by Event 3. The following instructions must be executed before SLEP: MOV A, @001110xxb IOW IOCA WDTC MOV R6, R6 ENI (or DISI) MOV A, @010xxxxxb MOV RA,A MOV A, @00000x1xb IOW IOCF SLEP ;Select WDT prescaler and disable WDT ;Clear WDT and prescaler ;Read Port 6 ;Enable (or disable) global interrupt ;Enable Port 6 input change Wake-up bit ;Enable Port 6 input change interrupt ;Sleep [c] If External (P60/INT) pin changes is used to wake-up the EM78F734N and EXWE bit of the RA register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78F734N can be awakened only by Event 4. [d] If AD conversion completed is used to wake-up EM78F734N and ADWE bit of the RA register is enabled before SLEP, the WDT must be disabled by software. Hence, the EM78F734N can be waken-up only by Event 5. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 35 EM78F734N 8-Bit Microcontroller The following instructions must be executed before SLEP: BS BS MOV R4, 7 R4, 6 A, @x10xxxxxb MOV MOV R7,A A, @001110xxb ; Select Bank 3 ; Select a comparator and P70 act ; as CO pin ; Select WDT prescaler and Disable ; WDT IOW IOCA WDTC ENI (or DISI) MOV A, @100xxxxxb MOV MOV RA,A A, @10000000b IOW SLEP IOCE ; ; ; ; ; Clear WDT and prescaler Enable (or disable) global interrupt Enable comparator output status change wake-up bit ; Enable comparator output status ; change interrupt ; Sleep 6.5.2 Summary of Wake-up and Interrupt Modes Operation All categories under Wake-up and Interrupt modes are summarized below. The controller can be awakened from Sleep mode and Idle mode. The Wake-up signals are listed as follows. Wake-up Signal Sleep Mode Idle Mode Green Mode Normal Mode External interrupt If enable EXWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction If enable EXWE bit Wake-up + interrupt (if interrupt is enablee) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Port 6 pin change If enable ICWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction If enable ICWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction x Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction TCC overflow interrupt 36 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller (Continuation) Wake-up Signal Sleep Mode Idle Mode Green Mode Normal Mode AD conversion complete interrupt If enable ADWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction Fs and Fm don’t stop If enable ADWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction Fs and Fm don’t stop Interrupt (if interrupt is enabled) or next instruction Fs and Fm don’t stop Interrupt (if interrupt is enabled) or next instruction x Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction x Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction WDT Time out RESET RESET RESET RESET Low Voltage Reset RESET RESET RESET RESET TC2 interrupt TC3 interrupt After wake up: 1. If interrupt is enabled → interrupt+ next instruction 2. If interrupt is disabled → next instruction 6.5.3 Summary of Register Initial Values Legend: x: Not used U: Unknown or don’t care Addr 0x05 0x06 Name IOC5 IOC6 Reset Type IOC7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name C57 - C55 C54 C53 C52 C51 C50 Power-on 1 0 1 1 1 1 1 1 /RESET and WDT 1 0 1 1 1 1 1 1 Wake-up from Pin Change P 0 P P P P P P Bit Name - - - - C63 C62 C61 C60 Power-on 0 0 0 0 1 1 1 1 /RESET and WDT 0 0 0 0 1 1 1 1 Wake-up from Pin Change 0 0 0 0 P P P P C77 - - C74 C73 C72 C71 C70 Bit Name 0x07 Bit 7 P: Previous value before reset t: Check tables under Section 6.5.4 Power-on 1 0 0 1 1 1 1 1 /RESET and WDT 1 0 0 1 1 1 1 1 Wake-up from Pin Change P 0 0 P P P P P Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 37 EM78F734N 8-Bit Microcontroller (Continuation) Addr 0x08 N/A Name IOC8 CONT Reset Type R1 (TCC) 0x02 R2 (PC) 0x03 R3 (SR) R4 (RSR) Bit 0 - - C83 - - - 0 0 1 0 0 0 /RESET and WDT 0 0 0 0 1 0 0 0 Wake-up from Pin Change 0 0 0 0 P 0 0 0 Bit Name INTE /INT TS TE PSTE PST2 PST1 PST0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 P P P P P P P P Bit Name IAR7 IAR6 IAR5 IAR4 IAR3 IAR2 IAR1 IAR0 Power-on U U U U U U U U /RESET and WDT P P P P P P P P P P P P P P P P Bit Name TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name A7 A6 A5 A4 A3 A2 A1 A0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - T P Z DC C Power-on 0 0 0 1 1 U U U /RESET and WDT 0 0 0 t t P P P 0 0 0 t t P P P Bit Name RSR7 RSR6 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 Power-on U U U U U U U U /RESET and WDT P P P P P P P P P P P P P P P P Bit Name P57 - P55 P54 P53 P52 P51 P50 Power-on P5 (Bank 0) /RESET and WDT 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 P 0 P P P P P P Bit Name - - - - P63 P62 P61 P60 Power-on 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P6 (Bank 0) /RESET and WDT 0 0 0 0 P P P P Bit Name P77 - - P74 P73 P72 P71 P70 Power-on P7 (Bank 0) /RESET and WDT 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 P 0 0 P P P P P Wake-up from Pin Change 38 • Bit 1 - Wake-up from Pin Change 0x07 Bit 2 0 Wake-up from Pin Change 0x06 Bit 3 - Wake-up from Pin Change 0x05 Bit 4 0 Wake-up from Pin Change 0x04 Bit 5 Power-on Wake-up from Pin Change 0x01 Bit 6 Bit Name Wake-up from Pin Change 0x00 R0 (IAR) Bit 7 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller (Continuation) Addr 0x08 Name Reset Type 0x0A Bit 6 Bit 5 - - - P83 - - - 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 P 0 0 0 Bit Name RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0 Power-on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P - - - - P8 (Bank 0) /RESET and WDT R9 (Bank 0) /RESET and WDT Wake-up from Pin Change P Bit Name - Power-on RA (Bank 0) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P ICWE ADWE EXWE P WR RB Power-on 0X0B (ECR) (Bank 0) /RESET and WDT Wake-up from Pin Change 0 0 0 P P P P Bit Name - Power-on 0 RC (Bank 0) /RESET and WDT Wake-up from Pin Change Bit Name Power-on RD (Bank 0) /RESET and WDT 0 0 0 0 EEPC - - - 0 0 0 0 0 P P P 0 0 0 P P P 0 0 0 EEWE EEDF EE_A6 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0 0 0 0 0 0 0 0 0 P P P P P P P 0 P P P P P P P EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0 0 0 0 0 0 0 0 0 P P P P P P P P P P P P P P P IDLE - - - - Wake-up from Pin Change P Bit Name - Power-on RE (Bank 0) /RESET and WDT 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 TIMERSC CPUS Wake-up from Pin Change 0 P P P 0 0 0 0 Bit Name - ADIF - - - EXIF ICIF TCIF RF (ISR) Power-on (Bank 0) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 P P P Wake-up from Pin Change Bit Name 0x5 Bit 0 0 0 0x0F Bit 1 - RD 0X0E Bit 2 0 Wake-up from Pin Change 0X0D Bit 3 Power-on Bit Name 0X0C Bit 4 Bit Name Wake-up from Pin Change 0X09 Bit 7 Power-on R5 (Bank 1) /RESET and WDT Wake-up from Pin Change TC1AP TC1S TC1M TC1ES TC1MOD TCK1CK2 TC1CK1 TC1CK0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 39 EM78F734N 8-Bit Microcontroller (Continuation) Addr Name Reset Type Bit Name 0x6 Power-on R6 (Bank 1) /RESET and WDT Wake-up from Pin Change Bit Name 0X7 Power-on R7 (Bank 1) /RESET and WDT Wake-up from Pin Change R8 0x8 (Bank 1) Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P - - - - - Power-on Option RCM1 Option RCM0 0 0 0 0 0 0 /RESET and WDT Option RCM1 Option RCM0 0 0 0 0 0 0 P P 0 0 0 0 0 0 Power-on R9 (Bank 1) /RESET and WDT Power-on RA (Bank 1) /RESET and WDT TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1 TC2DA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1 TC2DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - TCIF3 - TCIF1 - - - Power-on RF (Bank 1) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 P 0 0 0 Bit Name ADE7 - ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Power-on R5 (Bank 2) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 P P P P P P Wake-up from Pin Change Bit Name Power-on R6 (Bank 2) /RESET and WDT Wake-up from Pin Change 40 • Bit 2 P Wake-up from Pin Change 0x06 Bit 3 - Wake-up from Pin Change 0x05 Bit 4 P Bit Name 0XF Bit 5 RCM1 RCM0 Bit Name 0XA Bit 6 Bit Name Wake-up from Pin Change 0x9 Bit 7 TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller (Continuation) Addr 0x7 Name Reset Type Bit 0 - - - PDE - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R7 (Bank 2) /RESET and WDT Power-on R8 (Bank 2) /RESET and WDT ADD11 ADD10 ADD9 0 0 0 0 0 P 0 0 ADD8 ADD7 ADD6 ADD5 ADD4 0 0 0 0 0 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - ADD3 ADD2 ADD1 ADD0 Power-on R9 (Bank 2) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P IRVS1 IRVS0 Bit Name - - - - /PH73 /PH72 /PH71 /PH70 Power-On 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P P P RF (Bank 2) /RESET and WDT 0 0 0 0 Bit Name MLB - - - Power-On R6 (Bank 3) /RESET and WDT 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 P P P P Power-on RD (Bank 3) /RESET and WDT Wake-up from Pin Change Bit Name 0XF Bit 1 - Bit Name 0XE Bit 2 0 Wake-up from Pin Change 0XD Bit 3 - Wake-up from Pin Change 0X06 Bit 4 0 Wake-up from Pin Change 0x0F Bit 5 Power-on Wake-up from Pin Change 0x9 Bit 6 Bit Name Bit Name 0x8 Bit 7 Power-on RBit 11 RBit 10 RBit 9 0 0 0 P RBit 8 0 TC3FF1 TC3FF0 TC3S TC3CK2 TC3CK1 TC3CK0 TC3M1 TC3M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P P TC3D7 TC3D6 TC3D5 TC3D4 TC3D3 TC3D2 TC3D1 TC3D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name - - - - /PD73 /PD72 /PD71 /PD70 Power-on RF (Bank 3) /RESET and WDT 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 P P P P RE (Bank 3) /RESET and WDT Wake-up from Pin Change Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 41 EM78F734N 8-Bit Microcontroller (Continuation) Addr Name 0x0A IOCA Bit 7 Bit 6 Bit 5 Bit 4 Bit Name Reset Type WDTE EIS - - Power-on 0 0 0 0 0x0C IOCC 0x0D IOCD 0x0E IOCE 0x0F IOCF 0x10~ R10~ 0x2F R2F 42 • Bit 2 Bit 1 Bit 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P 0 0 P P P P /PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0 Bit Name 0x0B IOCB Bit 3 PSWE PSW2 PSW1 PSW0 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name - - - - OD3 OD2 OD1 OD0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change 0 0 0 0 P P P P Bit Name - - - - /PH3 /PH2 /PH1 /PH0 Power-on 0 0 0 0 1 1 1 1 /RESET and WDT 0 0 0 0 1 1 1 1 Wake-up from Pin Change 0 0 0 0 P P P P Bit Name - - TCIE3 - TCIE1 - - - Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change 0 0 P 0 P 0 0 0 Bit Name - ADIE - - - EXIE ICIE TCIE Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change 0 P 0 0 0 P P P Bit Name R7 R6 R5 R4 R3 R2 R1 R0 Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.5.4 Status of RST, T, and P of the Status Register A reset condition is initiated by the following events: 1. Power-on condition 2. High-low-high pulse on /RESET pin 3. Watchdog timer time-out The values of T and P, listed in the first table below are used to check how the processor wakes up. The second table shows the events that may affect the status of T and P. Values of RST, T and P after Reset Reset Type Power on T P 1 1 *P *P /RESET wake-up during Sleep mode 1 0 WDT during Operating mode 0 *P WDT wake-up during Sleep mode 0 0 Wake-up on pin change during Sleep mode 1 0 /RESET during Operating mode *P: Previous status before reset Status of T and P Being Affected by Events. Event T P Power on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-up on pin change during Sleep mode 1 0 *P: Previous value before reset Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 43 EM78F734N 8-Bit Microcontroller VDD D Oscillator Q CLK CLK CLR Power-On Reset Low Voltage Reset Setup time WDTE WDT WDT Timeout Reset /RESET Figure 6-13 Controller Reset Block Diagram 6.6 Interrupt The EM78F734N has eight interrupts (four external, four internal) as listed below: Interrupt Source Enable Condition Int. Flag Int. Vector Priority - - 0000 High 0 Internal / External Reset External INT ENI + EXIE=1 EXIF 0003 1 External Port 6 pin change ENI +ICIE=1 ICIF 0006 2 Internal TCC ENI + TCIE=1 TCIF 0009 3 Internal TC1 ENI + TCIE1=1 TCIF1 0018 4 Internal TC3 ENI + TCIE3=1 TCIF3 0027 5 Internal AD ENI + ADIE=1 ADIF 0030 6 RF is interrupt status register that records the interrupt requests in the relative flags/ bits. IOCF is interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the enabled interrupts occur, the next instruction will be fetched from their individual address. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. 44 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). The external interrupt is equipped with an on-chip digital noise rejection circuit (input pulse less than 8 system clock time is eliminated as noise). When an interrupt (Falling edge) is generated by the External interrupt (when enabled), the next instruction will be fetched from Address 003H. Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4 register will be saved by hardware. If another interrupt occurred, the ACC, R3 and R4 will be replaced by the new interrupt. After the interrupt service routine is finished, ACC, R3 and R4 will be pushed back. VCC /IRQn IRQn D PR Q _ CLK CL Q RF INT RFRD IRQm ENI/DISI Q PR D IOCF _ CLK Q CL IOD IOCFWR /RESET IOCFRD RFWR Figure 6-14 Interrupt Input Circuit Interrupt Sources ENI/DISI ACC R3 Interrupt occurs RETI R4 Stack ACC Stack R3 Stack R4 Figure 6-15 Interrupt Back-up Diagram Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 45 EM78F734N 8-Bit Microcontroller 6.7 Data EEPROM The Data EEPROM is readable and writable during normal operation over the whole Vdd range. The operation for Data EEPROM is based on a single byte. A write operation makes an erase-then-write cycle to take place on the allocated byte. The Data EEPROM memory provides high erase and write cycles. A byte write automatically erases the location and writes the new value. 6.7.1 Data EEPROM Control Register 6.7.1.1 RB (EEPROM Control Register) The EECR (EEPROM Control Register) is the control register for configuring and initiating the control register status. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD WR EEWE EEDF EEPC - - - Bit 7 (RD): Read control register 0 : Does not execute EEPROM read 1 : Read EEPROM content, (RD can be set by software, RD is cleared by hardware after Read instruction is completed) Bit 6 (WR): Write control register 0 : Write cycle to the EEPROM is completed. 1 : Initiate a write cycle, (WR can be set by software, WR is cleared by hardware after Write cycle is completed) Bit 5 (EEWE): EEPROM Write Enable bit 0 : Write to the EEPROM is prohibited. 1 : Allows EEPROM write cycles Bit 4 (EEDF): EEPROM Detect Flag 0 : Write cycle is completed 1 : Write cycle is unfinished Bit 3 (EEPC): EEPROM power-down control bit 0 : Switch off the EEPROM 1 : EEPROM is operating Bits 2 ~ 0: 46 • Not used, set to “0” at all time Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.7.1.2 RC (128 Bytes EEPROM Address) When accessing the EEPROM data memory, the RC (128 bytes EEPROM address register) holds the address to be accessed. In accordance with the operation, the RD (128 bytes EEPROM Data register) holds the data to be written, or the data read, at the address in RC. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - EE_A6 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0 Bit 7: Not used, set to “0” at all time. Bits 6 ~ 0: 128 bytes EEPROM address 6.7.1.3 RD (256 Bytes EEPROM Data) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0 Bits 7 ~ 0: 128 bytes EEPROM data 6.7.2 Programming Step / Example Demonstration 6.7.2.1 Programming Step Follow these steps to write to or read data from the EEPROM: Step 1 Set the RB.EEPC bit to “1” to enable the EEPROM power. Step 2 Write the address to RC (128 bytes EEPROM address). 1. (a) Set the RB.EEWE bit to 1, if the write function is employed. (b) Write the 8-bit data value to be programmed in the RD (256 bytes EEPROM data) (c) Set the RB.WR bit to “1”, then execute the write function. 2. Set the RB.READ bit to “1”, after which, execute the read function. Step 3 Wait for the RB.EEDF or RB.WR to be cleared Step 4 For the next conversion, go to Step 2 as required. Step 5 If you want to save power, make sure the EEPROM data is not used by clearing the RB.EEPC. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 47 EM78F734N 8-Bit Microcontroller 6.7.2.2 Example Demonstration Programs ; Define the control register and write data to EEPROM RC == 0x0C RB == 0x0B RD == 0x0D Read == 0x07 WR == 0x06 EEWE == 0x05 EEDF == 0x04 EEPC == 0x03 BS RB, EEPC MOV A,@0x0A MOV RC,A BS RB, EEWE MOV A,@0x55 MOV RD,A BS RB,WR JBC RB,EEDF JMP $-1 ; Set the EEPROM power on ; Assign the address from EEPROM ; Enable the EEPROM write function ; Set the data for EEPROM ; Write value to EEPROM ; Check whether the EEPROM bit is completed or not 6.8 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consists of a 9-bit analog multiplexer, three control registers (AISR/R5 (Bank 2), ADCON/R6 (Bank 2), ADOC/R7 (Bank 2), two data registers (ADDH, ADDL/R8, R9) and an ADC with 12-bit resolution. The analog reference voltage (Vref) and analog ground are connected via separate input pins. The functional block diagram of the ADC is shown below. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDH and ADDL. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS2, ADIS1 and ADIS0. Figure 6-16 Functional Block Diagram of Analog-to-Digital Conversion 48 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.8.1 ADC Control Register (AISR/R5, ADCON/R6, ADOC/R7) 6.8.2 Bank 2 R5 AISR (ADC Input Select Register) The AISR register defines the ADC pins as analog input or as digital I/O. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE7 − ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bit 7 (ADE7): AD converter enable bit of P57 pin. 0 : Disable ADC7, P57 functions as I/O pin. 1 : Enable ADC7 to function as analog input pin Bit 6: Not used, set to “0” at all time. Bit 5 (ADE5): AD converter enable bit of P77 pin 0 : Disable ADC5, P77 functions as I/O pin 1 : Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P73 pin 0 : Disable ADC4, P73 functions as I/O pin 1 : Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P63 pin. 0 : Disable ADC3, P63 functions as I/O pin 1 : Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P62 pin. 0 : Disable ADC2, P62 functions as I/O pin 1 : Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P61 pin 0 : Disable ADC1, P61 functions as I/O pin 1 : Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P60 pin 0 : Disable ADC0, P60 functions as I/O pin 1 : Enable ADC0 to function as analog input pin The following table shows the priority of P60/AD0//INT. P60/AD0//INT Pin Priority Hight Medium Low /INT AD0 P60 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 49 EM78F734N 8-Bit Microcontroller 6.8.3 Bank 2 R6 ADCON (A/D Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Bit 7 (VREFS): Input source of the Vref of the ADC. 0 : Vref of the ADC is connected to the internal reference which is selected by Bank 2 R9<5,4> (default value), and the P50/VREF pin carries out the function of P50 1 : Vref of the ADC is connected to P50/VREF Bit 6 ~ Bit 5 (CKR1 ~ CKR0): Prescaler of oscillator clock rate of ADC CKR1/CKR0 Operation Mode Max. Operation Frequency 00 FOSC/4 4 MHz 01 FOSC 1 MHz 10 FOSC/16 8 MHz 11 FOSC/2 1 MHz Bit 4 (ADRUN): ADC starts to run 0 : Reset upon completion of AD conversion. This bit cannot be reset by software. 1 : A/D conversion is started. This bit can be set by software. Bit 3 (ADPD): ADC Power-down mode 0 : Switch off the resistor reference to save power even while the CPU is operating 1 : ADC is operating Bits 2~0 (ADIS2~ADIS0): AD Input Select Bits 50 • ADIS2 ADIS1 ADIS0 AD Input Pin 0 0 0 AD0 0 0 1 AD1 0 1 0 AD2 0 1 1 AD3 1 0 0 AD4 1 0 1 AD5 1 1 0 Reserve 1 1 1 AD7 Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.8.4 Bank 2 R7 ADOC (A/D Offset Calibration Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - PDE - - Bits 7~3: Not used, set to “0” at all time. Bit 2 (PDE): 1/2 VDD Power Detect Enable bit. 0: Disable Power Detect (Default) 1: Enable Power Detect. PDE ADIS2 ADIS1 ADIS0 AD Input Select 1 x x x 1/2VDD 0 × × × ADx Bits 1~0: Not used, set to “0” at all time. 6.8.5 ADC Data Buffer (ADDH, ADDL/R8, R9) When the A/D conversion is completed, the result is loaded to the ADDH, ADDL. The ADRUN bit is cleared, and the ADIF is set. 6.8.6 A/D Sampling Time The accuracy, linearity, and speed of the successive approximation A/D converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2µs for each KΩ of the analog source impedance and at least 2µs for the lowimpedance source. The maximum recommended impedance for analog source is 10KΩ at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion can be started. RCM[1:0]* Frequency (MHz) Sample and Hold Timing 00 4 8 x TAD 01 1 4 x TAD 10 8 12 x TAD 11 455k 2 x TAD *When using XT, LXT1, HXT1, HXT2 mode can also modify RCM[1:0] At Code Option Word 1 to set the Sample and Hold time. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 51 EM78F734N 8-Bit Microcontroller 6.8.7 A/D Conversion Time CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at the maximum frequency without sacrificing the accuracy of A/D conversion. For the EM78F734N, the conversion time per bit is 1µs. The table below shows the relationship between Tct and the maximum operating frequencies. Tct vs. Maximum Operation Frequency CKR0: CKR1 Operation Max. Operating Max. Conversion Max. Conversion Rate (12bit) Mode Frequency Rate Per Bit 00 Fosc/4 4 MHz 1 MHz (1 µs) (12+8)*1µs=20µs(50kHz) 01 Fosc 1 MHz 1 MHz (1µs) (12+4)*1µs=16µs(62.5kHz) 10 Fosc/16 8 MHz 0.5 MHz (2 µs) (12+12)*2µs=48µs(20.8kHz) 11 Fosc/2 1 MHz 0.5 MHz (2 µs) (12+4)*2µs=32µs(31.25kHz) NOTE The pin that is not used as analog input can be used as regular input or output pin. During conversion, do not perform output instruction to maintain precision for all of the pins. 6.8.8 A/D Operation during Sleep Mode In order to obtain a more accurate ADC value and reduced power consumption, the A/D conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillator, TCC, TC1, TC3, and A/D conversion. The AD Conversion is considered completed when: 1 ADRUN Bit of R6 Register is cleared to “0”. 2 Wake-up from A/D Conversion remains in operation during Sleep Mode. The result is fed to the ADDATA, ADOC when the conversion is completed. If the ADWE is enabled, the device will wake up. Otherwise, the A/D conversion will be shut off, no matter what the status of the ADPD bit is. 52 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.8.9 Programming Steps/Considerations 6.8.9.1 Programming Steps Follow the following steps to obtain data from the ADC: 1. Write to the 8 bits (ADE7, ADE5~ ADE0) on the R5 (AISR) register to define the characteristics of R6: Digital I/O, analog channels, and voltage reference pin. 2. Write to the R6/ADCON register to configure the AD module: a. Select A/D input channel ( ADIS1 ~ ADIS0 ). b. Define the A/D conversion clock rate ( CKR1 ~ CKR0 ). c. Select the input source of the VREFS of the ADC. d. Set the ADPD bit to “1” to begin sampling. 3. Set the ADWE bit, if the wake-up function is employed. 4. Set the ADIE bit, if the interrupt function is employed. 5. Put “ENI” instruction, if the interrupt function is employed. 6. Set the ADRUN bit to “1”. 7. Wait for wake-up or when ADRUN bit is cleared to “0”. 8. Read ADDATA, ADOC the conversion data register. 9. Clear the interrupt flag bit (ADIF) when A/D interrupt function occurs. 10. For the next conversion, repeat from Step 1 or Step 2 as required. At least 2 Tct is required before the next acquisition starts. NOTE To obtain an accurate value, it is necessary to avoid any data transition on the I/O pins during AD conversion. 6.8.9.2 Sample Demonstration Programs ; To define the General Registers R_0 == 0 ; Indirect addressing register PSW == 3 ; Status register PORT5 == 5 PORT6 == 6 RE== 0XE ; Wake-up control resister RF== 0XF ; Interrupt status register ; To define the Control Register IOC50 == 0X5 ; Control Register of Port 5 IOC60 == 0X6 ; Control Register of Port 6 C_INT== 0XF ; Interrupt Control Register Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 53 EM78F734N 8-Bit Microcontroller ; ADC Control Registers ADDATA == 0x8 AISR == 0x08 ADCON == 0x6 ; To define bits ; In ADCON ADRUN == 0x4 ADPD == 0x3 ; Program Starts ORG 0 JMP INITIAL ORG 0x30 (User program) CLR RF BS ADCON , ADRUN ; The contents are the results of ADC ; ADC output select register ; 7 6 5 4 3 2 1 0 VREFS CKR1 CKR0 ADRUN ADPD − ADIS1 ADIS0 ; ADC is executed as the bit is set ; Power Mode of ADC ; Initial address ; Interrupt vector ; To clear the ADIF bit ; To start to execute the next AD ; conversion if necessary RETI INITIAL: MOV A MOV AISR MOV A , @0B00000001 , A , @0B00001000 MOV ADCON , A En_ADC: MOV A , @0BXXXXXXX1 ; To define P60 as an input pin, and ; the others are dependent ; on applications IOW PORT6 MOV A , @0BXXXX1XXX ; Enable the ADWE wake-up function ; of ADC, “X” by application MOV RE MOV A , A , @0BXXXX1XXX ; To define P60 as an analog input ; ; ; ; To select P60 as an analog input channel, and AD power on To define P60 as an input pin and set clock rate at fosc/16 ; Enable the ADIE interrupt function ; of ADC, “X” by application IOW C_INT ENI BS ADCON , ADRUN ; Enable the interrupt function ; Start to run the ADC ; If the interrupt function is ; employed, the following three lines ; may be ignored POLLING: JBC ADCON , ADRUN JMP POLLING ; (User program) ; 54 • ; To check the ADRUN bit ; continuously ; ADRUN bit will be reset as the AD ; conversion is completed Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.9 Timer/Counter 1 Figure 6-17 Timer / Counter 1 Configuration In Timer mode, counting up is performed using an internal clock. When the contents of the up-counter matched the TC1DA, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into TC1DB by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after capture. The timer mode will operate with 16bits by setting TC1MOD to “1” In Counter mode, counting up is performed using an external clock input pin (TC1) and either rising or falling edge can be selected by TC1ES but both edges cannot be used. When the contents of the up-counter matched the TC1DA, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into TC1DB by setting TC1CAP to “1” and the TC1CAP is automatically cleared to “0” after capture. The counter mode will operate with 16bits by setting TC1MOD to “1”. In Capture mode, the pulse width, period and duty of the TC1 input pin are measured in this mode, which can be used to decode the remote control signal. The counter is free running by the internal clock. On the rising (falling) edge of TC1 pin input, the contents of counter is loaded into TC1DA, then the counter is cleared and interrupt is generated. On a falling (rising) edge of TC1 pin input, the contents of the counter are loaded into TC1DB. The counter is still counting, on the next rising edge of TC1 pin input, the contents of the counter are loaded into TC1DA, the counter is cleared and interrupt is generated again. If an overflow before the edge is detected, the FFH is loaded into TC1DA and the overflow interrupt is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TC1DA value is FFH. After an interrupt (capture to TC1DA or Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 55 EM78F734N 8-Bit Microcontroller overflow detection) is generated, capture and overflow detection are halted until TC1DA is read out. The capture mode will operate with 16bits by setting TC1MOD to “1”. Clock source Up-counter K-2 K-1 K 0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF0 1 2 3 TC1 pin input TC1DA K TC1DB TC1 interrupt n FF (overflow) m capture FE capture overflow Reading TC1DA Figure 6-5 (a) Timing Chart of 8 bits Capture Mode Figure 6-5 (b) Timing Chart of 16 bits Capture Mode 6.10 Timer/Counter 3 Figure 6-19 Timer/Counter 3 Mode Configuration 56 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Timer Mode In Timer mode, counting up is performed using the internal clock (rising edge trigger). When the contents of the up-counter matched with TCR3, interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. Counter Mode In Counter mode, counting up is performed using the external clock input pin (TC3 pin). When the contents of the up-counter matched with TCR3, interrupt is then generated and the counter is cleared. Counting up resumes after the counter is cleared. Programmable Divider Output (PDO) Mode In Programmable Divider Output (PDO) mode, counting up is performed using the internal clock. The contents of TCR3 are compared with the contents of the up-counter. The F/F output is toggled and the counter is cleared each time a match is found. The F/F output is inverted and output to /PDO pin. This mode can generate 50% duty pulse output. The F/F can be initialized by program and it is initialized to “0” during reset. A TC3 interrupt is generated each time the /PDO output is toggled. Clock Source Up-counter TCR3 0 1 2 3 n-1 n 0 1 n-1 n 0 1 n-1 n 0 1 2 n F/F /PDO Pin TC3 Interrupt Figure 6-20 PDO Mode Timing Diagram Pulse Width Modulation (PWM) Output Mode In Pulse Width Modulation (PWM) Output mode, counting up is performed using the internal clock. The contents of TCR3 are compared with the contents of the up-counter. The F/F is toggled when a match is found. While the counter is counting, the F/F is toggled again when the counter overflows, then the counter is cleared. The F/F output is inverted and output to the /PWM pin. A TC3 interrupt is generated each time an overflow occurs. TCR3 is configured as a 2-stage shift register and during output, will not switch until one output cycle is completed even if TCR3 is overwritten. Hence, the output can be changed continuously. Also, on the first time, TRC3 is shifted by setting TC3S to “1” after data is loaded to TCR3. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 57 EM78F734N 8-Bit Microcontroller Source Clock Up-counter TCR3 0 1 n-1 n n+1 n+2 FE FF n-1 0 n/n n n+1 n+2 FE FF n/m overflow match match 0 1 m-1 m m/m overflow Shift overwrite F/F /PWM 1 period TC4 Interrupt Figure 6-21 PWM Mode Timing Diagram 6.12 Oscillator 6.12.1 Oscillator Modes The device can be operated in four different oscillator modes, such as Internal RC oscillator mode (IRC), High Crystal oscillator mode (HXT), and Low Crystal oscillator mode (LXT). You can select one of such modes by programming OSC2, OCS1, and OSC0 in the Code Option register. The following table depicts how these four modes are defined. Oscillator Modes defined by OSC2 ~ OSC0 Mode OSC2 OSC1 OSC0 0 0 0 0 0 1 LXT1 (Low Crystal 1 oscillator mode) 0 1 0 Reserve 0 1 1 IRC mode, OSCO (P54) act as I/O pin 1 0 0 IRC mode, OSCO (P54) act as RCOUT pin 1 0 1 HXT2 (High Crystal 2 oscillator mode) 1 1 0 Reserve 1 1 1 1 XT (Crystal oscillator mode) 2 HXT1 (High Crystal 1 oscillator mode) 3 4 1 The Frequency range of HXT1 mode is 12 MHz ~ 6 MHz. 2 The Frequency range of XT mode is 6 MHz ~ 1 MHz. 3 The Frequency range of LXT1 mode is 1 MHz ~ 100kHz. 4 The Frequency range of HXT2 mode is 20 MHz ~ 12 MHz. In LXT, XT, HXT modes, OSCI and OSCO are implemented. They cannot be used as normal I/O pins. 58 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller In IRC mode, P55 is used as normal I/O pin. The maximum operating frequency of the crystal/resonator on the different VDD is shown below: Summary of Maximum Operating Speeds Conditions Two cycles with two clocks VDD Max Fxt. (MHz) 2.2 4.0 4.0 8.0 5.0 20.0 6.12.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78F734N can be driven by an external clock signal through the OSCI pin as illustrated below. OSCI Ext. Clock OSCO Figure 6-22 External Clock Input Circuit In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation as depicted in the following figure. The same thing applies to HXT mode or LXT mode. C1 OSCI Crystal OSCO RS C2 Figure 6-23 Crystal/Resonator Circuit Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 59 EM78F734N 8-Bit Microcontroller The following table provides the recommended values of C1 and C2. Since each resonator has its own attributes, you should refer to its specification for appropriate values of C1 and C2. A serial resistor RS, may be necessary for AT strip cut crystal or low frequency mode. Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode LXT1 (100K~1 MHz) Ceramic Resonators XT (1M~6 MHz) LXT1 (100K~1 MHz) Crystal Oscillator XT (1~6 MHz) HXT1 (6~12 MHz) HXT2 (12~20 MHz) 60 • Frequency C1(pF) C2(pF) 100kHz 60pF 60pF 200kHz 60pF 60pF 455kHz 40pF 40pF 1 MHz 30pF 30pF 1.0 MHz 30pF 30pF 2.0 MHz 30pF 30pF 4.0 MHz 20pF 20pF 100kHz 60pF 60pF 200kHz 60pF 60pF 455kHz 40pF 40pF 1 MHz 30pF 30pF 1.0 MHz 30pF 30pF 2.0 MHz 30pF 30pF 4.0 MHz 20pF 20pF 6.0 MHz 30pF 30pF 6.0 MHz 30pF 30pF 8.0 MHz 20pF 20pF 12.0 MHz 30pF 30pF 12.0 MHz 30pF 30pF 16.0 MHz 20pF 20pF Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.12.3 Internal RC Oscillator Mode EM78F734N offers a versatile internal RC mode with default frequency value of 4 MHz. Internal RC oscillator mode has other frequencies (455kHz, 1 MHz and 8 MHz) that can be set by Code Option (Word 1), RCM1 and RCM0 when COBS =0, or set by Bank 1 R8 Bits 7, 6 when COBS=1 . All these four main frequencies can be calibrated by programming the Code Option (Word 1) bits, C6~C0. The table describes a typical instance of the calibration. Internal RC Drift Rate (Ta=25°C, VDD=5 V ± 5%, VSS=0V) Drift Rate Internal RC Temperature (-40°C~85°C) Voltage (2.2V~5.5V) Process Total 455KHz ± 2% ± 3.5% ± 1% ± 6.5% 1 MHz ± 2% ± 3.5% ± 1% ± 6.5% 4 MHz ± 2% ± 3.5% ± 1% ± 6.5% 8 MHz ± 2% ± 3.5% ± 1% ± 6.5% 6.13 Code Option Register The EM78F734N has a Code Option Word that is not part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 0 Word 1 Word 2 Bit 12~Bit 0 Bit 12~Bit 0 Bit 12~Bit 0 6.13.1 Code Option Register (Word 0) Word 0 Bit Bit 12 Bit 11 Bit 10 Mnemonic HLP Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NRHL NRE RESETEN - - ENWDT OSC2 OSC1 OSC0 PR2 PR1 PR0 1 Low 8/fc Disable Enable - - Enable High High High High High High 0 High 32/fc Enable Disable - - Disable Low Low Low Low Low Low default 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit 12 (HLP): Power consumption selection. 0: High power consumption, applies to working frequency above 400kHz (default) 1: Low power consumption, applies to working frequency at 400kHz or below 400kHz Bit 11 (NRHL): Noise rejection high/low pulse define bit. INT pin is falling edge trigger. 1 : Pulses equal to 8/fc [s] is regarded as signal 0 : Pulses equal to 32/fc [s] is regarded as signal (default) Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 61 EM78F734N 8-Bit Microcontroller Bit 10 (NRE): Noise rejection enable. INT pin is falling edge trigger. 1: Disable noise rejection 0: Enable noise rejection (default) Bit 9 (RESETEN): Reset Pin Enable Bit 1 : Enable, P83//RESET=>RESET pin. 0 : Disable, P83//RESET=>P83 (default) Bit 8 ~ 7: Not used, always set to “0” Bit 6 (ENWDT): Watchdog timer enable bit 1 : Enable 0 : Disable Bit 5 ~ 3 (OSC2 ~ OSC0): Oscillator Mode Selection bits Mode OSC2 OSC1 OSC0 0 0 0 0 0 1 1 XT (Crystal oscillator mode) 2 HXT1 (High Crystal 1 oscillator mode) 3 LXT1 (Low Crystal 1 oscillator mode) 0 1 0 Reserve 0 1 1 IRC mode, OSCO (P54) act as I/O pin 1 0 0 IRC mode, OSCO (P54) act as RCOUT pin 1 0 1 HXT2 (High Crystal 2 oscillator mode) 1 1 0 Reserve 1 1 1 4 1 The Frequency range of HXT1 mode is 12 MHz ~ 6 MHz. 2 The Frequency range of XT mode is 6 MHz ~ 1 MHz. 3 The Frequency range of LXT1 mode is 1 MHz ~ 100kHz. 4 The Frequency range of HXT2 mode is 20 MHz ~ 12 MHz. Bit 2 ~ 0 (PR2 ~ PR0): Protect Bit. PR2~PR0 are protect bits, protect type is as follows: 62 • PR2 PR1 PR0 Protect 1 1 1 Enable 0 0 0 Disable Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.13.2 Code Option Register (Word 1) Word 1 Bit Bit 12 Bit 11 Bit 10 Mnemonic COBS TCEN Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 C6 C5 C4 C3 C2 C1 C0 Bit 3 Bit 2 Bit 1 Bit 0 RCM1 RCM0 LVR1 LVR0 1 High TCC High High High High High High High High High High High 0 Low P77 Low Low Low Low Low Low Low Low Low Low Low default 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 12 (COBS): Code Option Bit Selection 0 : IRC frequency select for code option (default) 1 : IRC frequency select internal register by Bank 1 R8(7,6) Bit 11 (TCEN): TCC enable bit 0 : P77/TCC is set as P77 1 : P77/TCC is set as TCC Bit 10 ~ 4 (C6 ~ C0): Internal RC mode calibration bits. (IRC frequency auto calibration) Bit 3 ~ 2 (RCM1 ~ RCM0): RC mode selection bits RCM 1 0 0 1 1 RCM 0 0 1 0 1 *Frequency (MHz) 4 1 8 455k Bit 1 ~ 0 (LVR1 ~ LVR0): Low voltage reset enable bits LVR1 LVR0 0 0 0 1 1 0 1 1 Reset Level NA 2.5V 2.9V 3.2V Release Level NA 2.6V 3.0V 3.3V Note: LVR1, LVR0=“0, 0”: LVR disabled, power-on reset point of EM78F734N is 2.4V. LVR1, LVR0=“0, 1”: If Vdd < 2.9V, the EM78F734N will reset. LVR1, LVR0=“1, 0”: If Vdd < 3.2V, the EM78F734N will reset. LVR1, LVR0=“1, 1”: If Vdd < 3.9V, the EM78F734N will reset. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 63 EM78F734N 8-Bit Microcontroller 6.13.3 Code Option Register (Word 2) Word 2 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic SC4 SC3 SC2 SC1 SC0 EFTIM - - SFS IRE - - - 1 High High High High High 20MHz - - 128kHz Enable - - - 0 Low Low Low Low Low 10MHz - - 16kHz Disable - - - Default 0 0 0 0 0 1 0 0 0 0 0 0 0 Bits 12 ~ 8 (SC4 ~ SC0): Calibrator of sub frequency (WDT frequency auto calibration) Bit 7 (EFTIM): EFT improvement. If the MCU is at VDD=5V with working frequency of <12 MHz, or at VDD=3V with working frequency of <6 MHz, enabling this function can improve the performance of the electrical fast transient (EFT) test. If the MCU is at VDD=5V and the working frequency is >12 MHz, choose EFTIM=1 0: 10 MHz 1: 20 MHz Bits 6 ~ 5: Not used, always set to “0” Bits 4 (SFS): Sub-frequency select. 0: 16kHz (WDT frequency) 1: 128kHz Bit 3 (IRE) : IRC Regulator Enable bit 0: Disable regulator for saving power but more error of IRC. 1: Enable regulator for improving IRC accurately but more power consumed. Bits 2 ~ 0: 64 • Not used, always set to “0” Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.14 Power-on Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply stays has stabilized. The EM78F734N has an on-chip Power-on Voltage Detector (POVD) with a detecting level of 2.0V. It will work well if Vdd can rise quickly enough (50ms or less). In many critical applications, however, extra devices are still required to assist in solving power-up problems. 6.15 External Power-on Reset Circuit The circuit shown in Figure 6-24 uses an external RC to generate a reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is ± 5µA, it is recommended that R should not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) functions as a short circuit at the moment of power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET. Vdd R /RESET D Rin C Figure 6-24 External Power-up Reset Circuit Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 65 EM78F734N 8-Bit Microcontroller 6.16 Residue-Voltage Protection When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Figure 6-25 and Figure 6-26 show how to build a residue-voltage protection circuits. Vdd Vdd 33K Q1 10K /RESET 40K 1N4684 Figure 6-25 Circuit 1 for the Residue Voltage Protection Vdd Vdd R1 Q1 /RESET 40K R2 Figure 6-26 Circuit 2 for the Residue Voltage Protection 66 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 6.17 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) "JMP", "CALL", "RET", "RETL", "RETI" commands are executed with one instruction cycle, the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were tested to be true, are executed within two instruction cycles. The instructions that are written to the program counter also take two instruction cycles. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on the I/O register. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 67 EM78F734N 8-Bit Microcontroller Instruction Set Table: The following symbols are used in the following table: “R” Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. “b” Bit field designator that selects the value for the bit located in the register R and which affects the operation. “K” 8 or 10-bit constant or literal value Mnemonic Operation NOP Status Affected No Operation None DAA Decimal Adjust A CONTW A → CONT None C SLEP 0 → WDT, Stop oscillator T, P WDTC 0 → WDT T, P IOW R A → IOCR None ENI Enable Interrupt None DISI Disable Interrupt None RET [Top of Stack] → PC None 1 RETI [Top of Stack] → PC, Enable Interrupt None CONTR CONT → A None IOR R IOCR → A None MOV R,A A→R None CLRA 0→A Z CLR R 0→R Z SUB A,R R-A → A Z, C, DC SUB R,A R-A → R Z, C, DC DECA R R-1 → A Z DEC R R-1 → R Z OR A,R A∨R→A Z 1 OR R,A A∨R→R Z AND A,R A&R→A Z AND R,A A&R→R Z XOR A,R A⊕R→A Z XOR R,A A⊕R→R Z ADD A,R A+R→A Z, C, DC ADD R,A A+R→R Z, C, DC MOV A,R R→A MOV R,R R→R Z COMA R /R → A Z COM R /R → R Z INCA R R+1 → A Z R+1 → R Z INC R 1 68 • Z This instruction is applicable to IOC5~IOC7, IOCA ~ IOCF only. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Mnemonic Operation Status Affected DJZA R R-1 → A, skip if zero None DJZ R R-1 → R, skip if zero None RRCA R R(n) → A(n-1), R(0) → C, C → A(7) C RRC R R(n) → R(n-1), R(0) → C, C → R(7) C RLCA R R(n) → A(n+1), R(7) → C, C → A(0) C RLC R R(n) → R(n+1), R(7) → C, C → R(0) C SWAPA R R(0-3) → A(4-7), R(4-7) → A(0-3) None SWAP R R(0-3) ↔ R(4-7) None JZA R R+1 → A, skip if zero None JZ R R+1 → R, skip if zero None BC R,b 0 → R(b) None BS R,b 1 → R(b) None JBC R,b if R(b)=0, skip None JBS R,b if R(b)=1, skip None CALL k PC+1 → [SP], (Page, k) → PC None JMP k (Page, k) → PC None MOV A,k k→A None OR A,k A∨k→A 2 3 Z AND A,k A&k→A Z XOR A,k A⊕k→A Z RETL k k → A, [Top of Stack] → PC SUB A,k k-A → A Z, C, DC ADD A,k k+A → A Z, C, DC BANK k K → R4(7:6) None LCALL k Next instruction : k kkkk kkkk kkkk PC+1→[SP], k→PC4 None LJMP k Next instruction : k kkkk kkkk kkkk k→PC4 None TBRD R If Bank 3 R6.7=0, machine code (7:0) → R Else machine code (12:8) → R(4:0), R(7:5)=(0,0,0) None 2 3 None This instruction is not recommended for interrupt status register operation. This instruction cannot operate under interrupt status register. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 69 EM78F734N 8-Bit Microcontroller 7 Timing Diagrams Figure 7-1 AC Test Timing Diagram Reset Timing (CLK=”0”) Figure 7-2 Reset Timing Diagram TCC Input Timing (CLKS=”0”) Figure 7-3 TCC Input Timing Diagram 70 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller 8 Absolute Maximum Ratings EM78F734N Items Rating Temperature under bias -40°C to 85°C Storage temperature -65°C to 150°C Working voltage 2.2 to 5.5V Working frequency DC to 20 MHz* Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.3V to Vdd+0.5V Note: *These parameters are theoretical values and have not been tested. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 71 EM78F734N 8-Bit Microcontroller 9 DC Electrical Characteristics VDD=5.0V, VSS=0V, Ta=25°C Symbol Parameter Crystal: VDD to 3V Fxt Crystal: VDD to 5V IRC: VDD to 5 V Condition Two cycles with two clocks Min. Typ. DC - 4 MHz DC - 20 MHz 4 MHz, 455kHz, 1 MHz,,8 MHz F±30% F Max. Unit F±30% Hz - - ±1 µA OSCI in RC mode 3.9 4 4.1 V OSCI in RC mode 1.7 1.8 1.9 V Input Leakage Current for input pins VIN = VDD, VSS -1 0 1 µA VIH1 Input High Voltage (Schmitt trigge ) Ports 5, 6, 7, 8 - 0.7VDD (2.8V) - V VIL1 Input Low Voltage (Schmitt trigger) Ports 5, 6, 7, 8 - 0.3VDD (2.2V) - V VIHT1 Input High Threshold Voltage (Schmitt Trigger ) /RESET - 0.7VDD - V VILT1 Input Low Threshold Voltage (Schmitt trigger ) /RESET - 0.3VDD - V VIHT2 Input High Threshold Voltage (Schmitt Trigger ) TCC, INT - 0.7VDD - V VILT2 Input Low Threshold Voltage (Schmitt Trigger ) TCC, INT - 0.3VDD - V VIHX1 Clock Input High Voltage OSCI in crystal mode 2.9 3.0 3.1 V VILX1 Clock Input Low Voltage OSCI in crystal mode 1.7 1.8 1.9 V IIL Input Leakage Current for input pins VIN = VDD, VSS VIHRC Input High Threshold Voltage (Schmitt Trigger ) VILRC Input Low Threshold Voltage (Schmitt Trigger ) IIL Note: * The parameters are theoretical and have not been tested or verified. * Data in the Minimum, Typical, Maximum (“Min.”, “Typ.”, "Max.”) column are based on hypothetical results at 25°C. These data are for design guidance only. 72 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller (Continuation) Symbol Parameter Condition Min. Typ. Max. Unit IOH1 High Drive Current (Ports 5, 6, 7, 8) VOH = 0.9VDD -2.5 - - mA IOL1 Low Sink Current (Ports 5, 6, 7, 8) VOL = 0.1VDD 10 - - mA IPH Pull-high current Pull-high active, input pin at VSS - - -95 µA IPL Pull-low current Pull-low active, input pin at Vdd - - 40 µA LVR1 Low voltage reset level 1 (2.6V) Ta = 25°C 2.13 2.6 3.07 V Ta = -40°C ~ 85°C 1.72 2.6 3.46 V LVR2 Low voltage reset level 1 (3.0V) Ta = 25°C 2.48 3.0 3.51 V Ta = -40°C ~ 85°C 2.05 3.0 3.93 V LVR3 Low voltage reset level 1 (3.3V) Ta = 25°C 2.72 3.3 3.86 V Ta = -40°C ~ 85°C 2.25 3.3 4.3 V ISB1 Power down current All input and I/O pins at VDD, output pin floating, WDT disabled - - 2 µA ISB2 Power down current All input and I/O pins at VDD, output pin floating, WDT enabled - - 5 µA ICC1 Operating supply current at two clocks /RESET= 'High', Fosc=455kHz (IRC type), Voltage = 3V, output pin floating, WDT enabled - 96 - µA ICC2 Operating supply current at two clocks /RESET= 'High', Fosc=1MHz (IRC type), Voltage = 3V, output pin floating, WDT enabled - 170 - µA ICC3 Operating supply current at two clocks /RESET= 'High', Fosc=4 MHz (Crystal type), output pin floating, WDT enabled - 1.3 - mA ICC4 Operating supply current at two clocks /RESET= 'High', Fosc=10 MHz (Crystal type), output pin floating, WDT enabled - 3.25 - mA NOTE The above parameters are theoretical values only and have not been tested or verified. Data under the “Min.”, “Typ.”, and “Max.” (Minimum, Typical, and Maximum) columns are based on hypothetical results at 25°C. These data are for design reference only. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 73 EM78F734N 8-Bit Microcontroller 9.1 Data EEPROM Electrical Characteristics Symbol Tprog Parameter Condition Erase/Write cycle time Vdd = 2.2V~ 5.5V Temperature = -40°C ~ 85°C Treten Data Retention Tendu Endurance time Min. Typ. Max. Unit - - - ms - 10 - Years - 100K - Cycles 9.2 Program Flash Memory Electrical Characteristics Symbol Tprog Parameter Condition Erase/Write cycle time Vdd = 5.0V Temperature = -40°C ~ 85°C Treten Data Retention Tendu Endurance time Min. Typ. Max. Unit - - - ms - 10 - Years - 100K - Cycles 9.3 A/D Converter Characteristics VDD=5.0V, VSS=0V, Ta=25°C Type Parameter Symbol Test Conditions Unit Min. Typ. Max. Vdd Operating Range For 5.5v Fs=100KHz, Fin=2KHz, For 2.2v Fs=50KHz, Fin=1KHz VREFT Ivdd Current Consumption Iref 74 • VREFT= Vdd=5.5v, Fs=100KHz, Fin=2KHz 2.2 - 5.5 V 2.2 - Vdd V - - 0.5 mA - - 50 uA Standby Current Isb - - 0.1 uA ZAI ZAI - - 10k ohm SNR SNR VREFT= Vdd=3.3v, Fs=100KHz, Fin=2KHz 70 - - dBc THD THD VREFT= Vdd=3.3v, Fs=100KHz, Fin=2KHz - - -70 dBc SNDR SNDR VREFT= Vdd=3.3v, Fs=100KHz, Fin=2KHz 68 - - dBc Worst Harmonic WH VREFT= Vdd=3.3v, Fs=100KHz, Fin=2KHz - - -73 dBc SFDR SFDR VREFT= Vdd=3.3V, Fs=100KHz, Fin=2kHz 73 - - dBc Offset Error OE VREFT= Vdd=3.3V, Fs=100kHz - - +/-4 LSB Gain Error GE VREFT= Vdd=3.3V, Fs=100kHz - - +/-8 LSB DNL DNL VREFT= Vdd=3.3V, Fs=100kHz, Fin=2kHz - - +/-1 LSB INL INL VREFT= Vdd=3.3V, Fs=100kHz, Fin=2kHz - - +/-4 LSB Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller Fs1 Vdd=2.7~5.5V, Fin=2kHz 100 - - K SPS Fs2 Vdd=2.2~2.7V, Fin=1kHz 50 - - K SPS PSRR VREFT=2.2V, SVREF=”0”or”1”, Vdd=2.2V ~ 5.5V, Fs=50kHz, Vin=0V ~ 2.2V - - 2 LSB Conversion Rate Power Supply Rejection Ratio 1 Note: These parameters are hypothetical (not tested) and are provided for design reference only. 2 There is no current consumption when ADC is off other than minor leakage current. 3 The A/D conversion result will not decrease with an increase in the input voltage, and has no missing code. 4 These parameters are subject to change without prior notice. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 75 EM78F734N 8-Bit Microcontroller 10 AC Electrical Characteristics EM78F734N, 0 ≤ Ta ≤ 70°C, VDD=5V, VSS=0V -40 ≤ Ta ≤ 85°C, VDD=5V, VSS=0V Symbol Dclk Tins Parameter Conditions Min. Typ. Max. Unit Input CLK duty cycle − 45 50 55 % Instruction cycle time Crystal type 100 − DC ns RC type 500 − DC ns (CLKS="0") Ttcc TCC input period − (Tins+20)/N* − − ns Tdrh Device reset hold time − 11.8 16.8 21.8 ms Trst /RESET pulse width Ta = 25°C 2000 − − ns Twdt Watchdog timer period Ta = 25°C 11.8 16.8 21.8 ms Tset Input pin setup time − − 0 − ns Thold Input pin hold time − − 20 − ns Tdelay Output pin delay time Cload=20pF − 50 − ns Note: These parameters are theoretical values and have not been tested. Such parameters are for design reference only. Data in the Minimum, Typical, Maximum (“Min.”, “Typ.”, ”Max.”) columns are based on characterization results at 25°C. * N = selected prescaler ratio 76 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller APPENDIX A Package Type Flash MCU Package Type Pin Count Package Size EM78F734ND20 PDIP 20 300 mil EM78F734NSO20 SOP 20 300 mil EM78F734ND18 PDIP 18 300 mil EM78F734NSO18 SOP 18 300 mil EM78F734ND16 PDIP 16 300 mil EM78F734NSO16 SOP 16 300 mil EM78F734NSS16 SSOP 16 150 mil These are Green products which do not contain hazardous substances and comply with the third edition of Sony SS-00259 standard. Pb contents should be less than 100ppm and complies with Sony specifications. Part No. EM78F734NS/J Electroplate type Pure Tin Ingredient (%) Sn:100% Melting point (°C) 232°C Electrical resistivity (µΩ cm) 11.4 Hardness (hv) 8~10 Elongation (%) >50% Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 77 EM78F734N 8-Bit Microcontroller B Package Information B.1 EM78F734ND16 300mil Figure B-1 EM78F734N 16-Pin PDIP Package Type 78 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller B.2 EM78F734NSO16 300mil Figure B-2 EM78F734N 16-Pin SOP Package Type Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 79 EM78F734N 8-Bit Microcontroller B.3 EM78F734NSS16 150mil Package Type : SSOP-16L EMC(mm ) Symbal A A1 A2 b b1 c c1 D E E1 L e θ Min 1.35 0.10 0.20 0.20 0.18 0.18 4.80 5.79 3.81 0.41 0° Normal 1.63 0.18 0.25 0.20 4.90 5.99 3.91 0.64 .025BASIC - Max 1.75 0.25 1.50 0.30 0.28 0.25 0.23 5.00 6.20 3.99 1.27 8° TITLE: SSOP 16L (150MIL)PACKAGE OUTLINE DIMENSION File : SSOP 16L Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Figure B-3 EM78F734N 16-Pin SSOP Package Type 80 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller B.4 EM78F734ND18 300mil Figure B-4 EM78F734N 18-Pin PDIP Package Type Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 81 EM78F734N 8-Bit Microcontroller B.5 EM78F734NSO18 300mil Symbal A A1 b c E H D L e θ Min 2.350 0.102 Normal Max 2.650 0.300 0.406(TYP) 0.230 7.400 10.000 11.350 0.406 0 0.838 1.27(TYP) 0.320 7.600 10.650 11.750 1.270 8 Figure B-5 EM78F734N 18-Pin SOP Package Type 82 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller B.6 EM78F734ND20 300mil Symbal A A1 A2 c D E1 E eB B B1 L e θ Min 0.381 3.175 0.203 25.883 6.220 7.370 8.510 0.356 1.143 3.048 0 Normal Max 4.450 3.302 3.429 0.254 0.356 26.060 26.237 6.438 6.655 7.620 7.870 9.020 9.530 0.457 0.559 1.524 1.778 3.302 3.556 2.540(TYP) 15 A1 A2 E TITLE: PDIP-20L 300MIL PACKAGE OUTLINE DIMENSION File : D20 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Figure B-6 EM78F734N 20-Pin PDIP Package Type Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 83 EM78F734N 8-Bit Microcontroller B.7 EM78F734NSO20 300mil Figure B-7 EM78F734N 20-Pin SOP Package Type 84 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) EM78F734N 8-Bit Microcontroller C Quality Assurance and Reliability Test Category Test Conditions Solder temperature=245±5°C, for 5 seconds up to the stopper using a rosin-type flux Solderability Remarks – Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles Step 2: Bake at 125°C, TD (endurance)=24 hrs Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs Step 4: IR flow 3 cycles Pre-condition (Pkg thickness ≥ 2.5mm or 3 Pkg volume ≥ 350mm ----225±5°C) For SMD IC (such as SOP, QFP, SOJ, etc) (Pkg thickness ≤ 2.5mm or 3 Pkg volume ≤ 350mm ----240±5°C) Temperature cycle test -65°C (15mins)~150°C (15mins), 200 cycles – Pressure cooker test TA =121°C, RH=100%, pressure=2 atm, TD (endurance)= 96 hrs – High temperature / High humidity test TA=85°C , RH=85%，TD (endurance) = 168 , 500 hrs – High-temperature storage life TA=150°C, TD (endurance) = 500, 1000 hrs – High-temperature operating life TA=125°C, VCC = Max. operating voltage, TD (endurance) = 168, 500, 1000 hrs – Latch-up TA=25°C, VCC = Max. operating voltage, 150mA/20V – ESD (HBM) TA=25°C, ≥∣± 3KV∣ IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, ESD (MM) TA=25°C, ≥ ∣± 300V∣ IP_PS,OP_PS,IO_PS, VDD-VSS(+),VDD_VSS (-) mode C.1 Address Trap Detect An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise-caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program. Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice) • 85 EM78F734N 8-Bit Microcontroller 86 • Product Specification (V1.0) 05.13.2014 (This specification is subject to change without further notice)