PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 1 -P FEATURES IR3895 DESCRIPTION Single 5V to 21V application Wide Input Voltage Range from 1.0V to 21V with external Vcc Output Voltage Range: 0.5V to 0.86* Vin Enhanced Line/Load Regulation with Feed‐Forward Programmable Switching Frequency up to 1.5MHz Internal Digital Soft‐Start/Soft‐Stop Enable input with Voltage Monitoring Capability Thermally Compensated Current Limit with robust hiccup mode over current protection Smart internal LDO to improve light load and full load efficiency External Synchronization with Smooth Clocking Enhanced Pre‐Bias Start‐Up Precision Reference Voltage (0.5V+/‐0.5%) with margining capability Vp for Tracking Applications (source/sink capability ±16A) The IR3895 SupIRBuckTM is an easy‐to‐use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3895 a space‐efficient solution, providing accurate power delivery. IR3895 is a versatile regulator which offers programmable of switching frequency and the fixed internal current limit while operates in wide input and output voltage range. The switching frequency is programmable from 300kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre‐Bias startup, thermally compensated current limit, over voltage protection and thermal shutdown to give required system level security in the event of fault conditions. APPLICATIONS Integrated MOSFET drivers and Bootstrap Diode Netcom Applications Thermal Shut Down Embedded Telecom Systems Programmable Power Good Output with tracking capability Server Applications Storage Applications Monotonic Start‐Up Distributed Point of Load Power Architectures Operating temp: ‐40 C < Tj < 125 C o o Small Size: 5mm x 6mm PQFN Lead‐free, Halogen‐free and RoHS Compliant BASIC APPLICATION Figure 1: IR3895 Basic Application Circuit 1 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Figure 2:IR3895 Efficiency PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 2 -P ORDERING INFORMATION IR3895 ― Package M Tape & Reel Qty 750 Part Number IR3895MTR1PBF M 4000 IR3895MTRPBF PBF – Lead Free TR/TR1 – Tape and Reel M – Package Type PIN DIAGRAM 5m x 6mm POWER QFN (TOP VIEW) Fb Vref Comp Gnd Rt/SyncS_Ctrl PGood JA 30C / W J - PCB 2C / W 2 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 IR3895 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 3 -P IR3895 BLOCK DIAGRAM Vin Vcc/ LDO_Out VLDO_Ref LDO Gnd UVcc UVcc + VCC TSD POR FAULT CONTROL OV DCM Comp POR VREF Vref 0.5V Boot THERMAL SHUT DOWN OC PVin FAULT + HDrv + E/A + - Vp 0.15V HDin FB Fb GATE DRIVE LOGIC Intl_SS S_Ctrl SOFT START Vin FAULT Rff FAULT SW VCC LDrv LDin SSOK CONTROL LOGIC VREF POR Vp Enable UVEN UVcc OV PGnd DCM UVEN POR POR OC VREF OVER VOLTAGE PROTECTION OV ZERO CROSSING COMPARATOR OVER CURRENT PROTECTION Vp Vsns Rt/Sync PGood Figure 3: IR3895 Simplified Block Diagram 3 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 4 -P IR3895 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 Vref Internal reference voltage, it can be used for margining operation also. In normal and sequencing mode operation, Vref is left floating. A 1nF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. 3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation. 4 Gnd Signal ground for internal reference and control circuitry. 5 Rt/Sync Multi‐function pin to set switching frequency. Use an external resistor from this pin to Gnd to set the free‐running switching frequency. An external clock signal can be connected to this pin through a diode so that the device’s switching frequency is synchronized with the external clock. 6 S_Ctrl Soft start/stop control. A high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. Pull this pin to Vcc if this function is not used. 7 PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to the voltage lower than or equal to the Vcc. 8 Vsns Sense pin for over‐voltage protection and PGood. It is optional to tie this pin to FB pin directly instead of using a resistor divider from Vout. 9 Vin Input voltage for Internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. 10 Vcc/LDO_Out Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum 2.2µF cap from this pin to PGnd. 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW 13 PVin Input voltage for power stage. 14 Boot Supply voltage for high side driver, a 100nF capacitor should be connected between this pin and SW pin. 15 Enable Enable pin to turn on and off the device, if this pin is connected to PVin pin through a resistor divider, input voltage UVLO can be implemented. 16 Vp Input to error amplifier for tracking purposes. In the normal operation, it is left floating and no external capacitor is required. In the sequencing or the tracking mode operation, an external signal can be applied as the reference. 17 Gnd Signal ground for internal reference and control circuitry. Switch node. This pin is connected to the output inductor. 4 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 5 -P IR3895 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin ‐0.3V to 25V Vcc/LDO_Out ‐0.3V to 8V (Note 2) Boot ‐0.3V to 33V SW ‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) Boot to SW ‐0.3V to VCC + 0.3V (Note 1) S_Ctrl, PGood ‐0.3V to VCC + 0.3V (Note 1) Other Input/Output Pins ‐0.3V to +3.9V PGnd to Gnd ‐0.3V to +0.3V Storage Temperature Range ‐55°C to 150°C Junction Temperature Range ‐40°C to 150°C (Note 2) ESD Classification (HBM JESD22‐A114) 2kV Moisture Sensitivity Level JEDEC Level 3@260°C Note 1: Must not exceed 8V Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C 5 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 6 -P IR3895 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN SYMBOL MIN MAX Input Voltage Range* PVin 1.0 21 Input Voltage Range** Vin 6.8 21 Supply Voltage Range*** VCC 4.5 7.5 UNITS V Supply Voltage Range Boot to SW 4.5 7.5 Output Voltage Range VO 0.5 0.86xVin Output Current Range IO 0 ±16 A Switching Frequency F S 300 1500 kHz Operating Junction Temperature TJ ‐40 125 °C *Maximum SW node voltage should not exceed 25V. **For internally biased single rail operation. *** Vcc/LDO_out can be connected to an external regulated supply. If so, the Vin input should be connected to Vcc/LDO_out pin. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < TJ < 125°C. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT W Power Stage Top Switch Rds(on)_Top Vin = 12V, VO = 1.2V, IO = 16A, Fs = 600kHz, L = 0.4uH, Vcc = 6.4V (internal LDO), Note 4 VBoot ‐ Vsw= 6.4V, IO = 16A, Tj =25°C Bottom Switch Bootstrap Diode Forward Voltage Rds(on)_Bot Vcc = 6.4V, IO = 16A, Tj =25°C Power Losses PLOSS SW Leakage Current Dead Band Time 3.4 9.6 13.5 4.2 6.1 200 300 500 mV SW = 0V, Enable = 0V SW = 0V, Enable = high, Vp = 0V 1 µA Note 4 20 ns Iin(Standby) EN = Low, No Switching 100 µA Iin(Dyn) EN = High, Fs = 600kHz, Vin = PVin = 21V 20 23 6.4 6.7 I(Boot) = 15mA ISW Tdb mΩ Supply Current Vin Supply Current (standby) Vin Supply Current (dynamic) mA VCC LDO Output Vcc Output Voltage Vin(min) = 6.8V, Icc = 0‐50mA, Cload = 2.2uF, DCM = 0 6.0 Vin(min) = 6.8V, Icc = 0‐50mA, Cload = 2.2uF, DCM = 1 4.0 4.4 4.85 V VCC Dropout Vcc_drop Icc=50mA,Cload=2.2uF 0.8 V Short Circuit Current Ishort 70 mA 6 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 7 -P PARAMETER IR3895 SYMBOL CONDITIONS MIN TYP MAX UNIT Zero‐crossing Comparator Delay Tdly_zc Note 4 256/Fs s Zero‐crossing Comparator Offset Vos_zc Note 4 ‐4 0 4 mV 1.0 V Oscillator Rt Voltage Vrt Frequency Range Fs Rt = 80.6K 270 300 330 Rt = 39.2K 540 600 660 Rt = 15.0K 1350 1500 1650 Vin = 6.8V, Vin slew rate max = 1V/µs, Note 4 1.02 Vin = 12V, Vin slew rate max = 1V/µs, Note 4 1.80 Vin = 21V, Vin slew rate max = 1V/µs, Note 4 3.15 Vcc=Vin=5V,For external Vcc operation, Note 4 0.75 Ramp Amplitude Vramp kHz Vp‐p Ramp Offset Ramp(os) Note 4 0.16 V Min Pulse Width Tmin(ctrl) Note 4 60 ns Max Duty Cycle Dmax 86 % Fixed Off Time Toff 200 250 ns Fs = 300kHz, PVin = Vin = 12V Note 4 Sync Frequency Range Fsync 270 1650 kHz Sync Pulse Duration Tsync 100 200 ns Sync Level Threshold High 3 Low 0.6 VFb – Vref, Vref = 0.5V ‐1.5 +1.5 Vos_Vp VFb – Vp, Vp = 0.5V,Vref=0 ‐1.5 +1.5 Input Bias Current IFb(E/A) ‐1 +1 Input Bias Current IVp(E/A) 0 +4 Sink Current Isink(E/A) 0.4 0.85 1.2 mA Isource(E/A) 4 7.5 11 mA SR Note 4 7 12 20 V/µs GBWP Note 4 20 30 40 MHz Gain Note 4 100 110 120 dB V Error Amplifier Input Offset Voltage Source Current Vos_Vref Slew Rate Gain‐Bandwidth Product DC Gain % µA Maximum output Voltage Vmax(E/A) 1.7 2.0 2.3 V Minimum output Voltage Vmin(E/A) 100 mV 0 1.2 V Vref and Vp pin floating 0.5 V Common Mode input Voltage Reference Voltage Feedback Voltage 7 Vfb AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 8 -P PARAMETER Accuracy SYMBOL CONDITIONS IR3895 MIN TYP MAX 0°C < Tj < 70°C ‐0.5 +0.5 ‐40°C < Tj < 125°C, Note 3 ‐1.0 +1.0 Vref Margining Voltage Vref_marg 0.4 1.2 Sink Current Isink_Vref Vref = 0.6V 12.7 16.0 19.3 Source Current Isrc_Vref Vref = 0.4V 12.7 16.0 19.3 0.15 0.4 Vref Comparator Threshold Vref_disable Vref pin connected externally Vref_enable UNIT % V µA V Soft Start/Stop Soft Start Ramp Rate Ramp (SS_start) 0.16 0.2 0.24 Soft Start Ramp Rate Ramp (SS_stop) ‐0.24 ‐0.2 ‐0.16 High 2.4 Low 0.6 Vsns Rising, 0.4V < Vref < 1.2V 85 90 95 % Vref Vsns Rising, Vref < 0.1V 85 90 95 % Vp Vsns Falling, 0.4V < Vref < 1.2V 80 85 90 % Vref Vsns Falling, Vref < 0.1V 80 85 90 % Vp 1.28 ms S_Ctrl Threshold mV/µs V Power Good PGood Turn on Threshold PGood Lower Turn off Threshold VPG(on) VPG(lower) PGood Turn on Delay VPG(on)_Dly Vsns Rising, see VPG(on) PGood Upper Turn off Threshold VPG(upper) Vsns Rising, 0.4V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp PGood Comparator Delay VPG(comp)_ Dly Vsns < VPG(lower) or Vsns > VPG(upper) 1 2 3.5 µs PGood Voltage Low PG(voltage) IPgood = ‐5mA 0.5 V Tracker Comparator Upper Threshold VPG(tracker _upper) Vp Rising, Vref < 0.1V 0.4 Tracker Comparator Lower Threshold VPG(tracker _lower) Vp Falling, Vref < 0.1V 0.3 Tracker Comparator Delay Tdelay(track er) Vp Rising, Vref < 0.1V,see VPG(tracker_upper) 1.28 Vcc‐Start Threshold VCC_UVLO_ Start Vcc Rising Trip Level 4.0 4.2 4.4 Vcc‐Stop Threshold VCC_UVLO_ Stop Vcc Falling Trip Level 3.7 3.9 4.1 Enable‐Start‐Threshold Enable_UVL O_Start Supply ramping up 1.14 1.2 1.26 V ms Under‐Voltage Lockout 8 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 V V PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 9 -P PARAMETER Enable‐Stop‐Threshold Enable Leakage Current SYMBOL MIN TYP MAX 0.95 1 1.05 1 µA Vsns Rising, 0.45V < Vref < 1.2V 115 120 125 % Vref Vsns Rising, Vref < 0.1V 115 120 125 % Vp 1 2 3.5 µs 18.0 20.5 24.4 A 20.48 ms Ttsd Note 4 145 Ttsd_hys Note 4 20 Enable_UVL O_Stop Ien CONDITIONS IR3895 Supply ramping down Enable = 3.3V UNIT Over‐Voltage Protection OVP Trip Threshold OVP Comparator Delay OVP_Vth OVP_Tdly Over‐Current Protection Current Limit ILIMIT Hiccup Blanking Time Tblk_Hiccup Tj = 25°C, Vcc = 6.4V Over‐Temperature Protection Thermal Shutdown Threshold Hysteresis Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note 4: Guaranteed by design but not tested in production. 9 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 °C PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 10 -P IR3895 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.4 59PR9875N (Vitec) 0.29 1.2 0.4 59PR9875N (Vitec) 0.29 1.8 0.47 7443330047(Wurth Elektronik) 0.8 3.3 0.82 MPC1040LR88C(NEC/Tokin) 2.3 5 1.0 7443330010(Wurth Elektronik) 1.35 10 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 11 -P IR3895 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = External 5V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.4 59PR9875N (Vitec) 0.29 1.2 0.4 59PR9875N (Vitec) 0.29 1.8 0.47 7443330047(Wurth Elektronik) 0.8 3.3 0.82 MPC1040LR88C(NEC/Tokin) 2.3 5 1.0 7443330010(Wurth Elektronik) 1.35 11 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 12 -P IR3895 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 5.0V, Vcc = 5.0V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) P/N DCR(mΩ) 1.0 0.3 59PR9874N (Vitec) 0.29 1.2 0.3 59PR9874N (Vitec) 0.29 1.8 0.4 59PR9875N (Vitec) 0.29 12 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 13 -P IR3895 THERMAL DERATING CURVES Measurement done on Evaluation board of IRDC3895.PCB is 4 layer board with 2 oz Copper, FR4 material, size 2.23"x2" PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600kHz PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600kHz 13 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 14 -P RDSON OF MOSFETS OVER TEMPERATURE AT VCC=6.4V RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=5.0V 14 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 IR3895 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 15 -P IR3895 TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) 15 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 16 -P IR3895 TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) Note: See Over Current Protection Section 16 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Note: See Over Current Protection Section PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 17 -P THEORY OF OPERATION DESCRIPTION The IR3895 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300 kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3895 provides precisely regulated output voltage programmed via two external resistors from 0.5V to 0.86*Vin. The IR3895 operates with an internal bias supply (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The bias voltage is variable according to load condition. If the output load current is less than half of the peak‐to‐peak inductor current, a lower bias voltage, 4.4V, is used as the internal gate drive voltage; otherwise, a higher voltage, 6.4V, is used. This feature helps the converter to reduce power losses. The IC can also be operated with an external supply from 4.5 to 7.5V, allowing an extended operating input voltage (PVin) range from 1.0V to 21V. For using the internal LDO supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_Out pin and the Vin pin should be shorted to Vcc/LDO_Out pin. IR3895 The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). ENABLE The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under‐Voltage Lockout (UVLO) circuit. Therefore, the IR3895 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3895 does not turn on until the bus voltage reaches the desired level (Fig. 4). Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold, IR3895 will be enabled. Therefore, in addition to being a logic input pin to enable the IR3895, the Enable feature, with its precise threshold, also allows the user to implement an Under‐Voltage Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want the IR3895 to be disabled at least until PVIN exceeds the desired output voltage level. Pvin (12V) 10. 2 V Vcc The device utilizes the on‐resistance of the low side MOSFET (sync FET) for over current protection. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. Enable Threshold= 1.2V Enable Intl_SS IR3895 includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. Figure 4: Normal Start up, device turns on when the bus voltage reaches 10.2V UNDER‐VOLTAGE LOCKOUT AND POR The under‐voltage lockout circuit monitors the voltage of Vcc/LDO_Out pin and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc/LDO_Out and Enable rise above their thresholds. 17 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 A resistor divider is used at EN pin from PVin to turn on the device at 10.2V. PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 18 -P Pvin(12V) IR3895 Figure 5a shows the recommended start‐up sequence for the normal (non‐tracking, non‐sequencing) operation of IR3895, when Enable is used as a logic input. Figure 5b shows the recommended startup sequence for sequenced operation of IR3895 with Enable used as logic input. Figure 5c shows the recommended startup sequence for tracking operation of IR3895 with Enable used as logic input. Vcc Vp>1V In normal and sequencing mode operation, Vref is left floating. A 1nF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. Enable >1.2V Intl_SS Figure 5a: Recommended startup for Normal operation It is recommended to apply the Enable signal after the VCC voltage has been established. If the Enable signal is present before VCC, a 50kΩ resistor can be used in series with the Enable pin to limit the current flowing into the Enable pin. Pvin (12V) PRE‐BIAS STARTUP IR3895 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. Vcc Enable > 1. 2 V Intl_SS Vp Figure 5b: Recommended startup for sequencing operation (ratiometric or simultaneous) The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 6a shows a typical Pre‐Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 6b shows the series of 16x8 startup pulses. Pvin (12V) [V] Vo Pre-Bias Vcc Voltage [Time] Figure 6a: Pre‐Bias startup Vref=0 Enable > 1. 2 V Intl_SS HDRv 12.5% Vp Figure 5c: Recommended startup for memory tracking operation (Vtt‐DDR) 18 ... AUGUST 08, 2012 | DATA SHEET| Rev 3.1 16 ... 25% ... LDRv ... ... 16 ... 87.5% ... ... ... ... Figure 6b: Pre‐Bias startup pulses End of PB PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 19 -P TABLE 1: SWITCHING FREQUENCY (FS) VS. EXTERNAL RESISTOR (RT) SOFT‐START Rt (KΩ) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 21 19.1 17.4 16.2 15 IR3895 has an internal digital soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft‐start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7 shows the waveforms during soft start (also refer to Fig. 20). The normal Vout start up time is fixed, and is equal to: Tstart IR3895 0.65V-0.15V 2.5ms(1) 0.2mV/ s During the soft start the over‐current protection (OCP) and over‐voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. Freq (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 OVER CURRENT PROTECTION The over current (OC) protection is performed by sensing current through the RDS(on) of the Synchronous Mosfet. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The current limit is pre‐set internally and is compensated according to the IC temperature. So at different ambient temperature, the over‐current trip threshold remains almost constant. POR 3.0V 1.5V 0.65V 0.15V Intl_SS Over Current Protection circuit senses the inductor current flowing through the Synchronous Mosfet closer to the valley point. OCP circuit samples this current for 40nsec typically after the rising edge of the PWM set pulse which has a width of 12.5% of the switching period.The PWM pulse starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. PGood will go low and the internal soft start signal will be pulled low. The converter goes into hiccup mode with a 20.48ms (typ.) delay as shown in Figure 8. The convertor stays in this mode until the over load or short circuit is removed. The actual DC output current limit point will be greater than the valley point by an amount equal to approximately half of peak to peak inductor ripple current. The current limit point will be a function of the inductor value, input ,output voltage and the frequency of operation. Vout t1 t 2 t3 Figure 7: Theoretical operation waveforms during soft‐start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between 300 kHz – 1500 kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. SHUTDOWN IR3895 can be shutdown by pulling the Enable pin below its 1.0V threshold. This will tri‐state both the high side and the low side driver. 19 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 20 -P IOCP ILIMIT I 2 IR3895 frequency, a transition from the free‐running frequency to the external clock frequency will happen. This transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. On the contrary, when the external clock signal is removed from Rt/Sync pin, the switching frequency is also changed to free‐running gradually. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin, as shown in Fig9a. Figure 9b shows the timing diagram of these transitions. (2) IOCP= DC current limit hiccup point ILIMIT= Current limit Valley Point ΔI=Inductor ripple current IR3895 Rt/Sync Gnd Figure 8: Timing Diagram for Current Limit Hiccup Figure 9a: Configuration of External Synchronization THERMAL SHUTDOWN Temperature sensing is provided inside IR3895. The trip threshold is typically set to 145oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. EXTERNAL SYNCHRONIZATION IR3895 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub‐harmonic oscillations due to beat frequency for embedded systems when multiple point‐of‐load (POL) regulators are used. A multi‐function pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock signal solely and no other resistor is needed. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free‐running frequency, an external resistor from Rt/Sync pin to Gnd is required to set the free‐running frequency. When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its free‐running 20 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Figure 9: Timing Diagram for Synchronization to the external clock (Fs1>Fs2 or Fs1<Fs2) An internal circuit is used to change the PWM ramp slope according to the clock frequency applied on Rt/Sync pin. Even though the frequency of the external synchronization clock can vary in a wide range, the PLL circuit will make sure that the ramp amplitude is kept constant, requiring no adjustment of the loop compensation. Vin variation also affects the ramp amplitude, which will be discussed separately in Feed‐Forward section. PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 21 -P Feed‐Forward Feed‐Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load transient performance when Vin varies in a large range. In IR3895, F.F. function is enabled when Vin pin is connected to PVin pin. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (Vramp) is proportionally changed with Vin to maintain Vin/Vramp almost constant throughout Vin variation range (as shown in Fig. 10). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed‐forward function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the F.F. function is disabled. A re‐calculation of control loop parameters is needed for re‐compensation. IR3895 chattering. Figure 11 shows the timing diagram. Whenever device turns on, LDO always starts with 6.4V, and then goes to 4.4V/6.4V depending upon the load condition. For internally biased single rail operation, Vin pin should be connected to PVin pin, as shown in Figure 11b. If external bias voltage is used, Vin pin should be connected to Vcc/LDO_Out pin, as shown in Figure 11c. ... IL ... ... 0 ... 256/Fs Vcc/ LDO 6.4V 4.4V 6.4V 0 Figure 11a: Time Diagram for Smart LDO Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function SMART LOW DROPOUT REGULATOR (LDO) Figure 11b: Internally Biased Single Rail Operation IR3895 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. In order to improve overall efficiency over the whole load range, LDO voltage is set to 6.4V (typical.) at mid‐ or heavy load condition to reduce Rds(on) and thus MOSFET conduction loss; and it is reduced to 4.4 (typical.) at light load condition to reduce gate drive loss. The smart LDO can select its output voltage according to the load condition by sensing switch node (SW) voltage. At light load condition when part of the inductor current flows in the reverse direction (DCM=1), VSW > 0 on LDrv falling edge in a switching cycle. If this case happens for consecutive 256 switching cycles, the smart LDO reduces its output to 4.4V. If in any one of the 256 cycles, Vsw < 0 on LDrv falling edge, the counter is reset and LDO voltage doesn’t change. On the other hand, if Vsw < 0 on LDrv falling edge (DCM=0) , LDO output is increased to 6.4V. A hysteresis band is added to Vsw comparison to avoid 21 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Figure 11c: Use External Bias Voltage OUTPUT VOLTAGE TRACKING AND SEQUENCING IR3895 can accommodate user programmable tracking and/or sequencing options using Vp, Vref, Enable, and Power Good pins. In the block diagram presented on page PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 22 -P 3, the error‐amplifier (E/A) has been depicted with three positive inputs. Ideally, the input with the lowest voltage is used for regulating the output voltage and the other two inputs are ignored. In practice the voltage of the other two inputs should be about 200mV greater than the low‐voltage input so that their effects can completely be ignored. Vp is internally biased to 3.3V via a high impedance path. For normal operation, Vp and Vref is left floating (Vref should have a bypass capacitor). 6.8 V < Vin < 21 V Vref S_Ctrl EN Vin PVin Vcc/LDO Vo1 (master) RE PGood PGood RF Boot Vo2 (Salve) SW Vsns Vp RC Rt/ Sync Fb Gnd Therefore, in normal operating condition, after Enable goes high, the internal soft‐start (Intl_SS) ramps up the output voltage until Vfb (voltage of feedback/Fb pin) reaches about 0.5V. Then Vref takes over and the output voltage is regulated.. IR3895 PGnd Comp RD Figure 12: Application Circuit for Simultaneous and Ratiometric Sequencing Tracking‐mode operation is achieved by connecting Vref to GND. Then, while Vp=0, Enable is taken above its threshold so that the soft‐start circuit generates Intl_SS signal. After the Intl_SS signal reaches the final value (refer to Fig.5c) , ramping up the Vp input will ramp up the output voltage. In tracking mode, Vfb always follows Vp which means Vout is always proportional to Vp voltage (typical for DDR/Vtt rail applications). The effective Vp variation range is 0V~1.2V. In sequencing mode of operation (simultaneous or ratiometric), Vref is left floating and Vp is kept to ground level until Intl_SS signal reaches the final value. Then Vp is ramped up and Vfb follows Vp. When Vp>0.5V the error‐ amplifier switches to Vref and the output voltage is regulated with Vref.The final Vp voltage after sequencing startup should between 0.7V ~ 3.3V. Tracking and sequencing operations can be implemented to be simultaneous or ratiometric (refer to Fig. 13 and 14). Figure 12 shows typical circuit configuration for sequencing operation. With this power‐up configuration, the voltage at the Vp pin of the slave reaches 0.5V before the Fb pin of the master. If RE/RF =RC/RD, simultaneous startup is achieved. That is, the output voltage of the slave follows that of the master until the voltage at the Vp pin of the slave reaches 0.5 V. After the voltage at the Vp pin of the slave exceeds 0.5V, the internal 0.5V reference of the slave dictates its output voltage. In reality the regulation gradually shifts from Vp to internal Vref. The circuit shown in Fig. 12 can also be used for simultaneous or ratiometric tracking operation if Vref of the slave is connected to GND. Table 2 summarizes the required conditions to achieve simultaneous/ratiometric tracking or sequencing operations. Vcc Vref=0.5V Enable (slave) 1.2V Soft Start (slave) Vo1 (master) (a) Vo2 (slave) Vo1 (master) (b) Vo2 (slave) Figure 13: Typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric 22 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 23 -P Vcc POWER GOOD OUTPUT (TRACKING, SEQUENCING, VREF MARGINING) Vref=0V (slave) Enable (slave) IR3895 continually monitors the output voltage via the sense pin (Vsns) voltage. The Vsns voltage is an input to the window comparator with upper and lower threshold of 0.6V and 0.45V respectively. PGood signal is high whenever Vsns voltage is within the PGood comparator window thresholds. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. 1.2V Soft Start (slave) Vo1 (master) Vo2 (slave) (a) Vo1 (master) (b) Vo2 (slave) Figure 14: Typical waveforms in tracking mode of operation: (a) simultaneous, (b) ratiometric TABLE 2: REQUIRED CONDITIONS FOR SIMULTANEOUS/RATIOMETRIC TRACKING AND SEQUENCING (FIG. 12) Operating Mode Normal (Non‐sequencing, Non‐tracking) Simultaneous Sequencing Ratiometric Sequencing Simultaneous Tracking Ratiometric Tracking Vref (Slave) 0.5V (Floating) 0.5V 0.5V 0V 0V IR3895 Vp Required Condition Floating ― Ramp up from 0V Ramp up from 0V Ramp up from 0V Ramp up from 0V RA/RB>RE/ RF=RC/RD RA/RB>RE/ RF>RC/RD RE/RF =RC/RD RE/RF >RC/RD The threshold is set differently at different operating modes and the results of the comparison sets the PGood signal. Figures 15, 16, and 17 show the timing diagram of the PGood signal at different operating modes. Vsns signal is also used by OVP comparator for detecting output over voltage condition. Figure 15: Non‐sequence, Non‐tracking Startup and Vref Margin (Vp pin floating) VREF This pin reflects the internal reference voltage which is used by the error amplifier to set the output voltage. In most operating conditions this pin is only connected to an external bypass capacitor and it is left floating. A 1nF ceramic capacitor is recommended for the bypass capacitor. To keep stand by current to minimum, Vref is not allowed come up until EN starts going high. In tracking mode this pin should be pulled to GND. For margining applications, an external voltage source is connected to Vref pin and overrides the internal reference voltage. The external voltage source should have a low internal resistance (<100Ω) and be able to source and sink more than 25µA. 0.4V 0.3V Vp 0 1.2*Vp Vsns 0.9*Vp 0 PGood 0 1.28ms Figure 16: Vp Tracking (Vref =0V) 23 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 24 -P IR3895 SOFT‐STOP (S_CTRL) Soft‐stop function can make output voltage discharge gradually. To enable this function, S_Ctrl is kept low first when EN goes high. Then S_Ctrl is pulled high to cross the logic level threshold (typical 2V), the internal soft‐start ramp is initiated. So Vo follows Intl_SS to ramp up until it reaches its steady state. In soft‐stop process, S_Ctrl needs to be pulled low before EN goes low. After S_Ctrl goes below its threshold, a decreasing ramp is generated at Intl_SS with the same slope as in soft‐start ramp. Vo follows this ramp to discharge softly until shutdown completely. Figure 19 shows the timing diagram of S_Ctrl controlled soft‐start and soft‐stop. Figure 17: Vp Sequence and Vref Margin OVER‐VOLTAGE PROTECTION (OVP) Over‐voltage protection in IR3895 is achieved by comparing sense pin voltage Vsns to a pre‐set threshold. In non‐tracking mode, OVP threshold can be set at 1.2*Vref; in tracking mode, it can be at 1.2*Vp. When Vsns exceeds the over voltage threshold, an over voltage trip signal asserts after 2us (typical.) delay. Then the high side drive signal HDrv is turned off immediately, PGood flags low. The low side drive signal is kept on until the Vsns voltage drops below the threshold. After that, HDrv is latched off until a reset performed by cycling either Vcc or Enable. Vsns voltage is set by the voltage divider connected to the output and it can be programmed externally. Figure 18 shows the timing diagram for OVP in non‐tracking mode. If the falling edge of Enable signal asserts before S_Ctrl falling edge, the converter is still turned off by Enable. Both gate drivers are turned off immediately and Vo discharges to zero. Figure 20 shows the timing diagram of Enable controlled soft‐start and soft‐stop. Soft stop feature ensures that Vout discharges and also regulates the current precisely to zero with no undershoot. Enable 0 S_Ctrl 0 0.65V 0.65V Intl _SS 0.15V 0.15V 0 Vout 0 Figure 19: Timing Diagram for S_Ctrl controlled Soft Start/Soft Stop S_Ctrl 0 1.2V Enable 1.0V 0 0.65V Intl _SS 0.15V 0 Vout Figure 18: Timing Diagram for OVP in non‐tracking mode 24 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 0 Figure 20: Timing Diagram for Enable controlled Soft Start/Shutdown PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 25 -P IR3895 MINIMUM ON TIME CONSIDERATIONS MAXIMUM DUTY RATIO The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is very critical parameter for low duty cycle, high frequency applications. Conventional approach limits the pulse width to prevent noise, jitter and pulse skipping. This results to lower closed loop bandwidth. A certain off‐time is specified for IR3895. This provides an upper limit on the operating duty ratio at any given switching frequency. The off‐time remains at a relatively fixed ratio to switching period in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which IR3895 can operate. Figure 21 shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feed forward. IR has developed a proprietary scheme to improve and enhance minimum pulse width which utilizes the benefits of voltage mode control scheme with higher switching frequency, wider conversion ratio and higher closed loop bandwidth, the latter results in reduction of output capacitors. Any design or application using IR3895 must ensure operation with a pulse width that is higher than this minimum on‐time and preferably higher than 60 ns. This is necessary for the circuit to operate without jitter and pulse‐skipping, which can cause high inductor current ripple and high output voltage ripple. ton Vout D (3) Fs Vin Fs In any application that uses IR3895, the following condition must be satisfied: Figure 21: Maximum duty cycle vs. switching frequency. ton (min) ton (4) ton (min) Vout (5) Vin Fs Vin Fs Vout (6) ton (min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5 V. Therefore, for Vout(min) = 0.5 V, Vin Fs Vout (min) Vin Fs t on (min) 0.5 V 8.33 V/uS 60 ns Therefore, at the maximum recommended input voltage of 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 396 kHz. Conversely, for operation at the maximum recommended operating frequency (1.65 MHz) and minimum output voltage (0.5V). The input voltage (PVin) should not exceed 5.05V, otherwise pulse skipping will happen. 25 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 26 -P IR3895 DESIGN EXAMPLE Output Voltage Programming The following example is a typical application for IR3895. The application circuit is shown in Fig.28. Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.5V. The divider ratio is set to provide 0.5V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: Vin =12 V ( 10% ) Vo =1.2 V I o = 16 A Ripple Voltage= 1%*Vo ΔVo = 6% *︵ Vo for 50% load transient ) Fs =600 kHz R Vo Vref 1 5 (9) R6 When an external resistor divider is connected to the output as shown in Fig. 23. Enabling the IR3895 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage as shown in Fig. 22. Vref R6 R5 V o Vref (10) For the calculated values of R5 and R6, see feedback compensation section. Figure 22: Using Enable pin for UVLO implementation For a typical Enable threshold of VEN = 1.2 V R2 Vin (min) * VEN 1.2(7) R1 R2 VEN R2 R1 (8) Vin( min ) VEN For Vin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1. Figure 23: Typical application of the IR3895 for programming the output voltage Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (Fig.24), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: Vc Vcc VD (11) When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage 26 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 27 -P Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot Vin Vcc VD (12) IR3895 Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 5x10uF, 25V ceramic capacitors, C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEV‐FK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. Inductor Selection Figure 24: Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: I RMS I o D (1 D )(13) V D o (14) Vin Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=16A and D = 0.1, the IRMS = 4.8A. 27 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Vin Vo L i 1 ; t D Fs t Vo L Vin Vo Vin i * Fs (15) Where: Vin = Maximum input voltage V0 = Output Voltage Δi = Inductor Peak‐to‐Peak Ripple Current Fs = Switching Frequency Δt = On time for Control FET D = Duty Cycle If Δi ≈ 30%*Io, then the output inductor is calculated to be 0.38μH. Select L=0.4μH, 59PR9875N, from VITEC which provides a compact, low profile inductor suitable for this application. PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 28 -P IR3895 Output Capacitor Selection Feedback Compensation The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: The IR3895 is a voltage mode controller. The control loop is a single voltage feedback path including an error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to close the control loop at high crossover frequency with phase margin greater than 45o. Vo Vo(ESR) Vo(ESL) Vo(C) Vo(ESR) IL * ESR The output LC filter introduces a double pole, ‐ 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o. The resonant frequency of the LC filter is expressed as follows: V V Vo(ESL) in o * ESL L IL Vo(C) 8*Co * Fs FLC (16) Where: ΔV0 = Output Voltage Ripple ΔIL = Inductor Ripple Current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3895 can perform well with all types of capacitors. Figure 25 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Six of TDK C2012X5R0J476M (47uF/0805/X5R/6.3V) capacitors is a good choice. It is also recommended to use a 0.1µF ceramic capacitor at the output for high frequency filtering. 0dB 00 -40dB/Decade -900 FLC Frequency -1800 FLC Frequency Figure 25: Gain and Phase of LC filter The IR3895 uses a voltage‐type error amplifier with high‐ gain (110dB) and high‐bandwidth (30MHz). The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Type II compensation is shown in Fig. 26. This method requires that the output capacitors have enough ESR to satisfy stability requirements. If the output capacitor’s ESR generates a zero at 5kHz to 50kHz, the zero generates acceptable phase margin and the Type II compensator can be used. AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Phase Gain As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. 28 1 (17) 2 Lo Co PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 29 -P The ESR zero of the output capacitor is expressed as follows: FESR Use the following equation to calculate R3: R3 1 (18) 2π * ESR* Co VO U T Z IN C P O LE R3 C3 R5 Zf Fb E /A R6 C om p Ve VR E F G ain (dB ) Vosc * Fo * FESR * R5 (23) 2 Vin * FLC Where: Vin = Maximum Input Voltage Vosc = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz 75 % *FLC H (s) dB Fz 0.75* F FZ Use equation 21 to calculate C3. Figure 26: Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vout) is given by: Zf Ve 1 sR 3C3 H ( s) (19) Vout ZIN sR 5C3 The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: H s R3 (20) R5 1 Fz (21) 2 * R 3 * C3 1 (24) 2 Lo *Co F requency P O LE First select the desired zero‐crossover frequency (Fo): Fo FESR and Fo 1/5~1/10 * Fs (22) 29 IR3895 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 One more capacitor is sometimes added in parallel with C3 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP 1 (25) C3 * CPOLE 2 * R3 * C3 CPOLE The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE 1 * R 3 * Fs 1 C3 1 (26) * R 3 * Fs For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, a type III compensation network can be used, as shown in Fig. 27. PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 30 -P VOUT ZIN C2 C4 R4 R3 C3 R5 Zf IR3895 FZ 1 1 (31) 2 * R3 * C3 FZ 2 1 1 (32) 2 * C4 * ( R4 R5 ) 2 * C4 * R5 Fb R6 E/ A Ve Comp Fo R3 * C4 * VREF Gain (dB) FZ1 FZ 2 FP2 FP3 Frequency Figure 27: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: Zf Ve H ( s) Z IN Vout By replacing Zin and Zf, according to Fig. 27, the transfer function can be expressed as: H (s) Vin 1 * Vosc 2 * Lo * Co (33) Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. |H(s)| dB (1 sR3 C 3 ) 1 sC 4 R 4 R5 Cross over frequency is expressed as: C * C3 sR5 ( C 2 C 3 ) 1 sR3 2 (1 sR 4 C 4 ) C2 C3 (27) TABLE 3: DIFFERENT TYPES OF COMPENSATORS Compensator Type Type II Type III FESR vs FO Typical Output Capacitor Electrolytic SP Cap, Ceramic FLC < FESR < FO < FS/2 FLC < FO < FESR The higher the crossover frequency is, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency (Fo) is selected such that: Fo 1/5 ~ 1/10 * Fs The DC gain should be large enough to provide high DC‐regulation accuracy. The phase margin should be greater than 45o for overall stability. The compensation network has three poles and two zeros and they are expressed as follows: FP1 0(28) FP 2 FP 3 1 (29) 2 * R4 * C4 1 1 (30) C2 * C3 2 * R3 * C2 2 * R3 C2 C3 30 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 For this design we have: Vin=12V Vo=1.2V Vosc=1.8V (This is a function of Vin, pls. see feed forward section) Vref=0.5V Lo=0.4uH Co=6x47uF, ESR≈3mΩ each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 47uf capacitor used in this design is 29uf at 1.2V dc bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 31 -P The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (17) to compute the small signal Co. These result in: FLC=19.1 kHz FESR=1.8 MHz Fs/2=300 kHz Select crossover frequency F0=80 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. Detailed calculation of compensation Type III: Desired Phase Boost Θ = 70° FZ 2 Fo 1 sin 14.1 kHz 1 sin 1 sin 454.0 kHz 1 sin FP 2 Fo Select: FP 3 0.5*Fs 300 kHz Select C4 = 3.3nF. Calculate R3, C3 and C2: R3 2 * Fo * Lo * Co * Vosc ; R3 1.59 kΩ C4 * Vin Select R3 = 1.78 kΩ: C3 C2 Calculate R4, R5 and R6: R4 1 ; R4 106 Ω, Select: R4 100 Ω 2 * C4 * FP 2 R5 1 - R4 ; R5 3.4 kΩ, 2 * C4 * FZ 2 Select R5 = 4.02 kΩ: R6 Vref Vo - Vref * R5 ; R6 2.87 kΩ Select: R6 2.87 kΩ Setting the Power Good Threshold In this design IR3895 is used in normal (non‐tracking, non‐sequencing) mode, therefore the PGood thresholds are internally set at 90% and 120% of Vref. At startup as soon as Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), and after 1.28ms delay, PGood signal is asserted. As long as the Vsns voltage is between the threshold range, Enable is high, and no fault happens, the PGood remains high. The following formula can be used to set the PGood threshold. Vout (PGood_TH) can be taken as 90% of Vout. Choose R8=2.87KΩ. R7 ( FZ 1 0.5* FZ 2 7.1 kHzand 1 ; C3 12.7 nF, Select: C3 10 nF 2 *FZ 1 * R 3 1 ; C2 298 pF, Select: C2 220 pF 2 * FP 3 * R3 31 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 IR3895 Vout ( PGood _ TH ) 0.9*Vref R 7 4.02 K 1) * R8 (34) The PGood is an open drain output. Hence, it is necessary to use a pull up resistor, RPG, from PGood pin to Vcc. The value of the pull‐up resistor must be chosen such as to limit the current flowing into the PGood pin to be less than 5mA when the output voltage is not in regulation. A typical value used is 49.9kΩ. OVP comparator also uses Vsns signal for over Voltage dectection.With above values for R7 and R8, OVP trip point (Vout_OVP) is Vout _ OVP Vref *1.2 * ( R7 R8) / R8 1.44V (35) Vref Bypass Capacitor A minimum value of 100pF bypass capacitor is recommended to be placed between Vref and Gnd pins. This capacitor should be placed as close as possible to Vref pin PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 32 -P IR3895 APPLICATION DIAGRAM Figure 28: Application Circuit for a 12V to 1.2V, 16A Point of Load Converter Suggested bill of materials for the application circuit Part Reference Qty Value 1 330uF Description SMD Electrolytic F size 25V 20% 5 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M C1 C5 C6 3 0.1uF Murata GRM188R71E104KA01B Cref 1 1nF 0603, 25V, X7R, 10% 0603, 25V, COG, 5% Murata GRM1885C1E102JA01D C4 1 3300pF C2 1 220pF 0603,50V,X7R 0603, 50V, NP0, 5% Murata Murata GRM188R71H332KA01B GRM1885C1H221JA01D Co 6 47uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M Cin Manufacturer Panasonic Part Number EEV-FK1E331P CVcc 1 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 10nF 0603, 25V, X7R, 10% Murata GRM188R71E103KA01J Cvin 1 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D Lo 1 0.4uH 59PR9875N 1 1.78K SMD 11.0x7.2x7.5mm,0.29mΩ Thick Film, 0603,1/10W,1% Vitec R3 Panasonic ERJ-3EKF1781V R5 R7 2 4.02K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4021V R6 R8 2 2.87K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2871V R4 1 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V Panasonic ERJ-3EKF3922V Rt 1 39.2K Thick Film, 0603,1/10W,1% R1 Rpg 2 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V R2 1 7.5K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7551V U1 1 IR3895 PQFN 5x6mm IR IR3895MPBF 32 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 33 -P Vin= 5 V IR3895 C6 0.1uF Cin = 6 X10uF Enable U1 2.2uF CVcc Enable PVin Vin S_Ctrl Boot C1 0. 1 uF Lo 0.3 uH Vcc/LDO_out Vo=1V SW RPG 49.9K PGood PGood IR 3895 Vsns Vp R7 3.32k R8 3.32k R5 3.32k R4 100 Fb Rt/Sync Rt 39.2 . K Vref Gnd PGnd Comp C3 15nF R3 2.49k C5 0.1uF C4 2.2nF Co=6X47uF R6 3.32k C2 180pF 1nF Cref FIGURE 29: APPLICATION CIRCUIT FOR A 5V TO 1V, 16A POINT OF LOAD CONVERTER Suggested bill of materials for the application circuit: 5V to 1V Part Reference Cin C1 C5 C6 Qty Value 1 330uF Description SMD Electrolytic F size 25V 20% Manufacturer Panasonic Part Number 6 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M 3 0.1uF 0603, 25V, X7R, 10% 0603, 25V, COG, 5% Murata GRM188R71E104KA01B Murata GRM1885C1E102JA01D Murata TDK GRM188R71H222KA01B C1608C0G1H181J EEV-FK1E331P Cref 1 1nF C4 1 2200pF C2 1 180pF 0603,50V,X7R, 10% 0603, 50V, NP0, 5% Co 6 47uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M CVcc 1 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 15nF 0603,50V,X7R, 10% TDK C1608X7R1H153K Murata GRM188R61E105KA12D Cvin 1 1.0uF 0603, 25V, X5R, 10% Lo 1 0.3uH Vitec 59PR9874N R3 1 2.49k SMD 11.0x7.2x7.5mm,0.29mΩ Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2491V R5 R6 R7 R8 4 3.32k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V R4 1 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V Rt 1 39.2K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V Rpg 2 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V U1 1 IR3895 PQFN 5x6mm IR IR3895MPBF 33 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 34 -P IR3895 TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air flow Figure 30: Start up at 16A Load, Ch1:Vout, Ch2:Vin, Ch3:PGood Ch4:Enable Figure 31: Start up at 16A Load, Ch1:Vout, Ch2:Vin, Ch3: PGood, Ch4: Vcc Figure 32: Start up with Pre Bias voltage, 0A Load, Ch1:Vo Figure 33: Output Voltage Ripple, 16A Load, Ch1:Vout Figure 34: Inductor node at 16A load, Ch1:SW node 34 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Figure 35: Short Circuit Recovery, Ch1‐Vout, Ch4:Iout (5A/Div) PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 35 -P IR3895 TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air Flow Figure 37: Turn on at Full Load showing Vcc level Ch1‐Vout, Ch2‐Vin,Ch3‐Vcc,Ch4‐Inductor current Figure 36: Turn on at No Load showing Vcc level Ch1‐Vout, Ch2‐Vin, Ch3‐Vcc,Ch4‐Inductor current Figure 38: Transient Response, 8A to 16A step at 2.5A/uSec slew rate, Ch1:Vout, Ch4‐Iout (5A/Div) 35 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 36 -P IR3895 TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air flow Figure 40: Start/Stop using S_Ctrl Pin, Ch1:Vout, Ch2:Enable, Ch3: PGood,Ch4:S_Ctrl Figure 39: Feed forward for Vin change from 6.8 to 16V, Ch1:Vout, Ch2:Vin Figure 42: Over Voltage Protection, Ch1:Vout, Ch3:PGood Figure 41: External frequency synchronization to 800kHz from free running 600kHz, Ch1:Vo, Ch2:Rt/Sync Voltage,Ch3:SW Node Voltage Figure 43: Voltage margining using Vref pin Ch1:Vout, Ch3:PGood,Ch4:Vref 36 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 Figure 44: Voltage tracking using Vp pin Ch1‐Vout, Ch3:PGood ,Ch4:Vp PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 37 -P IR3895 TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air Flow Figure 45: Bode Plot at 16A load shows a bandwidth of 95.2kHz and phase margin of 54.5° Figure 46: Thermal Image of the Board at 16A Load, Test Point 1 is IR3895, Test Point 2 is inductor 37 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 38 -P IR3895 The critical bypass components such as capacitors for Vin, Vcc and Vref should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3899 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3899. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4‐layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figures 46a‐d illustrates the implementation of the layout guidelines outlined above, on the IRDC3899 4‐layer demo board. The feedback part of the system should be kept away from the inductor and other noise sources. Enough copper & minimum ground length path between Input and Output All bypass caps should be placed as close as possible to their connecting pins Compensation parts should be placed as close as possible to the Comp pin Resistor Rt and Vref decoupling cap should be placed as close as possible to their pins Switch Node Figure 47a: IRDC3895 Demo board Layout Considerations – Top layer 38 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 39 -P IR3895 Single point connection Feedback and Vsns trace routing should be kept away from noise sources between AGND & PGND, should be close to the SupIRBuck kept away from noise sources Figure 47b: IRDC3895 Demo board Layout Considerations – Bottom Layer Analog ground plane Power ground plane Figure 47c: IRDC3895 Demo board Layout Considerations – Mid Layer 1 Figure 47d: IRDC3895 Demo board Layout Considerations – Mid Layer 2 39 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 40 -P PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following Figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self‐centering behavior is highly dependent on solders and processes and experiments should be run to confirm the limits of self‐centering on specific processes. For further information, please refer to “SupIRBuck™ Multi‐Chip Module (MCM) Power Quad Flat No‐Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 48: PCB Metal Pad Sizing and Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 40 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 IR3895 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 41 -P IR3895 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in‐between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 49: Solder resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 41 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 42 -P IR3895 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100‐0.250mm (0.004‐0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm‐0.200mm (0.005‐0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following Figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 50: Stencil Pad Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 42 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 PD‐97746 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - 43 -P IR3895 MARKING INFORMATION Figure 51: Marking Information DIM A A1 b b1 c D E e e1 e2 MILIMITERS MIN MAX 0.800 1.000 0.000 0.050 0.375 0.475 0.250 0.350 0.203 REF. 5.000 BASIC 6.000 BASIC 1.033 BASIC 0.650 BASIC 0.852 BASIC INCHES MIN MAX 0.0315 0.0394 0.0000 0.0020 0.1477 0.1871 0.0098 0.1379 0.008 REF. 1.969 BASIC 2.362 BASIC 0.0407 BASIC 0.0256 BASIC 0.0335 BASIC DIM L M N O P Q R S t1, t2, t3 t4 t5 MILIMITERS MIN MAX 0.350 0.450 2.441 2.541 0.703 0.803 2.079 2.179 3.242 3.342 1.265 1.365 2.644 2.744 1.500 1.600 0.401 BASIC 1.153 BASIC 0.727 BASIC INCHES MIN MAX 0.0138 0.0177 0.0961 0.1000 0.0277 0.0316 0.0819 0.0858 0.1276 0.1316 0.0498 0.0537 0.1041 0.1080 0.0591 0.0630 0.016 BACIS 0.045 BASIC 0.0286 BASIC Figure 52: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 12/11 43 AUGUST 08, 2012 | DATA SHEET| Rev 3.1