Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator FEATURES iP1837 DESCRIPTION Wide input application 1.5V―16V Single 3.3V or single 5V application Output Voltage Range: 0.6V to 0.75*Vin 0.5% accurate Reference Voltage Programmable Switching Frequency up to 1.5MHz Programmable Soft‐Start Enable input with Voltage Monitoring Capability Remote Sense Amplifier with True Converter Voltage Sensing Thermally compensated Hiccup Mode Over Current Protection Over‐voltage protection Pre‐Bias Start up The iP1837 iPOWIRTM is an easy‐to‐use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make iP1837 a space‐efficient solution, providing accurate power delivery for low output voltage and high current applications. iP1837 is a versatile regulator which offers programmability of switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre‐Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. Body Braking to improve transient Integrated MOSFET drivers and Bootstrap diode Operating temp: ‐40oC<Tj<125oC APPLICATIONS Server Application Thermal Shut Down Netcom Applications Power Good Output with Window Comparator Embedded Telecom Systems Small Size 7.7mmx7.7mm LGA BASIC APPLICATION Distributed Point of Load Power Architectures 97 96 95 94 Efficiency (%) Halogen Free, Pb‐Free and RoHS Compliant 93 92 91 Vin=12V Vcc=3.3V Room Temperature 200 LFM airflow Includes biasing loss as well as inductor losses and stray PCB losses 90 89 iP1837 88 87 3.5 7 10.5 14 17.5 21 24.5 28 31.5 35 Iout (A) Vo=3.3V Vo=1.8V Figure 1 : iP1837 Basic Application Circuit 1 March 5, 2012 | V1.26 Figure 2: iP1837 Efficiency 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 PIN DIAGRAM LGND FB SS PIN 17 PIN 6 PIN 16 PIN 7 PIN 15 PIN 8 COMP PIN 1 Vin PIN 5 VOSM VOSO PIN 2 VOSP SW Θj-pcb=2.3 0C/W RT PIN 9 EN PIN 3 VCC PIN 14 PIN 10 PGD PGND OCSET PIN 13 PIN 11 PVCC BiasGND PIN 12 PIN 4 Figure 3: iP1837 Package Bottom View 7.65mm x 7.65mm LGA ORDERING INFORMATION Package Tape and Reel Qty Part Number LGA (7.65mm x 7.65mm body) 2000 iP1837TRPbF 2 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 FUNCTIONAL BLOCK DIAGRAM + Figure 4: iP1837 Simplified Block Diagram 3 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL APPLICATION DIAGRAM Figure 5: iP1837 Application Circuit Diagram for a 12V to 1.8V, 35A Point Of Load Converter 4 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 VIN Input voltage for power stage. Bypass capacitors between VIN and PGND should be connected very close to this pin and PGND (pin 3). 2 SW Switch node. This pin is connected to the output inductor. 3 PGND Power ground. This pin should be connected to the system’s power ground plane. Bypass capacitors between VIN and PGND should be connected very close to VIN pin (pin 1) and this pin. 4 PVCC Output of internal charge pump. Connect a 4.7uF to 10uF capacitor from this pin to local bias PGND (pin 12), very close to the pins. External 5V may also be connected to this pin for operation from 5V bias. 5 SS 6 LGND Signal ground for internal reference and control circuitry. 7 VOSM Remote Sense Amplifier input. Connect to ground at the load. 8 VOSP Remote Sense Amplifier input. Connect to output at the load. 9 RT 10 VCC 11 OCSET Current Limit setpoint. A resistor may be connected from this pin to SW pin to set thresholds lower than those allowed by maximum current rating of the device. 12 BIASGND This pin serves as a ground for the MOSFET drivers. It should be connected to the negative terminal of the bias voltage at the VCC and/or PVCC capacitors. 13 PGD 14 EN 15 VOSO Remote Sense Amplifier Output; also forms an input to the power good comparator and overvoltage comparator. 16 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation. 17 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. Soft start; a capacitor from SS and LGND sets the startup timing. Use an external resistor from this pin to GND to set the switching frequency, very close to the pin. Input bias voltage for internal IC. This also powers the charge pump circuit in the IC. Connect a 10uF capacitor from this pin to local bias PGND (pin 12), very close to the pins. For 5V bias operation, this pin should be tied to ground. Power Good status pin. Output is open collector. Connect a pull up resistor from this pin to VCC. Enable pin to turn on and off the IC. 5 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 ABSOLUTE MAXIMUM RATINGS VIN ‐0.3V to 25V VCC ‐0.3V to 3.9V PVCC ‐0.3V to 8V (Note 2) SW ‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) BOOT ‐0.3V to 33V Input/output pins, except PGD, Vosp and Voso ‐0.3V to VCC + 0.3V PGD, Vosp and Voso ‐0.3V to PVCC + 0.3V (Note 2) PGND to LGND, BIASGND to LGND, Vosm to LGND ‐0.3V to + 0.3V Storage Temperature Range ‐55°C to 150°C Junction Temperature Range ‐40°C to 150°C ESD Classification JEDEC Class 1C (1KV) Moisture Sensitivity level JEDEC Level 3@250°C Note 1: Must not exceed 8V. Note 2: PVCC must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. These devices are ESD sensitive, observe handling precautions to prevent electrostatic discharge damage. 6 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL DEFINITION MIN MAX VIN Input Voltage 1.5 16 PVCC Supply Voltage 4.5 7.5 VCC Supply Voltage 3.13 3.46 Boot to SW Supply Voltage 4.5 7.5 VO Output Voltage 0.6 0.75 Vin UNITS V IO Output Current 0 35 A Fs Switching Frequency 225 1650 kHz TJ Junction Temperature ‐40 125 °C ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specification apply over, 1.5V < Vin < 16V, 3.13V < Vcc < 3.46V. 0oC < TJ < 125oC. Typical values are specified at TA = 25oC. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Vin = 12V, VCC = 3.3V, VO = 1.8V, IO = 35A, Fs = 600kHz, L=0.215uH, TA = 25°C 7.12 W Power Loss Power Loss PLOSS MOSFET Rds(on) Top Switch Rds(on)_Top VBoot – VSW = 5V, ID = 5A, Tj = 25°C 4.8 6 Bottom Switch PVCC = 5V, ID = 25A, Tj = 25°C 1.45 1.64 VCC = 3.3V, ID = 25A, Tj = 25°C 1.2 1.35 0.6 mΩ Reference Voltage Feedback Voltage VFB V Accuracy 40°C < Tj < 105°C ‐0.5 +0.5 ‐40°C < Tj < 125°C, Note 3 ‐1.5 +1.5 400 600 uA 95 mA 150 200 uA 36 mA % Supply Current VCC Supply Current (Standby) ICC(Standby) Enable low, No Switching, VCC = 3.3V VCC Supply Current (Dyn) ICC(Dyn) Enable high, Fs = 500kHz, VCC = 3.3V PVCC Supply Current (Standby) IPCC(Standby) Enable low, No Switching, PVCC = 5V PVCC Supply Current (Dyn) IPCC(Dyn) Enable high, Fs = 500kHz, PVCC = 5V PVCC – Start – Threshold PVCC_UVLO_Start PVCC Rising Trip Level 4.0 4.2 4.4 PVCC – Stop – Threshold PVCC_UVLO_Stop PVCC Falling Trip Level 3.7 3.9 4.1 Under Voltage Lockout 7 March 5, 2012 | V1.26 V 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator PARAMETER SYMBOL CONDITIONS iP1837 MIN TYP MAX VCC – Start – Threshold VCC_UVLO_Start VCC Rising Trip Level 2.6 2.8 3.1 VCC – Stop – Threshold VCC_UVLO_Stop VCC Falling Trip Level 2 2.2 2.5 Enable – Start – Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable – Stop – Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 Rt Voltage 1 Frequency Range F S 450 500 550 1350 1500 1650 UNIT V Oscillator V kHz Ramp Offset Ramp (os) Note 3 0.4 V Min Pulse Width Dmin (ctrl) Note 3 50 ns Fixed Off Time Note 3 130 200 ns Max Duty Cycle Dmax 75 % Input Bias Current IFb(E/A) ‐1 +1 µA Input Bias Current IVp(E/A) ‐1 +1 µA Sink Current Isink(E/A) 0.6 0.9 1.2 mA Source Current Isource(E/A) 5 8 12 mA Slew Rate SR Note 3 7 12 20 V/µs Gain‐Bandwidth Product GBWP Note 3 20 30 40 MHz DC Gain Gain Note 3 100 110 120 dB Maximum Voltage Vmax(E/A) 1.7 2 2.3 V Minimum Voltage Vmin(E/A) 100 mV Error Amplifier Remote Sense Differential Amplifier Unity Gain Bandwidth BW_RS Note 3 3 6.4 9 MHz DC Gain Gain_RS Note 3 110 dB Offset Voltage Offset_RS ‐3 0 3 mV Source Current Isource_RS 3 9 20 mA Sink Current Isink_RS 0.4 1 2 mA Slew Rate Slew_RS Note 3, Cload = 100pF 2 4 8 V/µs VOSEN+ input impedance Rin_RS+ 70 120 200 kohm VOSEN‐ input impedance Rin_RS‐ Note 3 70 120 200 kohm Maximum Voltage Vmax_RS V(PVCC) – V(Vosp) 0.5 1 1.5 V Minimum Voltage Min_RS 50 mV Soft Start Charge Current Iss_Charg 14 20 26 µA Clamp Voltage Vss (Clamp) 3 3.3 3.6 µA Offset Voltage Vss (offset) 100 170 250 mV Soft Start 8 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator PARAMETER Shutdown Output Threshold SYMBOL CONDITIONS iP1837 MIN TYP MAX UNIT 0.1 V 360 520 960 mV 3 µA 5.5 6 6.5 V SD I(Boot) = 30mA, Note 3 lsw SW = 0V, Enable = 0V Output Voltage PVCC VCC = 3.3V, Fs = 1500 kHz, Cload = 2.2uF Oscillator Frequency Fs_CP Fs kHz BB_threshold Fb > Vref, Sw duty cycle 0 % Power Good Lower Threshold VPG (lower) Voso rising 0.48 0.51 0.54 V Lower Threshold Delay VPG (lower)_Dly Voso rising 256/Fs s PGood Voltage Low PG (voltage) IPGood = ‐5mA 0.5 V Leakage Current ILEAKAGE 0 1 µA OVP Trip Threshold OVP (trip) Voso rising 0.67 0.7 0.73 V OVP Fault Prop Delay OVP (delay) Voso rising, Note 3 200 ns OC Trip Current ITRIP OC set pin left floating, PVCC = 6.5V, TJ = 85°C 44 49 54 A SS Off Time SS_Hiccup Note 3 4096/ Fs s Thermal Shutdown Note 3 145 °C Hysteresis Note 3 20 °C Bootstrap Diode Forward Voltage Switch Node SW Leakage Current Charge Pump (PVCC) Body Braking BB Threshold Power Good Over Voltage Protection (OVP) Over‐Current Protection Thermal Shutdown Notes 3. Guaranteed by design but not tested in production. 9 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) Icc (Dyn) Icc (Standby) 600 95 560 92 89 520 86 480 83 [mA] [uA] 440 400 360 80 77 74 71 320 68 280 65 240 62 59 200 -40 -20 0 20 40 Temp[0C] 60 80 100 -40 120 -20 0 20 IPVcc (Standby) 200 40 0 Temp[ C] 60 80 100 120 IPVcc (Dyn) 35 34 180 33 160 32 31 [mA] [uA] 140 120 29 100 28 80 27 60 26 25 40 -40 -20 0 20 40 Temp[0C] 60 80 100 -40 120 0 20 60 80 100 120 60 80 100 120 60 80 100 120 25 24 530 23 520 22 510 [uA] 21 500 20 19 490 18 480 17 470 16 460 15 450 14 -40 -20 0 20 40 Temp[0C] 60 80 100 120 -40 VFB 0.609 -20 0 20 40 Temp[0C] Offset_RS 3 2.5 0.607 2 0.605 1.5 + 0.5% 0.603 1 0.5 [mV] 0.601 0.599 0.597 0 -0.5 -1 - 0.5% -1.5 0.595 -2 0.593 -2.5 -3 0.591 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 0 Temp[ C] VPG (lower) 0.54 40 Temp[0C] OVP (trip) 0.73 0.535 0.725 0.53 0.72 0.525 0.715 0.52 0.71 0.515 0.705 0.51 [V] [V] 40 0 Temp[ C] Iss_charg 26 540 [kHz] -20 Fs 550 [V] 30 0.505 0.7 0.695 0.5 0.69 0.495 0.685 0.49 0.68 0.485 0.675 0.48 0.67 -40 -20 0 20 40 60 80 0 Temp[ C] 10 March 5, 2012 | V1.26 100 120 -40 -20 0 20 40 60 80 100 120 Temp[0C] 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) 0.73 0.725 0.53 0.72 0.525 0.715 0.52 0.71 0.515 0.705 0.51 [V] [V] VPG (lower) 0.54 0.535 0.505 OVP (trip) 0.7 0.695 0.5 0.69 0.495 0.685 0.49 0.68 0.485 0.675 0.48 0.67 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temp[ C] VCC_UVLO_Start 3.1 2.4 2.95 2.35 120 60 80 100 120 60 80 100 120 60 80 100 120 2.3 [V] [V] 100 2.45 3 2.85 2.25 2.8 2.2 2.75 2.15 2.7 2.1 2.65 2.05 2 2.6 -40 -20 0 20 40 60 80 100 -40 120 -20 0 20 40 Temp[0C] 0 Temp [ C] PVCC_UVLO_Start PVCC_UVLO_Stop 4.4 4.1 4.36 4.06 4.32 4.02 4.28 3.98 4.24 3.94 [V] 80 VCC_UVLO_Stop 2.9 [V] 4.2 3.9 4.16 3.86 4.12 3.82 4.08 3.78 4.04 3.74 4 3.7 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temp [0C] Enable_UVLO_Start 1.36 1.06 1.34 1.044 1.32 1.028 1.3 40 Temp [0C] Enable_UVLO_Stop 1.012 1.28 0.996 1.26 [V] [V] 60 2.5 3.05 1.24 0.98 0.964 1.22 1.2 0.948 1.18 0.932 0.916 1.16 1.14 0.9 -40 -20 0 20 40 Temp[0C] 60 80 100 120 -40 -20 0 20 40 Temp[0C] ILtrip ILtrip 48 44 Vin=12V Vo=1.8V Fsw=600kHz Vcc=3.3V ROCSet open 46 44 Vin=12V Vo=1.8V Fsw=600kHz PVcc=5V ROCSet open 42 40 38 [A] 42 [A] 40 Temp[0C] 0 40 36 38 34 36 32 34 30 28 32 -40 -20 0 20 40 60 80 Temp[0C] 11 March 5, 2012 | V1.26 100 120 -40 -20 0 20 40 60 80 100 120 Temp[0C] 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) RDSON of Control FET over temperature at PVCC=5V 7.1 6.7 6.3 RDSON (mΩ) 5.9 5.5 5.1 4.7 4.3 3.9 3.5 -40 -20 0 20 40 60 80 100 120 Temp[0C] RDSON of Sync FET over temperature 1.9 1.8 1.7 1.6 RDSON(mΩ) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 -40 -20 0 20 40 60 80 100 120 Temp[0C] Rdson@PVcc=5V 12 March 5, 2012 | V1.26 Rdson@Vcc=3.3V 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 THERMAL DE‐RATING CURVES AT VCC = 3.3V Thermal Derating-iP1837 Vin-12V Vout-1.8V/35A Freq-600KHz 35 33 31 Iout(A) 29 27 25 23 21 0 LFM 100LFM 200LFM 300LFM 400LFM 19 25 30 35 40 45 50 55 Ta(°C) 60 65 70 75 80 85 80 85 Thermal Derating-iP1837 Vin-12V Vout-3.3V/35A Freq-600KHz 35 33 31 Iout(A) 29 27 25 23 21 19 0 LFM 100LFM 200LFM 300LFM 400LFM 17 25 13 30 35 40 March 5, 2012 | V1.26 45 50 Ta(°C) 55 60 65 70 75 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator THEORY OF OPERATION INTRODUCTION The iP1837 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. Alternatively, if operation from 3.3V bias is desired, the 3.3V supply should be applied between Vcc and the local bias PGnd. An internal charge‐pump whose output is tied to PVcc, roughly doubles this Vcc voltage. This should be preferred for high current applications which may benefit from the lower Rds(on) on account of the higher PVcc (almost 6.3V, from Figure 6), which forms the supply to the gate drivers. UNDER‐VOLTAGE LOCKOUT AND POR The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. iP1837 provides precisely regulated output voltage programmed from 0.6V to 0.75*Vin using two external resistors. The iP1837 is capable of operating with either a 3.3V Vcc bias voltage (3.13V to 3.46V) or a PVcc bias voltage from 4.5V to 7.5V, allowing an extended operating input voltage range from 1.5V to 16V. The device utilizes the on‐resistance of the low side MOSFET as the current sense element; this method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. The under‐voltage lockout circuit monitors the input supply PVcc and the Enable input. It ensures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once PVcc and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). ENABLE iP1837 includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. BIASING THE IP1837 The iP1837 offers flexibility in choosing the bias supply voltage as it is capable of operating with a 5V bias voltage as well as a 3.3V bias voltage (Figure 1 and Figure 32) If it is preferred to use a 5V bias voltage, this should be applied between the PVcc pin and the local bias PGnd (pin 12), with the Vcc pin tied to the local bias PGnd also. 6.5 6.45 6.4 6.35 6.3 PVcc (V) iP1837 6.25 6.2 The Enable feature allows another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under‐Voltage Lockout (UVLO) circuit. Therefore, the iP1837 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the iP1837 does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the iP1837. Therefore, in addition to being a logic input pin to enable the iP1837, the Enable feature, with its precise threshold, also allows the user to implement an Under‐Voltage Lockout for the bus voltage Vin. This is desirable particularly for high output voltage applications, where we might want the iP1837 to be disabled at least until Vin exceeds the desired output voltage level. 6.15 Figure 7a shows the startup sequence with the Enable used to implement a precise under‐voltage lockout for Vin. Figure 7b. shows the recommended start‐up sequence for iP1837, when Enable is used as a logic input. 6.1 6.05 6 5.95 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 Fsw (kHz) Figure 6: PVcc v/s Switching Frequency (Fsw) with Vcc=3.3V 14 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 [V ] Vo P re -B ia s V o lta g e [T im e ] Figure 8: Pre‐Bias startup At the end of the pre‐bias stage, the synchronous MOSFET is switched complementary to the Control MOSFET. Figure 8 shows a typical Pre‐Bias condition at start up. HDRv Figure 7a: Normal Start up, Device turns on when the Bus voltage reaches 10.2V ... ... ... LDRiss ... 12.5% ... 25% LDRv Bus Voltage (12V) ... 32 ... ...... ...... 87.5% ... 32 32 End of PB Figure 9: Pre‐Bias startup pulses PVcc(5V) or Vcc(3.3V) SOFT‐START Enable > 1.2V SS Figure 7b: Recommended startup sequence with Vcc or PVcc The iP1837 has a programmable soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to Vcc. Figure 10 shows the waveforms during the soft start. The start up time can be estimated by: PRE‐BIAS STARTUP iP1837 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated, following which, the synchronous MOSFET starts with a narrow duty cycle of 12.5% and gradually increases its duty cycle in steps of 12.5%, with 32 cycles at each step until the end of pre‐bias. Tstart 0.8 - 0.2 * C SS I ss (1) During the soft start the OCP is enabled to protect the device for any short circuit and over current condition. 15 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 An internal current source sources current (IOCSet ) out of the OCSet pin. The internal current source develops a voltage across ROCSet. When the low side MOSFET is turned on, the inductor current flows through Q2 and results in a voltage at OCSet which is given by: POR 0.8V 0.2V Vss VOCSet ( I OCSet ROCSet ) ( R DS (on ) I L ) Vout t1 t2 t3 Figure 10: Theoretical operation waveforms during soft‐start OPERATING FREQUENCY (2) An over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILtrip, ROCSet is calculated as follows: ROCSet The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from RT pin to Gnd. Table 1 tabulates the oscillator frequency versus RT. R DS ( on ) * I Ltrip (3) I OCSet Vin Q1 TABLE 1: SWITCHING FREQUENCY VS. EXTERNAL RESISTOR (RT) 250 88.7 300 73.2 400 54.9 450 48.7 500 44.2 600 36.5 800 27.4 1000 22.1 1500 14 SHUTDOWN The iP1837 can be shutdown by pulling the Enable pin below its 1 V threshold. This will tri‐state both, the high side driver as well as the low side driver. TEMPERATURE‐COMPENSATED OVER‐CURRENT PROTECTION The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. As shown in Figure 11, an external resistor (ROCSet) is connected between OCSet pin and the switch node (SW) which sets the current limit set point. 16 March 5, 2012 | V1.26 SW Q2 PGnd Hiccup Control + ROCSet(ext) RT (kohm) ROCSet(int) Fsw (kHz) ROCSet - IOCSet OCSet IntVCC Figure 11: Connection of over‐current sensing resistor It should be noted that the iP1837 uses a temperature compensated overcurrent protection scheme, i.e., IOCSet varies with temperature with the same temperature coeffecient as RDS(on), so that ILtrip depends only on Rocset and is independent of temperature. The value of Rocset calculated above is realized as a parallel combination of an internal 2.7K resistor and an external resistor connected between the Rocset and SW pins. Table 2 shows the selection of the external Rocset resistor for various values of the trip load current Iotrip at Vcc = 3.3V. 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator An overcurrent detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft‐start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. Following this, the OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. iP1837 Thus, for low duty cycle operation, the inductor current is sensed close to the valley. This allows a longer delay after the falling edge of the switch node, than the corresponding delay for an over‐current sensing scheme which samples the current at the peak of the inductor current. This longer delay serves to filter out any noise on the switch node and hence on the OCSet pin, making this method more immune to false tripping. THERMAL SHUTDOWN For operation at the maximum duty cycle, the OCP circuit samples current for 40 ns, starting 40 ns after the low drive signal for the Sync FET > 70% of PVcc. Temperature sensing is provided inside iP1837. The trip threshold is typically set to 145oC. When the trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. TABLE 2: OVERCURRENT SETTING VS. EXTERNAL ROCSET TRIMMABLE RISING EDGE DEADBAND For the iP1837, the Sync FET is turned OFF on the falling edge of a PWMSet or Clock signal that has a duration of 25% of the switching period. Iotrip (A) External Rocset (kohm) 25 4.02 26 4.42 27 4.87 28 5.4 29 6.04 30 6.8 31 7.68 32 8.66 33 10 34 11.5 35 13.7 36 16.2 37 20 38 26.1 39 35.7 40 54.9 41 113 42 Open For operating duty cycles less than the maximum duty cycle of 75%, the OCP circuit still samples current for typically 40ns, but starts sampling 40 ns after the rising edge of PWMSet . 17 March 5, 2012 | V1.26 The iP1837 has a rising edge deadband that is post‐ package trimmable. It is typically trimmed to 5ns‐10ns which is an optimal range to minimize switching transition loss and at the same time, prevent cross conduction. REMOTE VOLTAGE SENSING True differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. The Vosp and Vosm pins of the iP1837 form the inputs to a remote sense differential amplifier with high speed, low input offset (post‐package trimmed to +/‐3mV) and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. It should be noted, however, that the output Voso of the difference amplifier also forms the input toa power good comparator and overvoltage comparator, both referenced to an upper threshold of 0.7V as discussed in the next section. Hence, in applications where Vo > 0.6V, it is necessary to use a resistive divider network after Vo to attenuate the sensed output voltage signal between the remote Vo and the remote ground to 0.6V, which is then applied between Vosp and Vosm. 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator In applications where only local sensing is required for feedback, the remote voltage sensing pins of the iP1837 may be dedicated to sensing the output for power good indication and overvoltage protection. iP1837 0.7V 0.6V Voso 0 POWER GOOD OUTPUT AND OVER‐VOLTAGE PROTECTION HDrv 0 The IC continually monitors the output voltage via output of the remote sense amplifier (Voso pin). The Voso voltage forms an input to a window comparator whose upper and lower thresholds are 0.7V and 0.51V respectively. Hence, the Power Good signal is flagged when the Voso pin voltage is within PGood window, i.e., between 0.51V and 0.69V, as shown in Figure 12a. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Figure 12a also shows the PGood timing diagram with a 256 cycle delay between the Voso voltage entering within the thresholds defined by the PGood window and PGood going high If the output voltage exceeds the over voltage threshold 0.7V, an over voltage trip signal is asserted; this will turn off the high side driver and turn on the low side driver until the Voso voltage drops below the 0.7V threshold. Both drivers are then turned off until a reset is performed by cycling Vcc (or PVcc/Enable) or until another OVP event occurs turning on the low side driver again. Figure 12b shows the response in over‐voltage condition. 0.8V 0.2V SS 0 LDrv 0 SS 0 PGood 0 Figure 12b: iP1837 Signal Timing for OVP BODY BRAKINGTM The Body Braking feature of the iP1837 allows improved transient response to step‐down load transients. A severe step‐down load transient would cause an overshoot in the output voltage and drive the Comp pin voltage down until control saturation occurs demanding 0% duty cycle, and the PWM input to the Control FET driver is kept OFF. When the first such skipped pulse occurs, the iP1837 enters the Body Braking mode, wherein the Sync FET is also turned OFF. The inductor current then decays by freewheeling through the body diode of the Sync FET. Thus, with Body Braking, the forward voltage drop of the body diode provides an additional voltage to discharge the inductor current faster to the light load value as shown in equations 4 and 5 below: 0.7V Voso V VD di L o , with body braking dt L V di L o , without body braking dt L 0.51V 0 (4) (5) PGD where VD= forward voltage drop of the body diode of the Sync FET. 0 256/Fs 256/Fs Figure 12a: iP1837 Power Good Signal Timing Diagram 18 March 5, 2012 | V1.26 The Body Braking mechanism is kept OFF during pre‐bias operation. Also, in the event of an extremely severe load step‐down transient causing an OVP, the Body Brake is overridden by the OVP latch, which turns on the Sync FET. 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the iP1837, the minimum on‐time is specified as 50 ns maximum. Any design or application using the iP1837 must require a pulse width that is at least equal to this minimum on‐time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse‐skipping, which can cause high inductor current ripple and high output voltage ripple. MAXIMUM DUTY RATIO CONSIDERATIONS For the iP1837, the upper limit on the operating duty ratio is set by the duration of the PWMSet pulse or by the 200 ns fixed off‐time, whichever is higher. Since the PWMSet pulse has a 25% duty cycle, this limits the maximum duty ratio at which the iP1837 can operate, to 75%. At switching frequencies above 1.25 MHz, however, the maximum duty ratio is set by the 200 ns fixed off‐time. Thus, at switching frequencies above 1.25 MHz, higher the switching frequency, the lower is the maximum duty ratio at which the iP1837 can operate. Figure 13 shows a plot of the maximum duty ratio v/s the switching frequency, with 200 ns off‐time. iP1837 TRAILING EDGE PULSE WIDTH MODULATION WITH RAMP‐SLOPE MODULATION The iP1837 employs trailing edge Pulse width modulation. However, unlike conventional trailing edge modulators, which compare the PWM ramp with the output of the error amplifier or the Comp voltage, in the modulation scheme used in the iP1837, the slope of the PWM ramp is modulated by the Comp voltage and this modulated ramp is then compared to a fixed reference voltage. The advantage of this scheme is that comparison always takes place at a fixed reference irrespective of the duty cycle of operation. Conventional modulators suffer from increased noise susceptibility at the lower duty cycles, since the comparison takes place at the Comp voltage level which is close to the bottom of the PWM ramp for low duty cycle operation. Figure 14 shows theoretical waveforms for the PWM ramp and the PWM output in response to a changing Comp voltage. Figure 15 shows the variation of the modulator gain (Fm) with the duty cycle (D). 76% 75% Max Duty Cycle (%) 74% 73% 72% 71% 70% 69% Figure 14: Theoretical waveforms for the new PWM scheme 68% 67% 66% 250 350 450 550 650 750 850 Modulator Gain = -2E-05D2 + 0.0156D + 0.4168 950 1050 1150 1250 1350 1450 1550 1650 Switching Frequency (kHz) 1.4 Figure 13: Maximum duty cycle v/s switching frequency. 1.2 Modulator gain 1 0.8 0.6 0.4 0.2 0 5 10 15 20 25 30 35 40 45 50 D(%) 55 Figure 15: Modulator gain (Fm) v/s Duty Ratio (D%) 19 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator DESIGN PROCEDURE OUTPUT VOLTAGE PROGRAMMING APPLICATION INFORMATION Design Example The following example is a typical application for iP1837. The application circuit is shown on page 1. Vin = 12V (13.2V max) Vo = 1.8V Io = 35A ΔVo (transient) ≤ ±90mV for ΔIo = 10.5A @ 2.5A/µs ΔVo (ripple) ≤ ±13.5mV (±0.75%) Fs = 600kHz ENABLING THE IP1837 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. Vin iP1837 R1 R2 For a typical Enable threshold of VEN = 1.2 V V EN R 2 R1 Vin( min ) V EN For this design, with high output current requirements, we choose to use the true differential remote sense feature. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. This references the output of the remote sense amplifier to 0.6V also. In order to satisfy this condition, the voltage between the Vosp and Vosm pins of the error amplifier should be 0.6V when the output is at its desired value. The output voltage is defined by using the following equation: Rtop Vo Vref 1 Rbot (8) Equation (8) can be rewritten as: R2 V EN 1.2 R1 R 2 Output voltage is programmed by the reference voltage and external voltage divider. If the remote sense feature is used, the divider is connected to the Vosp and Vosm pins. If only local sensing is used for feedback, with the remote sense amplifier used only in the over‐voltage protection, circuit, the resistive divider should be connected to the Fb pin. when an external resistor divider is connected to the output as shown in Figure 16. Enable Vin (min) * iP1837 (6) V oV ref Rtop Rbot V ref (9) Vout (7) For a Vin (min) = 10.2V, R1 = 49.9K and R2 = 7.5K is a good choice. PROGRAMMING THE FREQUENCY iP1837 Rtop Vosp Rbot Figure 16: Typical application of the iP1837 for programming the output voltage For Fs = 600 kHz, select Rt = 36.5 kΩ, using Table 1. 20 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator For our design, Rbot is selected to be 604 ohm. This selection is based on a trade‐off between two considerations: 1) The resistive divider should be as low impedance as possible in order to have minimal impact on the impedance seen at the Vosp and Vosm pins. 2) The resistive divider should have high enough impedance so as to minimize the bleed current from the output. In order to ensure that the Vosp and Vosm see balanced impedances, it is advisable to use Rcomp such that: Rcomp Rtop || Rbot 402 Ω (10) SOFT‐START PROGRAMMING The soft‐start timing can be programmed by selecting the soft‐start capacitance value. From (1), for a desired start‐ up time of the converter, the soft start capacitor can be calculated by using: C SS ( F) T start ( ms ) 0.033 (11) Where Tstart is the desired start‐up time (ms). For a start‐up time of 3ms, the soft‐start capacitor will be 0.099μF. Choose a 0.1μF ceramic capacitor. INPUT CAPACITOR SELECTION The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: D Vo Vin (12) (13) Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=35A and D = 0.15, the IRMS = 12.5A. 21 Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 7x22uF 16V ceramic capacitors ECJ‐3YX1C106K from Panasonic. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV‐FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. INDUCTOR SELECTION Hence, from Equation (9), Rtop = 1.21K. I RMS I o D (1 D ) iP1837 March 5, 2012 | V1.26 The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, and a faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor. The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: i 1 ; t D t Fs Vo L Vin Vo Vin i * Fs Vin Vo L (14) Where: Vin = Maximum input voltage V0 = Output Voltage Δi = Inductor Ripple Current Fs = Switching Frequency Δt – Turn on time D – Duty Cycle If Δi ≈ 35%(Io), then the output inductor is calculated to be 0.21μH. Select L = 0.215 μH. The PCDC1008‐R215EMO from Cyntec provides a compact inductor suitable for this application. 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator OUTPUT CAPACITOR SELECTION The voltage ripple and transient requirements determine the output capacitors type and values. The criteria are normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: Vo Vo( ESR) Vo( ESL) Vo(C ) Vo( ESR) I L * ESR Vo(C ) I L 8 * Co * Fs The output LC filter introduces a double pole, ‐40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see Figure 16). The resonant frequency of the LC filter is expressed as follows: FLC 1 (16) 2 Lo C o Figure 17 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. Gain Phase 0dB 0° 0dB V V Vo( ESL) in o * ESL L iP1837 -40dB/decade (15) -90° ΔV0 = Output Voltage Ripple -180° FLC Frequency Frequency FLC ΔIL = Inductor Ripple Current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The iP1837 can perform well with all types of capacitors. Figure 17: Gain and Phase of LC filter The iP1837 uses a voltage‐type error amplifier with high‐gain (110dB) and wide‐bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The error amplifier can be compensated either in type II or type III compensation. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Fifteen of the Panasonic ECJ‐2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is a good choice. Local feedback with Type II compensation is shown in Figure 18. FEEDBACK COMPENSATION The iP1837 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide an open‐loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45o). 22 March 5, 2012 | V1.26 This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows: FESR 1 2 *ESR*C o (17) 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator VOSO Z IN Where: Vin = Maximum Input Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor β = Vref/Vo Fm=Modulator gain C POLE R3 C4 R8 Zf Fb R9 E/A Comp Ve To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: VREF Gain(dB) iP1837 Fz 75 % FLC H(s) dB Fz 0.75 * FZ F (18) FP The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: (20) Fo FESR and Fo 1/5 ~ 1/10* Fs Use the following equation to calculate R3: 23 March 5, 2012 | V1.26 1 C * C POLE 2 * R3 * 4 C 4 C POLE (23) The pole sets to one half of the switching frequency which results in the capacitor CPOLE: (19) First select the desired zero‐crossover frequency (Fo): Fo * FESR * R8 R3 2 Vin * Fm * * FLC Use equations (20), (21) and (22) to calculate C4. The additional pole is given by: Zf Ve 1 sR3 C 4 H ( s) Voso Z IN sR8 C 4 1 Fz 2 * R3 * C 4 2 Lo * C o One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The transfer function (Ve/Voso) is given by: R3 R8 (22) Frequency POLE Figure 18: Type II compensation network and its asymptotic gain plot H s 1 C POLE 1 1 *R3*Fs C4 1 *R3*Fs (24) For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage‐mode controller is shown in Figure 19. Again, the transfer function is given by: (21) Zf Ve H ( s) Voso Z IN 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator Cross over frequency is expressed as: By replacing Zin and Zf according to Figure 19, the transfer function can be expressed as: H (s) Fo R3 * C 7 * Vin * * Fm * (1 sR3 C 4 )1 sC 7 R8 R10 C * C3 sR8 (C 4 C 3 ) 1 sR3 4 C4 C3 .... (25) VOSO ZIN (1 sR10 C 7 ) R3 R10 C4 R8 Zf Fb R9 E/A Comp Ve (31) Compensator Type FESR v/s F0 Type II FLC < FESR < F0 < FS/2 Type III FLC < F0 < FESR Output Capacitor Electrolytic Tantalum Tantalum Ceramic The higher the crossover frequency, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that: VREF Gain(dB) 1 2 * Lo * C o Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types for relative locations of the crossover frequency. C3 C7 iP1837 H(s) dB Fo 1/5 ~ 1/10 * Fs FZ1 FZ2 FP2 FP3 Frequency The DC gain should be large enough to provide high DC‐regulation accuracy. The phase margin should be greater than 45o for overall stability. Figure 19: Type III Compensation network and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows: FP1 0 FP 2 (26) 1 2 * R10 * C 7 1 FP 3 C * C3 2 * R3 4 C 4 C3 1 FZ 1 2 * R3 * C 4 FZ 2 (27) 1 2 * R3 * C 3 1 1 2 * C 7 * ( R8 R10 ) 2 * C 7 * R8 24 March 5, 2012 | V1.26 (28) (29) (30) For this design we have: Vin = 12V Vo = 1.8V β = Vref/Vo=0.333 Modulator gain = Fm = 0.65, from Figure 15 Vref = 0.6V Lo = 0.215uH Co = 15x22uF, ESR = 3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 12uF at 1.8V DC bias and 600kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator These result in: FLC=25.58kHz FESR=4.4MHz Fs/2=300kHz iP1837 PROGRAMMING THE CURRENT‐LIMIT The Current‐Limit threshold can be set by connecting a resistor (ROCSet) from the SW pin to the OCSet pin. The resistor can be selected by using Table 2. Select crossover frequency Fo=110 kHz Since FLC<Fo<Fs/2<FESR, Type III is selected to place the pole and zeros. In order to set a trip current of 40A, we may select ROCSet = 54.9K, using Table 2. SETTING THE POWER GOOD THRESHOLD Detailed calculation of compensation Type III: Desired Phase Margin Θ = 80° FZ 2 Fo FP 2 Fo 1 sin 9.62 kHz 1 sin 1 sin 1257.31 kHz 1 sin FZ 1 0.5 * FZ 2 4.81 kHz FP 3 0.5 * Fs 300 kHz Select: C7 = 2.2nF Calculate: R3, C3 and C4: R3 2 * Fo * Lo * C o ; R3 4.75 kΩ C 7 * Vin * Fm * A window comparator internally sets a lower Power Good threshold at 0.51V and an upper Power Good threshold at 0.7V. When the voltage at the Voso pin is within the window set by these thresholds, PGood is asserted. The power good output PGD is an open drain output. Hence, it is necessary to use a pull up resistor RPG from PGD pin to Vcc. The value of the pull‐up resistor must be chosen such as to limit the current flowing into the PGD pin, when the output voltage is not in regulation, to less than 5mA. A typical value used is 10kΩ. It must be noted that if the voltage on Voso exceeds the upper threshold 0.7V, not only is PGD de‐asserted, but also an overvoltage fault is flagged, following which, even if the overvoltage condition gets resolved, the converter can be re‐started only by cycling Vcc or Enable. Select: R3 = 4.22 kΩ C4 1 ; C4 7.84 nF, Select : C4 8.2 nF 2 * FZ 1 * R 3 C3 1 ; C3 125.71 pF, Select : C3 120 pF 2 * FP 3 * R3 Calculate: R10, R8 and R9: R10 1 ; R10 60 Ω, Select : R10 57.6 Ω 2 * C7 * FP 2 R8 1 - R10 ; R8 7.46 kΩ, 2 * C7 * FZ 2 Select: R8 = 7.5 kΩ 25 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 35A, Room Temperature, no airflow Figure 20: Start up at 35A Load Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable Figure 21Error! No sequence specified.: Start up at 35A Load Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood Figure 22 : Start up with 1V Pre Bias , 0A Load, Ch2:Vo, Ch3:VSS Figure 23: Output Voltage Ripple, 35A load Ch2: Vout Figure 24 : Inductor node at 35A load Ch2:LX 26 March 5, 2012 | V1.26 Figure 25: Short (Hiccup) Recovery Ch2:Vout , Ch3:Vss 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 26: Transient Response, 3.5A to 14A step (2.5A/us) Ch2:Vout 27 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 27: Transient Response, 24.5A to 35A step (2.5A/us) Ch2:Vout 28 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 35A, Room Temperature Figure 28: Bode Plot at 35A load shows a bandwidth of 104.76kHz and phase margin of 60.247 degrees 29 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 35A, Room Temperature 95 94 93 92 Efficiency (%) 91 90 89 88 87 86 85 84 83 82 2 5 8 11 14 17 20 23 26 29 32 35 Iout (A) No Airflow 200LFM Figure 29: Efficiency versus load current 8 7 Power Loss (W) 6 5 4 3 2 1 0 2 5 8 11 14 17 20 23 26 29 32 35 Iout (A) No Airflow 200 LFM Figure 30: Power loss versus load current 30 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 THERMAL IMAGES Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A‐35A, Room Temperature, 200 LFM Figure 31: Thermal Image of the board at 35A load Test point 1 is iP1837 Test point 2 is inductor 31 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 OTHER APPLICATION CIRCUITS Figure 32: Application with external PVCC=5V Figure 33: Single 5V application 32 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 Vin=3.3V VCC En Vin OCSet PVCC Vo SW Vosp PGood PGD Vosm Rt Voso SS Fb LGnd BiasGnd PGnd Comp Figure 34: Single 3.3V Application 33 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator ground polygon should be connected to BiasGnd through a single point connection using a 0 ohm resistor, at a location away from noise sources. The PGnd pad (Pin 3) should be connected to system power Ground. LAYOUT CONSIDERATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. In order to minimize coupling switching noise into other layers, the area of the switch node copper should be kept small. It is also advisable to keep the switch node copper localized to the top layer. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. The inductor, output capacitors and the iP1837 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. A pair of sense traces running very close to each other and away from any noise sources should be used to implement true differential remote sensing of the voltage. The input capacitors should be placed as close as possible to the PGnd pad. The connection of the Vin pad to the Vin power polygon should be low impedance, using several vias in parallel. The layout must ensure minimum length ground path and enough copper for input and output capacitors with a direct connection. If remote sense is not used, the output voltage sense trace used for feedback should be tapped from a low impedance point such as directly from an output capacitor. The iPOWiR package is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 6‐layers PCB. Figures 35a‐f illustrates the implementation of the layout guidelines outlined above, on the IRDC1837 6 layer demoboard. The iP1837 has a local power ground pad called Bias Gnd (pin 12) for bypassing Vcc or PVcc supplies. The analog or signal ground, LGnd, is used as a separate control circuit ground to which all signals are referenced. The analog Enough copper & minimum length ground path between Input and Output iP1837 Optional on board load transient circuit: Not Critical All bypass caps (Marked in Cyan) should be placed as close as possible to their connecting pins BiasGnd Switch node should have small area and should be localized to Top layer Single Point Connection of AGND and BiasGnd Resistors Rt (marked in Brown) should be placed as close as possible to their pins Compensation parts (Marked in dark blue) should be placed as close as possible to the Comp pin Switch node should have small area and should be localized to Top layer Figure 35a: IRDC1837 demoboard layout considerations – Top Layer 34 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 Remote sense traces, tapped at a low impedance node, such as across a capacitor, shielded by PGND layer are routed very close to each other and away from SW node VOUT Vin Vin PGND GND PGnd All bypass caps (Marked in Cyan) should be placed as close as possible to their connecting pins SW AGnd Vin PGND LGND Vout Figure 35b: IRDC1837 demoboard layout considerations – Bottom Layer VOUT Vin GND GND SW PGND AGND Figure 35c: IRDC1837 demoboard layout considerations – Mid Layer 1 Figure 35d: IRDC1837 demoboard layout considerations – Mid Layer 2 GND PGND GND SW PGND SW Figure 35e: IRDC1837 demoboard layout considerations – Mid Layer 3 35 March 5, 2012 | V1.26 Figure 35f: IRDC1837 demoboard layout considerations – Mid Layer 4 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 METAL AND COMPONENT PLACEMENT Figure 36: PCB Metal and Component Placement * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 36 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 SOLDER RESIST It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. Ensure that the solder resist in‐between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the power pad lands. The three power land pads should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis‐alignment. Figure 37: Solder resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 37 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 STENCIL DESIGN The maximum length and width of the power land pads stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of opens to the lead lands or use the recommended stencil design below. The Stencil apertures for the lead lands should be approximately 80% of the area of the lead pads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the three power land pads the part will float and the lead pads will be open. Figure 38: Stencil design * Contact International Rectifier to receive an electronic PCB Library file in your preferred format. 38 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator MARKING INFORMATION A1 Marking Date Code Assembly Lot Code Part Number iP1837 International Rectifier Logo YYWW xxxxxx 1837PBF CS Factory Code Figure 39: Marking Information PACKAGE INFORMATION Figure 40: Tape and Reel Information 39 March 5, 2012 | V1.26 97600 Highly Integrated 35A Single‐input Voltage, Synchronous Buck Regulator iP1837 7.650 [0.301] 0.15 [.006] C 2X A B 6 NOTES: 1. 2. 3. 4 DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETERS LAND PAD OPENINGS. 5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE LAND PAD OPENINGS. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 7. NOT TO SCALE. CORNER ID 6 7.650 [0.301] TOP VIEW 2X 6 0.15 [.006] C 7.32 0.12 [.005] C 3.62 2.41 1.35 0.28 0.36 1.66 [.065] 4 5 C 14X 0.508 X 0.508 1.43 1.21 2.05 2.49 3.56 3.86 4.63 4.71 5.69 6.76 7.27 BOTTOM VIEW SIDE VIEW Figure 41: Mechanical Outline Drawing Data and specifications subject to change without notice 3/11. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com 40 March 5, 2012 | V1.26 97600