2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP AD7887 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 2.7 V to 5.25 V Flexible power/throughput rate management Shutdown mode: 1 μA max One or two single-ended inputs Serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible 8-lead narrow SOIC and MSOP packages AD7887 AIN0 I/P MUX T/H AIN1/ VREF VDD APPLICATIONS 2.5V REF AIN1/VREF SOFTWARE CONTROL LATCH Battery-powered systems (personal digital assistants, medical instruments, mobile communications) Instrumentation and control systems High speed modems COMP BUF GND CHARGE REDISTRIBUTION DAC SAR + ADC CONTROL LOGIC DIN CS DOUT SCLK 06191-001 SPORT Figure 1. GENERAL DESCRIPTION The AD7887 is a high speed, low power, 12-bit analog-to-digital converter (ADC) that operates from a single 2.7 V to 5.25 V power supply. The AD7887 is capable of 125 kSPS throughput rate. The input track-and-hold acquires a signal in 500 ns and features a single-ended sampling scheme. The output coding for the AD7887 is straight binary, and the part is capable of converting full power signals of up to 2.5 MHz. The AD7887 can be configured for either dual- or single-channel operation via the on-chip control register. There is a default single-channel mode that allows the AD7887 to be operated as a read-only ADC. In single-channel operation, there is one analog input (AIN0) and the AIN1/VREF pin assumes its VREF function. This VREF pin allows the user access to the part’s internal 2.5 V reference, or the VREF pin can be overdriven by an external reference to provide the reference voltage for the part. This external reference voltage has a range of 2.5 V to VDD. The analog input range on AIN0 is 0 to VREF. In dual-channel operation, the AIN1/VREF pin assumes its AIN1 function, providing a second analog input channel. In this case, the reference voltage for the part is provided via the VDD pin. As a result, the input voltage range on both the AIN0 and AIN1 inputs is 0 to VDD. CMOS construction ensures low power dissipation of typically 2 mW for normal operation and 3 μW in power-down mode. The part is available in an 8-lead, 0.15-inch-wide narrow body SOIC and an 8-lead MSOP package. PRODUCT HIGHLIGHTS 1. Smallest 12-bit dual-/single-channel ADC; 8-lead MSOP package. 2. Lowest power 12-bit dual-/single-channel ADC. 3. Flexible power management options, including automatic power-down after conversion. 4. Read-only ADC capability. 5. Analog input range from 0 V to VREF. 6. Versatile serial input/output port (SPI/QSPI/MICROWIRE/ DSP compatible). Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD7887 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Circuit Information.................................................................... 11 Functional Block Diagram .............................................................. 1 Converter Operation.................................................................. 11 General Description ......................................................................... 1 ADC Transfer Function ............................................................. 11 Product Highlights ........................................................................... 1 Typical Connection Diagram ................................................... 11 Revision History ............................................................................... 2 Analog Input ............................................................................... 12 Specifications..................................................................................... 3 Power-Down Options ................................................................ 13 Timing Specifications .................................................................. 5 Power vs. Throughput Rate ....................................................... 13 Absolute Maximum Ratings............................................................ 6 Modes of Operation ................................................................... 13 ESD Caution .................................................................................. 6 Serial Interface ............................................................................ 17 Pin Configurations and Function Descriptions ........................... 7 Microprocessor Interfacing ....................................................... 18 Typical Performance Characteristics ............................................. 8 Application Hints ....................................................................... 20 Terminology ...................................................................................... 9 Outline Dimensions ....................................................................... 21 Control Register .............................................................................. 10 Ordering Guide .......................................................................... 21 REVISION HISTORY 2/09—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 21 9/06—Rev. B to Rev. C Updated Format .................................................................. Universal Change to Absolute Maximum Ratings......................................... 6 Additions to Pin Configurations .................................................... 7 Added Table 7.................................................................................. 18 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 Rev. D | Page 2 of 24 AD7887 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VREF = 2.5 V, external/internal reference unless otherwise noted, fSCLK = 2 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio (SNR) 2, 3 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 Full-Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error2 Offset Error Match2 Gain Error2 Gain Error Match2 ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT REFIN Input Voltage Range Input Impedance REFOUT Output Voltage REFOUT Temperature Coefficient LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 5 Output Coding A Version 1 B Version1 Unit Test Conditions/Comments 71 −80 –80 71 −80 −80 dB typ dB typ dB typ fIN = 10 kHz sine wave, fSAMPLE = 125 kSPS fIN = 10 kHz sine wave, fSAMPLE = 125 kSPS fIN = 10 kHz sine wave, fSAMPLE = 125 kSPS −80 −80 −80 2.5 −80 −80 −80 2.5 dB typ dB typ dB typ MHz typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS fIN = 25 kHz @ 3 dB Any channel 12 ±2 ±2 ±3 ±4 ±6 0.5 ±2 ±1 ±6 2 12 ±1 ±1 ±3 ±4 ±6 0.5 ±2 ±1 ±6 2 Bits LSB max LSB max LSB max LSB max LSB typ LSB max LSB max LSB max LSB typ LSB max 0 to VREF ±5 20 0 to VREF ±5 20 V μA max pF typ 2.5/VDD 10 2.45/2.55 ±50 2.5/VDD 10 2.45/2.55 ±50 V min/max kΩ typ V min/max ppm/°C typ Functional from 1.2 V Very high impedance if internal reference disabled 2.4 2.1 0.8 ±1 10 2.4 2.1 0.8 ±1 10 V min V min V max μA max pF max VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V VDD = 2.7 V to 5.25 V Typically 10 nA, VIN = 0 V or VDD VDD − 0.5 VDD − 0.5 0.4 0.4 ±1 ±1 10 10 Straight (Natural) Binary V min V max μA max pF max Rev. D | Page 3 of 24 Guaranteed no missing codes to 11 bits (A Grade) VDD = 5 V, dual-channel mode VDD = 3 V, dual-channel mode Single-channel mode Dual-channel mode Single-channel mode, external reference Single-channel mode, internal reference ISOURCE = 200 μA VDD = 2.7 V to 5.25 V ISINK = 200 μA AD7887 Parameter CONVERSION RATE Throughput Time A Version 1 B Version1 Unit Test Conditions/Comments 16 16 SCLK cycles Conversion time plus acquisition time is 125 kSPS, with 2 MHz Clock Track/Hold Acquisition Time2 Conversion Time POWER REQUIREMENTS VDD IDD Normal Mode5 (Mode 2) Static Operational (fSAMPLE = 125 kSPS) 1.5 14.5 1.5 14.5 SCLK cycles SCLK cycles +2.7/+5.25 +2.7/+5.25 V min/max 700 850 700 450 120 12 210 1 2 3.5 2.1 5 3 1.05 630 700 850 700 450 120 12 210 1 2 3.5 2.1 5 3 1.05 630 μA max μA typ μA typ μA typ μA typ μA typ μA max μA max μA max mW max mW max μW max μW max mW max μW max Using Standby Mode (Mode 4) Using Shutdown Mode (Modes 1, 3) Standby Mode 6 Shutdown Mode6 Normal Mode Power Dissipation Shutdown Power Dissipation Standby Power Dissipation 1 7.25 μs (2 MHz Clock) Internal reference enabled Internal reference disabled fSAMPLE = 50 kSPS fSAMPLE = 10 kSPS fSAMPLE = 1 kSPS VDD = 2.7 V to 5.25 V VDD = 2.7 V to 3.6 V VDD = 4.75 V to 5.25 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Temperature range for A and B versions is −40°C to +125°C. See the Terminology section. 3 SNR calculation includes distortion and noise components. 4 Sample tested at +25°C to ensure compliance. 5 All digital inputs at GND except CS at VDD. No load on the digital outputs. Analog inputs at GND. 6 SCLK at GND when SCLK off. All digital inputs at GND except for CS at VDD. No load on the digital outputs. Analog inputs at GND. 2 Rev. D | Page 4 of 24 AD7887 TIMING SPECIFICATIONS 1 Table 2. Parameter fSCLK 2 tCONVERT tACQ t1 t2 3 t33 t4 t5 t6 t7 t8 4 t9 Limit at TMIN, TMAX (A, B Versions) 4.75 V to 5.25 V 2.7 V to 3.6 V 2 2 14.5 × tSCLK 14.5 × tSCLK 1.5 × tSCLK 1.5 × tSCLK 10 10 30 60 75 100 20 20 20 20 0.4 × tSCLK 0.4 × tSCLK 0.4 × tSCLK 0.4 × tSCLK 80 80 5 5 Unit MHz max Description Throughput time = tCONVERT + tACQ = 16 tSCLK CS to SCLK setup time Delay from CS until DOUT three-state disabled Data access time after SCLK falling edge Data setup time prior to SCLK rising edge Data valid to SCLK hold time SCLK high pulse width SCLK low pulse width CS rising edge to DOUT high impedance Power-up time from shutdown ns min ns max ns max ns min ns min ns min ns min ns max μs typ 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 2 200µA 1.6V CL 50pF 200µA IOH 06191-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 5 of 24 AD7887 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to AGND Analog Input Voltage to AGND Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN/REFOUT to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial Temperature Range A, B Versions Storage Temperature Range Junction Temperature SOIC or MSOP Package Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Pb-Free Temperature, Soldering Reflow ESD 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +150°C +150°C 450 mW 157°C/W (SOIC) 205.9°C/W (MSOP) 56°C/W (SOIC) 43.74°C/W (MSOP) 215°C 220°C 260(0)°C 4 kV Transient currents of up to 100 mA do not cause SCR latch-up. Rev. D | Page 6 of 24 AD7887 AD7887 8 SCLK CS 1 7 DOUT VDD 2 GND 3 6 DIN TOP VIEW AIN1/VREF 4 (Not to Scale) 5 AIN0 GND 3 06191-003 CS 1 VDD 2 AIN1/VREF 4 Figure 3. SOIC_N Pin Configuration AD7887 TOP VIEW (Not to Scale) 8 SCLK 7 DOUT 6 DIN 5 AIN0 06191-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. MSOP Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic CS 2 VDD 3 GND 4 AIN1/VREF 5 AIN0 6 DIN 7 DOUT 8 SCLK Description Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode. Power Supply Input. The VDD range for the AD7887 is from 2.7 V to 5.25 V. When the AD7887 is configured for two-channel operation, this pin also provides the reference source for the part. Ground Pin. This pin is the ground reference point for all circuitry on the AD7887. In systems with separate AGND and DGND planes, these planes should be tied together as close as possible to this GND pin. Where this is not possible, this GND pin should connect to the AGND plane. Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/output. In this case, the user can either access the internal 2.5 V reference or overdrive the internal reference with the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.2 V to VDD. In twochannel mode, this pin provides the second analog input channel, AIN1. The input voltage range on AIN1 is 0 to VDD. Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to VREF. In dualchannel mode, it has an analog input range of 0 to VDD. Data In. Logic Input. Data to be written to the AD7887’s control register is provided on this input and clocked into the register on the rising edge of SCLK (see the Control Register section). The AD7887 can be operated as a single-channel, read-only ADC by tying the DIN line permanently to GND. Data Out. Logic output. The conversion result from the AD7887 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part and writing serial data to the control register. This clock input is also used as the clock source for the AD7887’s conversion process. Rev. D | Page 7 of 24 AD7887 TYPICAL PERFORMANCE CHARACTERISTICS 0 –75 4096 POINT FFT SAMPLING 125kSPS fIN = 10kHz SNR = 71dB –10 –77 –79 –30 VDD = 5.5V/2.7V 100mV p-p SINE WAVE ON VDD REFIN = 2.488V EXT REFERENCE PSRR (dB) –81 –50 –83 –85 –87 –70 –89 –90 –93 2.65 06191-005 61.03516 54.93164 48.82813 42.72461 36.62109 30.51758 24.41406 18.31055 12.20703 6.103516 0 –110 Figure 5. Dynamic Performance VDD = 5V 5V EXT REFERENCE 72.0 71.5 42.14 06191-006 SNR (dB) 72.5 10.89 31.59 21.14 INPUT FREQUENCY (kHz) 23.15 33.65 43.85 INPUT FREQUENCY (kHz) Figure 7. PSRR vs. Frequency 73.0 71.0 0.15 12.85 Figure 6. SNR vs. Input Frequency Rev. D | Page 8 of 24 54.35 64.15 06191-007 –91 AD7887 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Offset Error Match This is the difference in offset error between any two channels. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, VREF − 1.5 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in gain error between any two channels. Track/Hold Acquisition Time The track/hold amplifier returns to track mode at the end of conversion. Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of a conversion. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb). The AD7887 is tested using the CCIF standard in which two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 25 kHz sine wave signal to the nonselected input channel and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across both channels for the AD7887. Thus for a 12-bit converter, this is 74 dB. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition, but not the converter’s linearity. PSR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. See Figure 7. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7887, it is defined as PSRR is defined as the ratio of the power in the ADC output at frequency f to the power of a full-scale sine wave applied to the ADC of frequency fS: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB THD(dB) = 20 log PSRR (dB) = 10 log(Pf/Pfs) V2 2 + V3 2 + V 4 2 + V5 2 + V6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. where Pf is the power at frequency f in ADC output and Pfs is the power at frequency fS in ADC full-scale input. Rev. D | Page 9 of 24 AD7887 CONTROL REGISTER The control register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer. Only the information provided on the first eight rising clock edges after CS falling edge is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 5. The contents of the control register on power up is all 0s. MSB DONTC ZERO REF SIN/DUAL CH ZERO PM1 PM0 Table 5. Control Register Bit 7 Mnemonic DONTC 6 5 ZERO REF 4 SIN/DUAL 3 CH 2 1, 0 ZERO PM1, PM0 Comment Don’t Care. The value written to this bit of the control register is a don’t care, that is, it doesn’t matter if the bit is 0 or 1. A zero must be written to this bit to ensure correct operation of the AD7887. Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is disabled. Single/Dual Bit. This bit determines whether the AD7887 operates in single-channel or dual-channel mode. A 0 in this bit selects single-channel operation and the AIN1/VREF pin assumes its VREF function. A 1 in this bit selects dual-channel mode, with the reference voltage for the ADC internally connected to VDD and the AIN1/VREF pin assuming its AIN1 function as the second analog input channel. To obtain best performance from the AD7887, the internal reference should be disabled when operating in the dual-channel mode, that is, REF = 1. Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel is converted for the next conversion. A 0 in this bit selects the AIN0 input, and a 1 in this bit selects the AIN1 input. In singlechannel mode, this bit should always be 0. A 0 must be written to this bit to ensure correct operation of the AD7887. Power Management Bits. These two bits decode the mode of operation of the AD7887 as described in Table 6. Table 6. Power Management Options PM1 0 PM0 0 0 1 1 0 1 1 Mode Mode 1. In this mode, the AD7887 enters shutdown if the CS input is 1 and is in full power mode when CS is 0. Thus the part comes out of shutdown on the falling edge of CS and enters shutdown on the rising edge of CS. Mode 2. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic inputs. Mode 3. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion, regardless of the state of CS. Mode 4. In this standby mode, portions of the AD7887 are powered down but the on-chip reference voltage remains powered up. This mode is similar to Mode 3, but allows the part to power up much faster. The REF bit should be 0 to ensure that the on-chip reference is enabled. Rev. D | Page 10 of 24 AD7887 THEORY OF OPERATION CHARGE REDISTRIBUTION DAC CIRCUIT INFORMATION The AD7887 provides the user with an on-chip, track/hold analog-to-digital converter reference and a serial interface housed in an 8-lead package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The part can be configured for singlechannel or dual-channel operation. When configured as a single-channel part, the analog input range is 0 to VREF (where the externally applied VREF can be between 1.2 V and VDD). When the AD7887 is configured for two input channels, the input range is determined by internal connections to be 0 to VDD. SW1 The output coding of the AD7887 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristic for the AD7887 is shown in Figure 10. SAMPLING CAPACITOR CONTROL LOGIC 111 ... 111 111 ... 110 SW2 COMPARATOR (REF IN/REF OUT)/2 Figure 8. ADC Acquisition Phase 1LSB = VREF /4096 011 ... 111 000 ... 010 000 ... 001 000 ... 000 0V 0.5LSB ANALOG INPUT +VREF – 1.5LSB 06191-010 ADC CODE 111 ... 000 Figure 10. Transfer Characteristic TYPICAL CONNECTION DIAGRAM Figure 11 shows a typical connection diagram for the AD7887. The GND pin is connected to the analog ground plane of the system. The part is in dual-channel mode so VREF is internally connected to a well-decoupled VDD pin to provide an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. For applications where power consumption is of concern, the automatic power-down at the end of conversion should be used to improve power performance. See the Modes of Operation section. SUPPLY 2.7V TO 5.25V When the ADC starts a conversion (see Figure 9), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge-redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 10 shows the ADC transfer function. 10µF 0.1µF SERIAL INTERFACE VDD AD7887 0V TO VDD INPUT AIN1 SCLK AIN2 DOUT DIN GND CS Figure 11. Typical Connection Diagram Rev. D | Page 11 of 24 µC/µP 06191-011 ACQUISITION PHASE 06191-008 AGND COMPARATOR ADC TRANSFER FUNCTION CHARGE REDISTRIBUTION DAC B SW2 Figure 9. ADC Conversion Phase The AD7887 is a successive approximation ADC built around a charge-redistribution DAC. Figure 8 and Figure 9 show simplified schematics of the ADC. Figure 8 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on AIN. SW1 CONVERSION PHASE (REF IN/REF OUT)/2 CONVERTER OPERATION A CONTROL LOGIC B AGND If single-channel operation is required, the AD7887 can be operated in a read-only mode by tying the DIN line permanently to GND. For applications where the user wants to change the mode of operation or wants to operate the AD7887 as a dualchannel ADC, the DIN line can be used to clock data into the part’s control register. AIN SAMPLING CAPACITOR A VIN 06191-009 The AD7887 is a fast, low power, 12-bit, single-supply, singlechannel/dual-channel ADC. The part can be operated from a 3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply. When operated from either a 5 V or 3 V supply, the AD7887 is capable of throughput rates of 125 kSPS when provided with a 2 MHz clock. AD7887 –65 ANALOG INPUT VDD D1 R1 VIN D2 CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED 06191-012 C1 4pF C2 20pF Figure 12. Equivalent Analog Input Circuit For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of op amp is a function of the particular application. VDD = 5V 5V EXT REFERENCE RIN = 1kΩ, CIN = 100pF –75 RIN = 50Ω, CIN = 2.2nF –80 –85 10.89 21.14 31.59 INPUT FREQUENCY (kHz) 49.86 42.14 06191-013 RIN = 10Ω, CIN = 10nF –90 0.15 Figure 13. THD vs. Analog Input Frequency On-Chip Reference The AD7887 has an on-chip 2.5 V reference. This reference can be enabled or disabled by clearing or setting the REF bit in the control register, respectively. If the on-chip reference is to be used externally in a system, it must be buffered before it is applied elsewhere. If an external reference is applied to the device, the internal reference is automatically overdriven. However, it is advised to disable the internal reference by setting the REF bit in the control register when an external reference is applied in order to obtain optimum performance from the device. When the internal reference is disabled, SW1, shown in Figure 14, opens and the input impedance seen at the AIN1/VREF pin is the input impedance of the reference buffer, which is in the region of gigaohms. When the internal reference is enabled, the input impedance seen at the pin is typically 10 kΩ. When the AD7887 is operated in two-channel mode, the reference is taken from VDD internally, not from the on-chip 2.5 V reference. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 13 shows a graph of the total harmonic distortion vs. the analog input signal frequency for different source impedances. Rev. D | Page 12 of 24 AIN1/VREF SW1 10kΩ 2.5V Figure 14. On-Chip Reference Circuitry 06191-014 Note that the analog input capacitance seen when in track mode is typically 38 pF, whereas in hold mode it is typically 4 pF. –70 THD (dB) Figure 12 shows an equivalent circuit of the analog input structure of the AD7887. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceed the supply rails by more than 200 mV. Exceeding this value causes the diodes to become forward biased and to start conducting into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 20 mA. However, it is worth noting that a small amount of current (1 mA) being conducted into the substrate due to an overvoltage on an unselected channel can cause inaccurate conversions on a selected channel. Capacitor C1 in Figure 12 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch. This resistor is typically about 100 Ω. Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 20 pF. THD vs. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES AD7887 power vs. throughput rate for automatic shutdown with both 5 V and 3 V supplies. POWER-DOWN OPTIONS The AD7887 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. 10 VDD = 5V SCLK = 2MHz 1 POWER (mW) VDD = 3V SCLK = 2MHz 0.1 0.01 0 10 20 30 THROUGHPUT RATE (kSPS) 40 50 06191-015 The power management options are selected by programming the power management bits (that is, PM1 and PM0) in the control register. Table 6 summarizes the available options. When the power management bits are programmed for either of the auto power-down modes, the part enters power-down mode on the 16th rising SCLK edge after the falling edge of CS. The first falling SCLK edge after the CS falling edge causes the part to power up again. When the AD7887 is in Mode 1, that is, PM1 = PM0 = 0, the part enters shutdown on the rising edge of CS and power up from shutdown on the falling edge of CS. If CS is brought high during the conversion in this mode, the part immediately enters shutdown. Figure 15. Power vs. Throughput Rate Power-Up Times MODES OF OPERATION The AD7887 has an approximate 1 μs power-up time when powering up from standby or when using an external reference. When VDD is first connected the AD7887 powers up in Mode 1, that is, PM1 = PM0 = 0. The part is put into shutdown on the rising edge of CS in this mode. A subsequent power-up from shutdown takes approximately 5 μs. The AD7887 wake-up time is very short in the autostandby mode; therefore, it is possible to wake up the part and carry out a valid conversion in the same read/write operation. The AD7887 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The modes of operation are controlled by the PM1 and PM0 bits of the control register, as previously outlined in Table 6. For read-only operation of the AD7887, the default mode of all 0s in the control register can be set up by tying the DIN line permanently low. POWER VS. THROUGHPUT RATE By operating the AD7887 in autoshutdown mode, autostandby mode, or Mode 1, the average power consumption of the AD7887 decreases at lower throughput rates. Figure 15 shows how as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. For example, if the AD7887 is operated in a continuous sampling mode with a throughput rate of 10 kSPS and a SCLK of 2 MHz (VDD = 5 V), PM1 = 1 and PM0 = 0, that is, the device is in autoshutdown mode, and the on-chip reference is used, the power consumption is calculated as follows: The power dissipation during normal operation is 3.5 mW (VDD = 5 V). If the power-up time is 5 μs and the remaining conversion plus acquisition time is 15.5 tSCLK, that is, approximately 7.75 μs (see Figure 18), the AD7887 can be said to dissipate 3.5 mW for 12.75 μs during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 μs and the average power dissipated during each cycle is (12.75/100) × (3.5 mW) = 446.25 μW. If VDD = 3 V, SCLK = 2 MHz, and the device is in autoshutdown mode using the on-chip reference, the power dissipation during normal operation is 2.1 mW. The AD7887 can now be said to dissipate 2.1 mW for 12.75 μs during each conversion cycle. With a throughput rate of 10 kSPS, the average power dissipated during each cycle is (12.75/100) × (2.1 mW) = 267.75 μW. Figure 15 shows the Mode 1 (PM1 = 0, PM0 = 0) This mode allows the user to control the powering down of the part via the CS pin. Whenever CS is low, the AD7887 is fully powered up; whenever CS is high, the AD7887 is in full shutdown. When CS goes from high to low, all on-chip circuitry starts to power up. It takes approximately 5 μs for the AD7887 internal circuitry to be fully powered up. As a result, a conversion (or sample-and-hold acquisition) should not be initiated during this 5 μs. Figure 16 shows a general diagram of the operation of the AD7887 in this mode. The input signal is sampled on the second rising edge of SCLK following the CS falling edge. The user should ensure that 5 μs elapses between the falling edge of CS and the second rising edge of SCLK. In microcontroller applications, this is readily achievable by driving the CS input from one of the port lines and ensuring that the serial data read (from the microcontrollers serial port) is not initiated for 5 μs. In DSP applications, where CS is generally derived from the serial frame synchronization line, it is usually not possible to separate the CS falling edge and second SCLK rising edge by up to 5 μs without affecting the speed of the rest of the serial clock. Therefore, the user must write to the control register to exit this mode and (by writing PM1 = 0 and PM0 = 1) put the part into Mode 2, that is, normal mode. A second conversion needs to be initiated when the part is powered up to get a conversion result. The write operation that takes place in conjunction with this Rev. D | Page 13 of 24 AD7887 second conversion can put the part back into Mode 1, and the part goes into power-down mode when CS returns high. Mode 2 (PM1 = 0, PM0 = 1) In this mode of operation, the AD7887 remains fully powered up regardless of the status of the CS line. It is intended for fastest throughput rate performance because the user does not have to worry about the 5 μs power-up time previously mentioned. Figure 17 shows the general diagram of the operation of the AD7887 in this mode. The data presented to the AD7887 on the DIN line during the first eight clock cycles of the data transfer are loaded to the control register. To continue to operate in this mode, the user must ensure that PM1 is loaded with 0 and PM0 is loaded with 1 on every data transfer. The falling edge of CS initiates the sequence, and the input signal is sampled on the second rising edge of the SCLK input. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. Once a data transfer is complete (that is, once CS returns high), another conversion can be initiated immediately by bringing CS low again. Mode 3 (PM1 = 1, PM0 = 0) In this mode, the AD7887 automatically enters its full shutdown mode at the end of every conversion. It is similar to Mode 1 except that the status of CS does not have any effect on the power-down status of the AD7887. Figure 18 shows the general diagram of the operation of the AD7887 in this mode. On the first falling SCLK edge after CS goes low, all on-chip circuitry starts to power up. It takes approximately 5 μs for the AD7887 internal circuitry to be fully powered up. As a result, a conversion (or sample-and-hold acquisition) should not be initiated during this 5 μs. The input signal is sampled on the second rising edge of SCLK following the CS falling edge. The user should ensure that 5 μs elapses between the first falling edge of SCLK and the second rising edge of SCLK after the CS falling edge, as shown in Figure 18. In microcontroller applications (or with a slow serial clock), this is readily achievable by driving the CS input from one of the port lines and ensuring that the serial data read (from the microcontroller’s serial port) is not initiated for 5 μs. However, for higher speed serial clocks, it will not be possible to have a 5 μs delay between powering up and the first rising edge of the SCLK. Therefore, the user must write to the control register to exit this mode and (by writing PM1 = 0 and PM0 = 1) put the part into Mode 2. A second conversion needs to be initiated when the part is powered up to get a conversion result, as shown in Figure 19. The write operation that takes place in conjunction with this second conversion can put the part back into Mode 3, and the part goes into power-down mode when the conversion sequence ends. Mode 4 (PM1 = 1, PM0 = 1) In this mode, the AD7887 automatically enters a standby (or sleep) mode at the end of every conversion. In this standby mode, all on-chip circuitry, apart from the on-chip reference, is powered down. This mode is similar to Mode 3, but, in this case, the power-up time is much shorter because the on-chip reference remains powered up at all times. Figure 20 shows the general diagram of the operation of the AD7887 in this mode. On the first falling SCLK edge after CS goes low, the AD7887 comes out of standby. The AD7887 wakeup time is very short in this mode, so it is possible to wake up the part and carry out a valid conversion in the same read/write operation. The input signal is sampled on the second rising edge of SCLK following the CS falling edge. At the end of conversion (last rising edge of SCLK), the part automatically enters its standby mode. Rev. D | Page 14 of 24 AD7887 THE PART POWERS UP ON CS FALLING EDGE AS PM1 AND PM0 = 0 THE PART POWERS DOWN ON CS RISING EDGE AS PM1 AND PM0 = 0 CS 16 1 SCLK FOUR LEADING ZEROS + CONVERSION RESULT DOUT DIN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE 06191-016 DATA IN Figure 16. Mode 1 Operation THE PART REMAINS POWERED UP AT ALL TIMES AS PM1 = 0 AND PM0 = 1 CS 16 1 SCLK DIN FOUR LEADING ZEROS + CONVERSION RESULT DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE Figure 17. Mode 2 Operation Rev. D | Page 15 of 24 06191-017 DOUT AD7887 THE PART ENTERS SHUTDOWN AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = 0 THE PART POWERS UP FROM SHUTDOWN ON SCLK FALLING EDGE AS PM1 = 1 AND PM0 = 0 CS 16 1 1 16 2 SCLK t10 = 5µs FOUR LEADING ZEROS + CONVERSION RESULT FOUR LEADING ZEROS + CONVERSION RESULT DATA IN DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0 06191-018 DOUT PM1 = 1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE Figure 18. Mode 3 Operation (Microcontroller for Slow SCLKs) THE PART ENTERS SHUTDOWN AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = 0 THE PART BEGINS TO POWER UP FROM SHUTDOWN THE PART REMAINS POWERED UP AS PM1 = 0 AND PM0 = 1 THE PART ENTERS SHUTDOWN AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = 0 CS 1 8 8 1 16 16 8 1 16 SCLK FOUR LEADING ZEROS + CONVERSION RESULT DATA IN DATA IN DIN FOUR LEADING ZEROS + CONVERSION RESULT CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0 DATA IN PM1 = 0 AND PM0 = 1 TO PLACE THE PART IN NORMAL MODE 06191-019 FOUR LEADING ZEROS + CONVERSION RESULT DOUT PM1 = 1 AND PM0 = 0 TO PLACE THE PART BACK IN MODE 3 Figure 19. Mode 3 Operation (Microcontroller for High Speed SCLKs) THE PART ENTERS STANDBY AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = 1 THE PART POWERS UP FROM STANDBY ON SCLK FALLING EDGE AS PM1 = 1 AND PM0 = 1 CS 16 1 16 1 SCLK DIN FOUR LEADING ZEROS + CONVERSION RESULT FOUR LEADING ZEROS + CONVERSION RESULT DATA IN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 1 Figure 20. Mode 4 Operation Rev. D | Page 16 of 24 PM1 = 1 AND PM0 = 1 TO KEEP THE PART IN THIS MODE 06191-020 DOUT AD7887 the channel address for the next conversion while the present conversion is in progress. SERIAL INTERFACE Figure 21 shows the detailed timing diagrams for serial interfacing to the AD7887. The serial clock provides the conversion clock and also controls the transfer of information to and from the AD7887 during conversion. Writing of information to the control register takes place on the first eight rising edges of SCLK in a data transfer. The control register is always written to when a data transfer takes place. However, the AD7887 can be operated in a read-only mode by tying DIN low, thereby loading all 0s to the control register every time. When operating the AD7887 in write/read mode, the user must be careful to always set up the correct information on the DIN line when reading data from the part. CS initiates the data transfer and conversion process. For some modes, the falling edge of CS wakes up the part. In all cases, it gates the serial clock to the AD7887 and puts the on-chip track/hold into track mode. The input signal is sampled on the second rising edge of the SCLK input after the falling edge of CS. Thus, the first one and one-half clock cycles after the falling edge of CS are when the acquisition of the input signal takes place. This time is denoted as the acquisition time (tACQ). In modes where the falling edge of CS wakes up the part, the acquisition time must allow for the wake-up time of 5 μs. The on-chip track/hold goes from track mode to hold mode on the second rising edge of SCLK, and a conversion is also initiated on this edge. The conversion process takes an additional fourteen and one-half SCLK cycles to complete. The rising edge of CS puts the bus back into three-state. If CS is left low, a new conversion can be initiated. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7887. In applications where the first serial clock edge following CS going low is a falling edge, this edge clocks out the first leading zero. Thus, the first rising clock edge on the SCLK clock has the first leading zero provided. In applications where the first serial clock edge following CS going low is a rising edge, the first leading zero may not be set up in time for the processor to read it correctly. However, subsequent bits are clocked out on the falling edge of SCLK so that they are provided to the processor on the following rising edge. Thus, the second leading zero is clocked out on the falling edge subsequent to the first rising edge. The final bit in the data transfer is valid on the 16th rising edge, having been clocked out on the previous falling edge. In dual-channel operation, the input channel that is sampled is the one that was selected in the previous write to the control register. Thus, in dual-channel operation, the user must write tACQ tCONVERT CS t6 t1 DOUT 2 1 SCLK THREESTATE 3 t2 4 5 t7 6 15 16 t8 t3 FOUR LEADING ZEROS DB11 DB10 DB9 DB0 THREESTATE t5 DIN DONTC ZERO REF SIN/DUAL CH ZERO PM1 Figure 21. Serial Interface Timing Diagram Rev. D | Page 17 of 24 PM0 06191-021 t4 AD7887 The serial interface on the AD7887 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7887 with some of the more common microcontroller and DSP serial interface protocols. AD7887 to TMS320C5x The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7887. The CS input allows easy interfacing with an inverter between the serial clock of the TMS320C5x and the AD7887 being the only glue logic required. The serial port of the TMS320C5x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 22. TMS320C5x1 CLKX SCLK CLKR DOUT DR DIN DT CS FSX The timer registers are loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and hence the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before a transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, a SCLK of 2 MHz is obtained and eight master clock periods will elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer number of N, equidistant sampling will be implemented by the DSP. FSR 06191-022 1ADDITIONAL AD78871 PINS OMITTED FOR CLARITY. Figure 22. Interfacing to the TMS320C5x SCLK DOUT DR DIN DT AD7887 to ADSP-21xx CS The ADSP-21xx family of DSPs are easily interfaced to the AD7887 with an inverter between the serial clock of the ADSP21xx and the AD7887. This is the only glue logic required. The SPORT control register should be set up as follows: RFS TFS 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 23. Interfacing to the ADSP-21xx AD7887 to DSP56xxx Table 7. SPORT0 Control Register Setup Setting TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 SLEN = 1111 ISCLK = 1 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 ADSP-21xx1 SCLK The connection diagram in Figure 24 shows how the AD7887 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with an internally generated 1-bit clock period frame sync for both Tx and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An inverter is also necessary between the SCLK from the DSP56xxx and the SCLK pin of the AD7887, as shown in Figure 24. Description Alternative framing Active low frame signal Right justify data 16-bit data-word Internal serial clock Frame every word AD78871 The connection diagram is shown in Figure 23. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described in Table 7. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. In 1ADDITIONAL Rev. D | Page 18 of 24 DSP56xxx1 SCLK SCK DOUT SRD DIN STD CS SC2 PINS OMITTED FOR CLARITY. Figure 24. Interfacing to the DSP56xxx 06191-024 AD78871 this example however, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling cannot be achieved. 06191-023 MICROPROCESSOR INTERFACING AD7887 AD7887 to MC68HC11 AD78871 SCLK/PD4 DOUT MISO/PD2 DIN MOSI/PD3 DIN P1.2 CS P1.3 AD7887 to PIC16C6x/PIC16C7x PA0 1ADDITIONAL PINS OMITTED FOR CLARITY. P1.1 Figure 26. Interfacing to the 8051 Using Input/Output Ports 06191-025 CS DOUT Figure 25. Interfacing to the MC68HC11 AD7887 to 8051 The PIC16C6x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 1. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/PIC17 Microcontroller User Manual. Figure 27 shows the hardware connections needed to interface to the PIC16C6x/ PIC16C7x. In this example, input/output port RA1 is being used to pulse CS. This microcontroller only transfers eight bits of data during each serial transfer operation. Therefore, two consecutive read/write operations are needed. It is possible to implement a serial interface using the data ports on the 8051. This allows a full duplex serial transfer to be implemented. The technique involves bit-banging an input/output port (for example, P1.0) to generate a serial clock and using two other input/output ports (for example, P1.1 and P1.2) to shift data in and out—see Figure 26. PIC16C6x/ PIC16C7x1 AD78871 SCLK SCK/RC3 DOUT SDI/RC4 DIN CS 1ADDITIONAL SDO/RC5 RA1 PINS OMITTED FOR CLARITY. Figure 27. Interfacing to the PIC16C6x/PIC16C7x Rev. D | Page 19 of 24 06191-027 SCLK P1.0 1ADDITIONAL PINS OMITTED FOR CLARITY. MC68HC111 AD78871 80511 SCLK 06191-026 The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1) when the clock polarity bit (CPOL) = 1 and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)—see the M68HC11 reference manual from Freescale Semiconductor, Inc., for more information. The serial transfer takes place as two 8-bit operations. A connection diagram is shown in Figure 25. AD7887 APPLICATION HINTS Grounding and Layout The AD7887 has very good immunity to noise on the power supplies, as can be seen in Figure 7. However, care should still be taken with regard to grounding and layout. The printed circuit board that houses the AD7887 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it results in the best shielding. Digital and analog ground planes should be joined in only one place, as close as possible to the GND pin of the AD7887. If the AD7887 is in a system where multiple devices require AGND-to-DGND connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7887. Avoid running digital lines under the device because these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7887 to avoid noise coupling. The power supply lines to the AD7887 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best approach, but it is not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. Evaluating the AD7887 Performance The recommended layout for the AD7887 is outlined in the evaluation board for the AD7887. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7887 evaluation board, as well as many other Analog Devices, Inc., evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7887. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7887. Rev. D | Page 20 of 24 AD7887 OUTLINE DIMENSIONS 3.20 3.00 2.80 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 8 3.20 3.00 2.80 0.50 (0.0196) 0.25 (0.0099) 45° 0.25 (0.0098) 0.17 (0.0067) 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1 5 PIN 1 8° 0° 1.10 MAX 0.15 0.00 060506-A 4.00 (0.1574) 3.80 (0.1497) Figure 28. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.38 0.22 COPLANARITY 0.10 0.23 0.08 0.80 0.60 0.40 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 29. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD7887AR AD7887AR-REEL AD7887AR-REEL7 AD7887ARZ 2 AD7887ARZ-REEL2 AD7887ARZ-REEL72 AD7887ARM AD7887ARM-REEL AD7887ARM-REEL7 AD7887ARMZ2 AD7887ARMZ-REEL2 AD7887ARMZ-REEL72 AD7887BR AD7887BR-REEL AD7887BR-REEL7 AD7887BRZ2 AD7887BRZ-REEL2 AD7887BRZ-REEL72 AD7887WARMZ2, 3 EVAL-AD7887CB 4 EVAL-CONTROL BRD2 5 Linearity Error 1 ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±2 LSB Temperature −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] Evaluation Board Controller Board 1 Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 Branding C5A C5A C5A C5A# C5A# C5A# C5A# Linearity error here refers to integral linearity error. Z = RoHS Compliant Part, # denotes lead-free product, may be top or bottom marked. Qualified for automotive. 4 This can be used as a standalone evaluation board or can be used in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. 2 3 Rev. D | Page 21 of 24 AD7887 NOTES Rev. D | Page 22 of 24 AD7887 NOTES Rev. D | Page 23 of 24 AD7887 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06191-0-2/09(D) Rev. D | Page 24 of 24