F75121 F75121R/RG Dynamic VID Control + 8 GPIO Datasheet Release Date: July, 2007 Revision: V0.24P F75121 V0.24P July, 2007 F75121 F75121R/RG Datasheet Revision History Version Date Page Revision History 0.20P Apr/2003 0.21P Oct/2003 6 0.22P Jan/2004 5-7 Revise pin name and pin description 0.23P Dec/2005 42 Update Green Package Ordering Information 0.24P July/2007 - Preliminary Public Version Update pin11 pin type Add company address Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. F75121 V0.24P July, 2007 Table of Contents 1. GENERAL DESCRIPTION ....................................................................................................................................................- 4 2. FEATURES ...............................................................................................................................................................................- 4 3. KEY SPECIFICATIONS .........................................................................................................................................................- 5 4. PIN CONFIGURATION..........................................................................................................................................................- 5 5. PIN DESCRIPTION.................................................................................................................................................................- 6 5.1 POWER PIN ......................................................................................................................................................................... - 6 5.2 VID CONTROL AND GPIO PINS .......................................................................................................................................... - 6 6. FUNCTIONAL DESCRIPTION .............................................................................................................................................- 7 6.1 GENERAL DESCRIPTION ..................................................................................................................................................... - 7 6.2 ACCESS INTERFACE ............................................................................................................................................................ - 8 6.3 THE SMBUS ACCESS TIMING ARE SHOWN AS FOLLOW: ....................................................................................................... - 8 6.4 VID FUNCTION .................................................................................................................................................................. - 9 6.5 GPIO FUNCTION ................................................................................................................................................................ - 9 6.5.1 General GPIO Function..................................................................................................................................................- 9 6.5.3 Reset Out (RSTOUT) Function......................................................................................................................................- 10 6..4 Watchdog Function..........................................................................................................................................................- 10 7. REGISTERS DESCRIPTION............................................................................................................................................... - 10 7.1 CONFIGURATION AND CONTROL REGISTER – INDEX 01H.................................................................................................. - 10 7.2 STATUS REGISTER – INDEX 02H ........................................................................................................................................ - 11 7.3 CONFIGURATION AND FUNCTION SELECT REGISTER – INDEX 03H..................................................................................... - 11 7.4 PIN MODE FUNCTION SELECT REGISTER – INDEX 04H....................................................................................................... - 12 7.5 PIN MODE FUNCTION SELECT REGISTER – INDEX 05H....................................................................................................... - 12 7.6 LED FREQ CONTROL REGISTER – INDEX 06H .................................................................................................................. - 13 7.7 LED FREQ CONTROL REGISTER – INDEX 07H .................................................................................................................. - 14 7.8 LED FREQ CONTROL REGISTER – INDEX 08H .................................................................................................................. - 15 7.9 LED FREQ CONTROL REGISTER – INDEX 09H .................................................................................................................. - 15 7.10 GPIO1X OUTPUT CONTROL REGISTER – INDEX 10H ...................................................................................................... - 16 7.11 GPIO1X OUTPUT DATA REGISTER – INDEX 11H ............................................................................................................. - 17 7.12 GPIO1X INPUT STATUS REGISTER – INDEX 12H ............................................................................................................. - 17 7.13 GPIO1X LEVEL/PULSE CONTROL REGISTER – INDEX 13H ............................................................................................. - 18 7.14 GPIO1X PULSE WIDTH CONTROL REGISTER – INDEX 14H ............................................................................................. - 18 7.15 GPIO1X PULL-UP RESISTOR CONTROL REGISTER – INDEX 15H ..................................................................................... - 18 - - 1 - July, 2007 V0.24P 7.16 GPIO1X INPUT DE-BOUNCE REGISTER – INDEX 16H ...................................................................................................... - 19 7.17 GPIO1X PULSE INVERSE REGISTER – INDEX 17H........................................................................................................... - 19 7.18 EDGE DETECTOR ENABLE REGISTER – INDEX 0X18....................................................................................................... - 20 7.19 EDGE DETECTOR STATUS REGISTER – INDEX 0X19 ........................................................................................................ - 21 7.20 IRQ OR SMI# ENABLE REGISTER – INDEX 0X1A ........................................................................................................... - 21 7.21 OUTPUT DRIVING ENABLE – INDEX 0X1B...................................................................................................................... - 22 7.22 OUTPUT DRIVING ENABLE – INDEX 0X1C...................................................................................................................... - 22 7.23 GPIO2X OUTPUT CONTROL REGISTER – INDEX 20H ...................................................................................................... - 23 7.24 GPIO2X OUTPUT DATA REGISTER – INDEX 21H ............................................................................................................. - 23 7.25 GPIO2X INPUT STATUS REGISTER – INDEX 22H ............................................................................................................. - 24 7.26 GPIO2X LEVEL/PULSE CONTROL REGISTER – INDEX 23H ............................................................................................. - 24 7.27 GPIO2X PULSE WIDTH CONTROL REGISTER – INDEX 24H ............................................................................................. - 25 7.28 GPIO2X PULL-UP RESISTOR CONTROL REGISTER – INDEX 25H ..................................................................................... - 25 7.29 GPIO2X INPUT DE-BOUNCE REGISTER – INDEX 26H ...................................................................................................... - 25 7.30 GPIO2X PULSE INVERSE REGISTER – INDEX 27H........................................................................................................... - 26 7.31 GP2X EDGE DETECTOR ENABLE REGISTER – INDEX 0X28............................................................................................. - 27 7.32 EDGE DETECTOR STATUS REGISTER – INDEX 0X29 ........................................................................................................ - 27 7.33 IRQ OR SMI# ENABLE REGISTER – INDEX 0X2A ........................................................................................................... - 28 7.34 OUTPUT DRIVING ENABLE – INDEX 0X2B...................................................................................................................... - 29 7.35 OUTPUT DRIVING ENABLE – INDEX 0X2C...................................................................................................................... - 29 7.36 VID ON THE FLY OFFSET REGISTER – INDEX 30H ............................................................................................................ - 30 7.37 VID OUTPUT DATA REGISTER – INDEX 31H ................................................................................................................... - 30 7.38 VIDKEY PROTECTION REGISTER – INDEX 32H.............................................................................................................. - 31 7.39 VID INPUT LATCH REGISTER – INDEX 33H ..................................................................................................................... - 31 7.40 RSTOUT CONTROL REGISTER – INDEX 34H .................................................................................................................. - 31 7.41 RSTOUT CONTROL REGISTER – INDEX 35H .................................................................................................................. - 31 7.42 WATCHDOG TIMER CONTROL REGISTER – INDEX 36H .................................................................................................... - 32 7.43 WATCHDOG TIMER RANGE REGISTER – INDEX 37H ........................................................................................................ - 32 7.44 GPIO3X OUTPUT CONTROL REGISTER – INDEX 40H ...................................................................................................... - 33 7.45 GPIO3X OUTPUT DATA REGISTER – INDEX 41H ............................................................................................................. - 33 7.46 GPIO3X INPUT STATUS REGISTER – INDEX 42H ............................................................................................................. - 33 7.47 GPIO3X LEVEL/PULSE CONTROL REGISTER – INDEX 43H ............................................................................................. - 34 7.48 GPIO3X PULSE WIDTH CONTROL REGISTER – INDEX 44H ............................................................................................. - 34 7.49 GPIO3X INPUT DE-BOUNCE REGISTER – INDEX 46H ...................................................................................................... - 34 7.50 GPIO3X PULSE INVERSE REGISTER – INDEX 47H........................................................................................................... - 35 7.51 GP3X EDGE DETECTOR ENABLE REGISTER – INDEX 0X48............................................................................................. - 35 7.52 EDGE DETECTOR STATUS REGISTER – INDEX 0X49 ........................................................................................................ - 36 - - 2 - July, 2007 V0.24P 7.53 IRQ OR SMI# ENABLE REGISTER – INDEX 0X4A ........................................................................................................... - 36 7.54 OUTPUT DRIVING ENABLE – INDEX 0X4C...................................................................................................................... - 37 7.55 CHIPID(1) REGISTER – INDEX 5AH ............................................................................................................................... - 37 7.56 CHIPID(2) REGISTER – INDEX 5BH ............................................................................................................................... - 37 7.57 VENDOR ID(1) REGISTER – INDEX 5DH....................................................................................................................... - 38 7.58 VENDOR ID(2) REGISTER – INDEX 5EH ....................................................................................................................... - 38 8. ELECTRON CHARACTERISTIC ...................................................................................................................................... - 38 8.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... - 38 8.2 DC CHARACTERISTICS ..................................................................................................................................................... - 38 8.3 AC CHARACTERISTICS ..................................................................................................................................................... - 41 9. ORDERING INFORMATION .............................................................................................................................................. - 42 10. PACKAGE DIMENSIONS................................................................................................................................................. - 42 - - 3 - July, 2007 V0.24P 1. General Description The F75121 is the dynamic voltage ID controller chip to provide the advanced CPU voltage programming when over clocking. F75121 supports the dynamic VID spec. for new generation Intel CPU and also compatible to VRM10.0/VRM9.X spec.. setting watch dog timer for OS idling protection. also supports pure 8 GPIO pins. Auto sensing CPU replacement and Besides of VID controlling function, F75121 Level or pulse modes can be programmed by registers. With 2 sets of watchdog timer, F75121 provides more flexible control for PC system, and there are four kinds of pulse width of the time out alert output pin can be selected. 2. Features Supporting new generation Intel dynamic Processor VID input /output Compatible VRM 9.X and VRM10.0 Auto detecting the CPU replacement Pure 8 GPIO pins Two sets of Watch dog timer to protect system from hanging when over-clocking SMbus interface Package in 28-SSOP (150mil) - 4 - July, 2007 V0.24P 3. Key Specifications Supply Voltage 3.0V to 3.6V Operating Supply Current 1mA typ. 4. Pin Configuration 1 28 SEL GPIO30 2 27 GPIO31 GPIO13/I2C_ADDR 3 26 GPIO32 VIDIN0 4 25 GPIO33 VIDIN1 5 24 VIDOUT0 VIDIN2 6 23 VIDOUT1 VIDIN3 7 22 VIDOUT2 VIDIN4 8 21 VIDOUT3 VIDIN5 9 20 VIDOUT4 GPIO10 10 19 VIDOUT5 GPIO11 11 18 VBAT GPIO12 12 17 SLOTOCC# SDATA 13 16 GND SCLK 14 15 RSTOUT# F75121R/RG VSB3V Figure 1. - 5 - July, 2007 V0.24P 5. Pin Description I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12ts - TTL level and schmitt trigger I/OOD12t - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability I/OD12 - TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability OUT12 - Output pin with 12 mA source-sink capability AOUT - Output pin(Analog) OD12 - Open-drain output pin with 12 mA sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin(Analog) P - Power 5.1 Power Pin Pin No. Pin Name Type Description 1 VSB3V P Standard Power Supply Voltage Input with 3.3V 18 VBAT P 3V Battery 16 GND P GND 5.2 VID Control and GPIO pins Pin No. Pin Name Type PWR Description 10,11,12 GPIO10,GPIO11, I/OOD16ts VSB3V General purpose I/O pins GPIO12 4,5,6,7,8,9 VIDIN[0:5] INts VSB3V CPU Voltage ID input 3 GPIO13 I/O16ts VSB3V General purpose I/O pin. - 6 - July, 2007 V0.24P I2C_ADDR INtsd100k The GPIO serial bus hardware power on setting pin. Default address is 0x9C (when I2C_ADDR=0). Another one is 0x6E (when I2C_ADDR=1). This pin internal pull-down 100k to Ground. If this pin is pull-up 10k to VSB3V, this pin will be trapped to 1. 13 SDATA I/OD12ts VSB3V SMbus data. 14 SCLK INt s VSB3V SMBus clock 15 RSTOUT# OD12 VSB3V System reset signal when the Reset-Out timer is time out. This pin will generate 100mS pulse when the Reset-Out timer is timeout. 17 SLOTOCC# INts VBAT Powered by VBAT. CPU detect pin. 24,23,22,21, VIDOUT[0:5] OD16 VSB3V CPU Voltage ID output. 28 SEL INtsd100k VSB3V Default pull up to 3VSB. 2,27,26,25 GPIO30,GPIO31, I/OD12ts VSB3V General purpose I/O pins. 20,19 GPIO32,GPIO33 6. Functional Description 6.1 General Description The F75121 provides VIDIN, VIDOUT function. It can latch the VIDIN from CPU side, and output VIDOUT to PWM. The VIDOUT value can be programmed by the interface GPIO Serial Bus serial interface. Dedicate GPIO functions. That includes two set watchdog timer. The watchdog timer timeout unit is set to second and range is 0 to 31 seconds. When the timeout has occurred, that will generate a status bit to indicate it and write one will be clear. All GPIO can be programmed to logic one or zero or high pulse or low pulse. - 7 - July, 2007 V0.24P Providing CPU on board detection (SLOTOCC#). The detection circuit is powered by battery. That is latch circuit is powered by VBAT. The de-bounce circuit should be added to avoid low power noise. The de-bounce circuit is generated by internal low frequency clock with 32K Hz to filter out the low-to-high or high-to-low glitch. 6.2 Access Interface The F75121 provides one serial access interface, Serial Bus, to read/write internal registers. The address of Serial Bus is configurable by using power-on trapping of standby power VBS3V. The pin 11 (GPIO11/I2C _ADDR) is multi-function pin. During the VSB 3V power-on, this pin serves as input detection of logic high or logic low. This pin is default pull-down resistor with 100K ohms mapping the Serial Bus address 0x9C (1001_1100). Another Serial Bus address 0x6E (0110_1110) is set when external pull-up resistor with 10K ohms is connected in this pin. 6.3 The SMBus access timing are shown as follow: (a) SMBus write to internal address register followed by the data byte 0 7 8 0 7 8 SCL SDA 0 Start By Master 1 0 1 1 0 1 R/W D7 D6 Ack by 121R Frame 1 Serial Bus Address Byte D5 D4 D3 D2 D1 D0 Ack by 101R Frame 2 Internal Index Register Byte 0 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by 784R Stop by Master Frame 3 Data Byte Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte - 8 - July, 2007 V0.24P (b) Serial bus write to internal address register only 0 7 8 0 7 8 SCL SDA 0 1 Start By Master 0 1 1 0 1 R/W D7 D6 Ack by 121R Frame 1 Serial Bus Address Byte D5 D4 D3 D2 D1 D0 Ack by 101R Frame 2 Internal Index Register Byte Stop by Master 0 Figure 2. Serial Bus Write to Internal Address Register Only (c) Serial bus read from a register with the internal address register prefer to desired location 0 7 8 0 7 8 SCL 0 SDA 1 Start By Master 0 1 1 0 1 R/W D7 Ack by 121R Frame 1 Serial Bus Address Byte D6 D5 D4 D3 D2 Frame 2 Internal Index Register Byte D1 D0 Ack by Master Stop by Master 0 Figure 3. Serial Bus Read from Internal Address Register 6.4 VID Function Please refer to control registers. 6.5 GPIO Function The GPIO functions in the F75121 include general GPIO with programming Input and output. The output function also can be programmed high level or low level or high pulse or low pulse. CPU Voltage ID (VID) function The F75121 provides a voltage adjustment in the CPU with VID control. In general, the VIDIN is connected to CPU VID<4:0>(VRM9.X) or VID<5:0>(VRM10.0) and VIDOUT is connected to PWM Vcore VID. In the first power-on, the VIDIN is bypassed to VIDOUT. 6.5.1 General GPIO Function Please refer to control registers. - 9 - July, 2007 V0.24P 6.5.3 Reset Out (RSTOUT) Function Please refer to control registers. 6..4 Watchdog Function Please refer to control register. 7. Registers Description 7.1 Configuration and Control Register – Index 01h Power-on default [7:0] =0000_1000b Bit Name R/W PWR Description 7 INIT R/W VSB3V Software reset for all registers including Test Mode registers. Users use only. 6 CPU_SEL R/W VSB3V CPU select, if set this bit to 1 will select AMD CPU, else if set to 0 is Intel CPU(default), this bit clear by SLOTOCC#, and protect write command by VID_KEY REG 0x30. 5 EN_RSTOUT R/W VSB3V Enable Reset Out. If set to 1, enable RSTOUT output. Default is disable. 4 EN_OTF R/W VSB3V If set this bit to 1 will enable VID on the fly mode, user can change new VID value by program the REG 0x30 VID_OFFSET, this bit will clear by SLOTOCC#, and protect write command by VID_KEY REG 0x30. 3 VID_EXTEND R/W VSB3V Set this bit to 1 to enable Intel VRM10 mode, then GPIO14 and GPIO15 will be implement to VID_IN[5] and VID_OUT[5], this bit default is enable, , this bit will clear by SLOTOCC#, and protect write command by VID_KEY REG 0x30. 2 Reserved R/W VSB3V 1 AUTO_POWR_ R/W VSB3V MODE Set this bit to 1 will enable auto power down mode, when all function are idle then 20ms the chip will auto power down, it will wakeup when GPIO state change or read write register 0 SOFT_POWR_ DOWN R/W VSB3V Set this bit to 1 will power down all of the analog block and stop internal clock, write 0 to clear this bit or when GPIO state change will auto clear this bit to 0. - 10 - July, 2007 V0.24P 7.2 Status Register – Index 02h Power-on default [7:0] =0000_000xb Bit Name R/W PWR Description 7-4 Reserved RO VSB3V 3 POWR_DOWN RO VSB3V If this bit is set to 1, it mean the chip is in power down mode 2 FUNC_SEL RO VSB3V VID and GPIO function select. This is dedicated pin. if input value is 1(external pull-down 10K), the function is selected to VID. Otherwise, the input value is 0, the function is selected to GPIO. 1 I2C_ADDR RO VSB3V GPIO serial bus address Select. Internal pull-down 100K ohms are address 0x9C. If external is pull-up 10K ohms, the address is 0x6E. This pin is trapped during the VSB3VOK. 0 STS_SLOTOCC R/W VBAT Indicate the SLOTOCC# pin value. This pin will be latched till write this bit to 1. Writing 0 is invalid. 7.3 Configuration and function select Register – Index 03h Power-on default [7:0] =0000_0000b Bit Name R/W PWR 7 Reserved RO VSB3V 6 IRQ_LEVEL R/W VSB3V Description Select IRQ Polarity (Level). Set to 1, IRQ is low active and SMI# is high active. Default, the IRQ is high active and SMI# is low active. 5 IRQ_MODE R/W VSB3V IRQ/SMI# mode select. 0 – Level mode (IRQ mode), 1 – Pulse Mode (SMI# mode). If pulse mode is selected, the active pulse is over 100us. 4-3 PIN12_MODE R/W VSB3V 00: GPIO12 01: LED12 IN this mode can use REG 0x06(bit5,4) to select LED frequency. 10: IRQ 11: RSTOUT1#: 2 PIN11_MODE R/W VSB3V 0: GPIO11 1: LED11 IN this mode can use REG 0x06(bit3,2) to select LED frequency. 1-0 PIN10_MODE R/W VSB3V 00: GPIO10 01: LED10 IN this mode can use REG 0x06(bit1,0) to select LED frequency. - 11 - July, 2007 V0.24P 10,11: WD_OUT 7.4 Pin mode function select Register – Index 04h Power-on default [7:0] =0000_0000b Bit 7 Name PIN20_MODE R/W PWR R/W VSB3V Description 0: GPIO27 1: LED27 IN this mode can use REG 0x09(bit7, 6) to select LED frequency. 6 PIN19_MODE R/W VSB3V 0: GPIO15 1: LED15 IN this mode can use REG 0x07(bit3, 2) to select LED frequency. 5 PIN9_MODE R/W VSB3V 0: GPIO14 1: LED14 IN this mode can use REG 0x07(bit1, 0) to select LED frequency. 4 PIN8_MODE R/W VSB3V 0: GPIO22 1: LED22 IN this mode can use REG 0x08(bit5, 4) to select LED frequency. 3 PIN7_MODE R/W VSB3V 0: GPIO21 1: LED21 IN this mode can use REG 0x08(bit3, 2) to select LED frequency. 2 PIN6_MODE R/W VSB3V 0: GPIO20 1: LED20 IN this mode can use REG 0x08(bit1, 0) to select LED frequency. 1 PIN5_MODE R/W VSB3V 0: GPIO17 1: LED17 IN this mode can use REG 0x07(bit7, 6) to select LED frequency. 0 PIN4_MODE R/W VSB3V 0: GPIO16 1: LED16 IN this mode can use REG 0x07(bit5, 4) to select LED frequency. 7.5 Pin mode function select Register – Index 05h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description - 12 - July, 2007 V0.24P 7-4 Reserved RO 3 PIN24_MODE R/W VSB3V 0: GPIO23 1: LED23 IN this mode can use REG 0x08(bit7, 6) to select LED frequency. 2 PIN23_MODE R/W VSB3V 0: GPIO24 1: LED24 IN this mode can use REG 0x09(bit1, 0) to select LED frequency. 1 PIN22_MODE R/W VSB3V 0: GPIO25 1: LED25 IN this mode can use REG 0x09(bit3, 2) to select LED frequency. 0 PIN21_MODE R/W VSB3V 0: GPIO26 1: LED26 IN this mode can use REG 0x09(bit5, 4) to select LED frequency. 7.6 LED Freq Control Register – Index 06h Power-on default [7:0] =0000_0000b Bit Name R/W PWR 7-6 Reserved R/W VSB3V 5-4 LED12_FREQ R/W VSB3V 3-2 1-0 LED11_FREQ LED10_FREQ R/W R/W VSB3V VSB3V Description LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) - 13 - July, 2007 V0.24P 10 1 Hz (period is 1 second) 11 Low. 7.7 LED Freq Control Register – Index 07h Power-on default [7:0] =0000_0000b Bit 7-6 5-4 3-2 1-0 Name LED17_FREQ LED16_FREQ LED15_FREQ LED14_FREQ R/W PWR R/W VSB3V R/W R/W R/W VSB3V VSB3V VSB3V Description LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. - 14 - July, 2007 V0.24P 7.8 LED Freq Control Register – Index 08h Power-on default [7:0] =0000_0000b Bit 7-6 5-4 3-2 1-0 Name LED23_FREQ LED22_FREQ LED21_FREQ LED20_FREQ R/W PWR R/W VSB3V R/W R/W R/W VSB3V VSB3V VSB3V Description LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. 7.9 LED Freq Control Register – Index 09h Power-on default [7:0] =0000_0000b Bit 7-6 Name LED27_FREQ R/W PWR R/W VSB3V Description LED output frequency. Bit Description - 15 - July, 2007 V0.24P 5-4 3-2 1-0 LED26_FREQ LED25_FREQ LED24_FREQ R/W R/W R/W VSB3V VSB3V VSB3V 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. LED output frequency. Bit Description 00 Tri-state (default). 01 0.5Hz (period is 2 seconds, duty cycle is 50%) 10 1 Hz (period is 1 second) 11 Low. 7.10 GPIO1x Output Control Register – Index 10h Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR GP17_OCTRL R/W VSB3V Description GPIO 17 output control. Set to 1 for output function. Set to 0 for input function(default). 6 GP16_OCTRL R/W VSB3V GPIO 16 output control. Set to 1 for output function. Set to 0 for input function(default). 5 GP15_OCTRL R/W VSB3V GPIO 15 output control. Set to 1 for output function. Set to 0 for input function(default). 4 GP14_OCTRL R/W VSB3V GPIO 14 output control. Set to 1 for output function. Set to 0 for input - 16 - July, 2007 V0.24P function(default). 3 GP13_OCTRL R/W VSB3V GPIO 13 output control. Set to 1 for output function. Set to 0 for input function(default). 2 GP12_OCTRL R/W VSB3V GPIO 12 output control. If this pin serves as IRQ/SMI#, this bit has no effect. Set to 1 for output function. Set to 0 for input function(default). 1 GP11_OCTRL R/W VSB3V GPIO 11 output control. Set to 1 for output function. Set to 0 for input function(default). 0 GP10_OCTRL R/W VSB3V GPIO 10 output control. Set to 1 for output function. Set to 0 for input function(default). 7.11 GPIO1x Output Data Register – Index 11h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP17_ODATA R/W VSB3V GPIO 17 output data. 6 GP16_ODATA R/W VSB3V GPIO 16 output data. 5 GP15_ODATA R/W VSB3V GPIO 15 output data. 4 GP14_ODATA R/W VSB3V GPIO 14 output data. 3 GP13_ODATA R/W VSB3V GPIO 13 output data. 2 GP12_ODATA R/W VSB3V GPIO 12 output data. If this pin serves as IRQ/SMI#, this bit has no effect. 1 GP11_ODATA R/W VSB3V GPIO 11 output data. 0 GP10_ODATA R/W VSB3V GPIO 10 output data. 7.12 GPIO1x Input Status Register – Index 12h Power-on default [7:0] =xxxx_xxxxb Bit Name R/W PWR Description 7 GP17_PSTS RO VSB3V Read the GPIO17 data on the pin. 6 GP16_PSTS RO VSB3V Read the GPIO16 data on the pin. 5 GP15_PSTS RO VSB3V Read the GPIO15 data on the pin. 4 GP14_PSTS RO VSB3V Read the GPIO14 data on the pin. 3 GP13_PSTS RO VSB3V Read the GPIO13 data on the pin. 2 GP12_PSTS RO VSB3V Read the GPIO12 data on the pin. 1 GP11_PSTS RO VSB3V Read the GPIO11 data on the pin. - 17 - July, 2007 V0.24P 0 GP10_PSTS RO VSB3V Read the GPIO10 data on the pin. 7.13 GPIO1x Level/Pulse Control Register – Index 13h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP17_OMODE R/W VSB3V GPIO 17 output mode. 0 – level, 1 – pulse. 6 GP16_OMODE R/W VSB3V GPIO 16 output mode. 0 – level, 1 – pulse. 5 GP15_OMODE R/W VSB3V GPIO 15 output mode. 0 – level, 1 – pulse. 4 GP14_OMODE R/W VSB3V GPIO 14 output mode. 0 – level, 1 – pulse. 3 GP13_OMODE R/W VSB3V GPIO 13 output mode. 0 – level, 1 – pulse. 2 GP12_OMODE R/W VSB3V GPIO 12 output mode. 0 – level, 1 – pulse. If this serves as IRQ/SMI# mode, it will have same function. 1 GP11_OMODE R/W VSB3V GPIO 11 output mode. 0 – level, 1 – pulse. 0 GP10_OMODE R/W VSB3V GPIO 10 output mode. 0 – level, 1 – pulse. 7.14 GPIO1x Pulse Width Control Register – Index 14h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7:2 Reserved R/W VSB3V Reserved. Read return 0. 1:0 GP1_PSWDTH[1:0 R/W VSB3V GPIO1x pulse width. If set the GPIO1x to pulse mode, the pulse width ] can be defined as follows. 00b – 500us (Default) 01b – 1ms 10b – 20ms 11b – 100ms 7.15 GPIO1x Pull-up Resistor Control Register – Index 15h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description - 18 - July, 2007 V0.24P 7 GP17_RESON R/W VSB3V Set to 1, turn on the GPIO17 internal pull-up resistor. 6 GP16_RESON R/W VSB3V Set to 1, turn on the GPIO16 internal pull-up resistor. 5 GP15_RESON R/W VSB3V Set to 1, turn on the GPIO15 internal pull-up resistor. 4 GP14_RESON R/W VSB3V Set to 1, turn on the GPIO14 internal pull-up resistor. 3 Reserved R/W VSB3V 2 GP12_RESON R/W VSB3V Set to 1, turn on the GPIO12 internal pull-up resistor. If this pin serves as IRQ/SMI#, this bit also control IRQ/SMI# pull-up switch. 1 GP11_RESON R/W VSB3V Set to 1, turn on the GPIO11 internal pull-up resistor. 0 GP10_RESON R/W VSB3V Set to 1, turn on the GPIO10 internal pull-up resistor. 7.16 GPIO1x Input De-bounce Register – Index 16h Power-on default [7:0] =0000_0000b Bit 7 Name GP17_ENDB R/W PWR R/W VSB3V Description Enable GPIO17 input de-bounce with 7u or 25ms second that selected by 0x1C bit7. 6 GP16_ENDB R/W VSB3V Enable GPIO16 input de-bounce with 7u or 25ms second that selected by 0x1C bit6. 5 GP15_ENDB R/W VSB3V Enable GPIO15 input de-bounce with 7u or 25ms second that selected by 0x1C bit5. 4 GP14_ENDB R/W VSB3V Enable GPIO14 input de-bounce with 7u or 25ms second that selected by 0x1C bit4. 3 GP13_ENDB R/W VSB3V Enable GPIO13 input de-bounce with 7u or 25ms second that selected by 0x1C bit3. 2 GP12_ENDB R/W VSB3V Enable GPIO12 input de-bounce with 7u or 25ms second that selected by 0x1C bit2. 1 GP11_ENDB R/W VSB3V Enable GPIO11 input de-bounce with 7u or 25ms second that selected by 0x1C bit1. 0 GP10_ENDB R/W VSB3V Enable GPIO10 input de-bounce with 7u or 25ms second that selected by 0x1C bit0. 7.17 GPIO1x Pulse Inverse Register – Index 17h Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR Description GP17_PULSINV R/W VSB3V GPIO 17 Pulse inversed. If the pulse inverse is selected, the output pulse is - 19 - July, 2007 V0.24P high pulse. Default low pulse. The pulse width is defined in CR14. 6 GP16_PULSINV R/W VSB3V GPIO 16 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 5 GP15_PULSINV R/W VSB3V GPIO15 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 4 GP14_PULSINV R/W VSB3V GPIO14 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 3 GP13_PULSINV R/W VSB3V GPIO13 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 2 GP12_PULSINV R/W VSB3V GPIO12 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. If this pin services as IRQ/SMI#, this bit has no effect. 1 GP11_PULSINV R/W VSB3V GPIO 11 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 0 GP10_PULSINV R/W VSB3V GPIO10 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR14. 7.18 Edge Detector Enable Register – Index 0x18 Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR Description EN_GP17EDGE R/W VSB3V Enable GPIO17 Edge Detector. If set to 1, enable GPIO17 edge detection. Default is disable. 6 EN_GP16EDGE R/W VSB3V Enable GPIO16 Edge Detector. If set to 1, enable GPIO16 edge detection. Default is disable. 5 EN_GP15EDGE R/W VSB3V Enable GPIO15 Edge Detector. If set to 1, enable GPIO15 edge detection. Default is disable. 4 EN_GP14EDGE R/W VSB3V Enable GPIO14 Edge Detector. If set to 1, enable GPIO14 edge detection. Default is disable. 3 EN_GP13EDGE R/W VSB3V Enable GPIO13 Edge Detector. If set to 1, enable GPIO13 edge detection. Default is disable. 2 EN_GP12EDGE R/W VSB3V Enable GPIO12 Edge Detector. If set to 1, enable GPIO12 edge detection. Default is disable. If this bit serves as IRQ/SMI#, this bit has no effect. 1 EN_GP11EDGE R/W VSB3V Enable GPIO11 Edge Detector. If set to 1, enable GPIO11 edge detection. - 20 - July, 2007 V0.24P Default is disable. 0 EN_GP10EDGE R/W VSB3V Enable GPIO10 Edge Detector. If set to 1, enable GPIO10 edge detection. Default is disable. 7.19 Edge Detector Status Register – Index 0x19 Power-on default [7:0] =0000_0000b Bit 7 Name STS_GP17ED R/W RW PWR Description VSB3V Indicate GPIO17 Edge Status. If set to 1, the edge of GPIO17 has occurred. GE 6 Writing 1 will clear this bit to 0. Writing 0 is invalid. STS_GP16ED RW VSB3V GE 5 Writing 1 will clear this bit to 0. Writing 0 is invalid. STS_GP15ED RW VSB3V GE 4 STS_GP14ED RW VSB3V Indicate GPIO14 Edge Status. If set to 1, the edge of GPIO14 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. STS_GP13ED RW VSB3V GE 2 Indicate GPIO15 Edge Status. If set to 1, the edge of GPIO15 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. GE 3 Indicate GPIO16 Edge Status. If set to 1, the edge of GPIO16 has occurred. Indicate GPIO13 Edge Status. If set to 1, the edge of GPIO13 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. STS_GP12ED RW VSB3V GE Indicate GPIO12 Edge Status. If set to 1, the edge of GPIO12 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. If this bit serves as IRQ/SMI#, this bit has no effect. 1 STS_GP11ED RW VSB3V GE 0 Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO11 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. STS_GP10ED RW VSB3V GE Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO10 has occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. 7.20 IRQ or SMI# Enable Register – Index 0x1A Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 EN_GP17IRQ R/W VSB3V Enable GPIO17 IRQ or SMI# Generation. If this bit set to 1, enable GPIO17 to generate IRQ or SMI#. 6 EN_GP16IRQ R/W VSB3V Enable GPIO16 IRQ or SMI# Generation. If this bit set to 1, enable GPIO16 to generate IRQ or SMI#. 5 EN_GP15IRQ R/W VSB3V Enable GPIO15 IRQ or SMI# Generation. If this bit set to 1, enable GPIO15 to generate IRQ or SMI#. 4 EN_GP14IRQ R/W VSB3V Enable GPIO14 IRQ or SMI# Generation. If this bit set to 1, enable GPIO14 to generate IRQ or SMI#. - 21 - July, 2007 V0.24P 3 EN_GP13IRQ R/W VSB3V Enable GPIO13 IRQ or SMI# Generation. If this bit set to 1, enable GPIO13 to generate IRQ or SMI#. 2 EN_GP12IRQ R/W VSB3V Enable GPIO12 IRQ or SMI# Generation. If this bit set to 1, enable GPIO12 to generate IRQ or SMI#. 1 EN_GP11IRQ R/W VSB3V Enable GPIO11 IRQ or SMI# Generation. If this bit set to 1, enable GPIO11 to generate IRQ or SMI#. 0 EN_GP10IRQ R/W VSB3V Enable GPIO10 IRQ or SMI# Generation. If this bit set to 1, enable GPIO10 to generate IRQ or SMI#. 7.21 Output Driving Enable – Index 0x1B Power-on default [7:0] =0000_1000b Bit Name R/W PWR Description 7 EN_GP17_OBUF R/W VSB3V Enable GPIO17 drive high buffer. If this bit is set to 0, the pin GPIO17 will be I/OD pin, if set to 1 the pin GPIO17 is I/O pin. 6 EN_GP16_OBUF R/W VSB3V Enable GPIO16 drive high buffer. If this bit is set to 0, the pin GPIO16 will be I/OD pin, if set to 1 the pin GPIO16 is I/O pin. 5 EN_GP15_OBUF R/W VSB3V Enable GPIO15 drive high buffer. If this bit is set to 0, the pin GPIO15 will be I/OD pin, if set to 1 the pin GPIO15 is I/O pin. 4 EN_GP14_OBUF R/W VSB3V Enable GPIO14 drive high buffer. If this bit is set to 0, the pin GPIO14 will be I/OD pin, if set to 1 the pin GPIO14 is I/O pin. 3 EN_GP13_OBUF R/W VSB3V Enable GPIO13 drive high buffer. If this bit is set to 0, the pin GPIO13 will be I/OD pin, if set to 1 the pin GPIO13 is I/O pin(default). 2 EN_GP12_OBUF R/W VSB3V Enable GPIO12 drive high buffer. If this bit is set to 0, the pin GPIO12 will be I/OD pin, if set to 1 the pin GPIO12 is I/O pin. 1 EN_GP11_OBUF R/W VSB3V Enable GPIO11 drive high buffer. If this bit is set to 0, the pin GPIO11 will be I/OD pin, if set to 1 the pin GPIO11 is I/O pin. 0 EN_GP10_OBUF R/W VSB3V Enable GPIO10 drive high buffer. If this bit is set to 0, the pin GPIO10 will be I/OD pin, if set to 1 the pin GPIO10 is I/O pin. 7.22 Output Driving Enable – Index 0x1C Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 DB_TIME17_SEL R/W VSB3V Select GPIO17 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 6 DB_TIME16_SEL R/W VSB3V Select GPIO16 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). - 22 - July, 2007 V0.24P 5 DB_TIME15_SEL R/W VSB3V Select GPIO15 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 4 DB_TIME14_SEL R/W VSB3V Select GPIO14 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 3 DB_TIME13_SEL R/W VSB3V Select GPIO13 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 2 DB_TIME12_SEL R/W VSB3V Select GPIO12 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 1 DB_TIME11_SEL R/W VSB3V Select GPIO11 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 0 DB_TIME10_SEL R/W VSB3V Select GPIO10 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 7.23 GPIO2x Output Control Register – Index 20h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP27_OCTRL R/W VSB3V GPIO 27 output control 6 GP26_OCTRL R/W VSB3V GPIO 26 output control 5 GP25_OCTRL R/W VSB3V GPIO 25 output control 4 GP24_OCTRL R/W VSB3V GPIO 24 output control 3 GP23_OCTRL R/W VSB3V GPIO 23 output control 2 GP22_OCTRL R/W VSB3V GPIO 22 output control 1 GP21_OCTRL R/W VSB3V GPIO 21 output control 0 GP20_OCTRL R/W VSB3V GPIO 20 output control 7.24 GPIO2x Output Data Register – Index 21h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP27_ODATA R/W VSB3V GPIO 27 output data. 6 GP26_ODATA R/W VSB3V GPIO 26 output data. 5 GP25_ODATA R/W VSB3V GPIO 25 output data. 4 GP24_ODATA R/W VSB3V GPIO 24 output data. 3 GP23_ODATA R/W VSB3V GPIO 23 output data. - 23 - July, 2007 V0.24P 2 GP22_ODATA R/W VSB3V GPIO 22 output data. 1 GP21_ODATA R/W VSB3V GPIO 21 output data. 0 GP20_ODATA R/W VSB3V GPIO 20 output data. 7.25 GPIO2x Input Status Register – Index 22h Power-on default [7:0] =xxxx_xxxxb Bit Name R/W PWR Description 7 GP27_PSTS RO VSB3V Read the GPIO27 data on the pin. 6 GP26_PSTS RO VSB3V Read the GPIO26 data on the pin. 5 GP25_PSTS RO VSB3V Read the GPIO25 data on the pin. 4 GP24_PSTS RO VSB3V Read the GPIO24 data on the pin. 3 GP23_PSTS RO VSB3V Read the GPIO23 data on the pin. 2 GP22_PSTS RO VSB3V Read the GPIO22 data on the pin. 1 GP21_PSTS RO VSB3V Read the GPIO21 data on the pin. 0 GP20_PSTS RO VSB3V Read the GPIO20 data on the pin. 7.26 GPIO2x Level/Pulse Control Register – Index 23h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP27_OMODE R/W VSB3V GPIO 27 output mode. 0 – level, 1 – pulse. 6 GP26_OMODE R/W VSB3V GPIO 26 output mode. 0 – level, 1 – pulse. 5 GP25_OMODE R/W VSB3V GPIO 25 output mode. 0 – level, 1 – pulse. 4 GP24_OMODE R/W VSB3V GPIO 24 output mode. 0 – level, 1 – pulse. 3 GP23_OMODE R/W VSB3V GPIO 23 output mode. 0 – level, 1 – pulse. 2 GP22_OMODE R/W VSB3V GPIO 22 output mode. 0 – level, 1 – pulse. 1 GP21_OMODE R/W VSB3V GPIO 21 output mode. 0 – level, 1 – pulse. 0 GP27_OMODE R/W VSB3V GPIO 20 output mode. 0 – level, 1 – pulse. - 24 - July, 2007 V0.24P 7.27 GPIO2x Pulse Width Control Register – Index 24h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7:2 Reserved R/W VSB3V Reserved. Read return 0. 1:0 GP2_PLSWD[1:0 R/W VSB3V GPIO2x pulse width. If set the GPIO2x to pulse mode, the pulse width ] can be defined as follows. 00b – 500us (Default) 01b – 1ms 10b – 20ms 11b – 100ms 7.28 GPIO2x Pull-up Resistor Control Register – Index 25h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 GP27_RESON R/W VSB3V Turn on the GPIO27 internal pull-up resistor. 6 GP26_RESON R/W VSB3V Turn on the GPIO26 internal pull-up resistor. 5 GP25_RESON R/W VSB3V Turn on the GPIO25 internal pull-up resistor. 4 GP24_RESON R/W VSB3V Turn on the GPIO24 internal pull-up resistor. 3 GP23_RESON R/W VSB3V Turn on the GPIO23 internal pull-up resistor. 2 GP22_RESON R/W VSB3V Turn on the GPIO22 internal pull-up resistor. 1 GP21_RESON R/W VSB3V Turn on the GPIO21 internal pull-up resistor. 0 GP20_RESON R/W VSB3V Turn on the GPIO20 internal pull-up resistor. 7.29 GPIO2x Input De-bounce Register – Index 26h Power-on default [7:0] =0000_0000b Bit 7 Name GP27_ENDB R/W PWR Description R/W VSB3V Enable GPIO27 input de-bounce with 7u or 25ms second that selected by 0x2C bit7. 6 GP26_ENDB R/W VSB3V Enable GPIO26 input de-bounce with 7u or 25ms second that selected by - 25 - July, 2007 V0.24P 0x2C bit6. 5 GP25_ENDB R/W VSB3V Enable GPIO25 input de-bounce with 7u or 25ms second that selected by 0x2C bit5. 4 GP24_ENDB R/W VSB3V Enable GPIO24 input de-bounce with 7u or 25ms second that selected by 0x2C bit4. 3 GP23_ENDB R/W VSB3V Enable GPIO23 input de-bounce with 7u or 25ms second that selected by 0x2C bit3. 2 GP22_ENDB R/W VSB3V Enable GPIO22 input de-bounce with 7u or 25ms second that selected by 0x2C bit2. 1 GP21_ENDB R/W VSB3V Enable GPIO21 input de-bounce with 7u or 25ms second that selected by 0x2C bit1. 0 GP20_ENDB R/W VSB3V Enable GPIO20 input de-bounce with 7u or 25ms second that selected by 0x2C bit0. 7.30 GPIO2x Pulse Inverse Register – Index 27h Power-on default [7:0] =0000_0000b Bit 7 Name GP27_PULSINV R/W R/W PWR Description VSB3V GPIO 27 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 6 GP26_PULSINV R/W VSB3V GPIO 26 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 5 GP25_PULSINV R/W VSB3V GPIO25 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 4 GP24_PULSINV R/W VSB3V GPIO24 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 3 GP23_PULSINV R/W VSB3V GPIO23 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 2 GP22_PULSINV R/W VSB3V GPIO22 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 1 GP21_PULSINV R/W VSB3V GPIO 21 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. 0 GP20_PULSINV R/W VSB3V GPIO20 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR24. - 26 - July, 2007 V0.24P 7.31 GP2x Edge Detector Enable Register – Index 0x28 Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR Description EN_GP27EDGE R/W VSB3V Enable GPIO27 Edge Detector. If set to 1, enable GPIO27 edge detection. Default is disabled. 6 EN_GP26EDGE R/W VSB3V Enable GPIO26 Edge Detector. If set to 1, enable GPIO26 edge detection. Default is disabled. 5 EN_GP25EDGE R/W VSB3V Enable GPIO25 Edge Detector. If set to 1, enable GPIO25 edge detection. Default is disabled. 4 EN_GP24EDGE R/W VSB3V Enable GPIO24 Edge Detector. If set to 1, enable GPIO24 edge detection. Default is disabled. 3 EN_GP23EDGE R/W VSB3V Enable GPIO23 Edge Detector. If set to 1, enable GPIO23 edge detection. Default is disabled. 2 EN_GP22EDGE R/W VSB3V Enable GPIO22 Edge Detector. If set to 1, enable GPIO22 edge detection. Default is disabled. 1 EN_GP21EDGE R/W VSB3V Enable GPIO21 Edge Detector. If set to 1, enable GPIO21 edge detection. Default is disabled. 0 EN_GP20EDGE R/W VSB3V Enable GPIO20 Edge Detector. If set to 1, enable GPIO20 edge detection. Default is disabled. 7.32 Edge Detector Status Register – Index 0x29 Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR STS_GP27EDGE R/W VSB3V Description Indicate GPIO27 Edge Status. If set to 1, the edge of GPIO27 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 6 STS_GP26EDGE R/W VSB3V Indicate GPIO26 Edge Status. If set to 1, the edge of GPIO26 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 5 STS_GP25EDGE R/W VSB3V Indicate GPIO25 Edge Status. If set to 1, the edge of GPIO25 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 4 STS_GP24EDGE R/W VSB3V Indicate GPIO24 Edge Status. If set to 1, the edge of GPIO24 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 3 STS_GP23EDGE R/W VSB3V Indicate GPIO23 Edge Status. If set to 1, the edge of GPIO23 has occurred. Write 1 to clear this bit. Writing 0 is invalid. - 27 - July, 2007 V0.24P 2 STS_GP22EDGE R/W VSB3V Indicate GPIO22 Edge Status. If set to 1, the edge of GPIO22 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 1 STS_GP21EDGE R/W VSB3V Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO21 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 0 STS_GP20EDGE R/W VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO20 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 7.33 IRQ or SMI# Enable Register – Index 0x2A Power-on default [7:0] =0000_0000b Bit 7 Name EN_GP27IRQ R/W PWR Description R/W VSB3V Enable GPIO27 IRQ or SMI# Generation. If this bit set to 1, enable GPIO27 to generate IRQ or SMI#. 6 EN_GP26IRQ R/W VSB3V Enable GPIO26 IRQ or SMI# Generation. If this bit set to 1, enable GPIO26 to generate IRQ or SMI#. 5 EN_GP25IRQ R/W VSB3V Enable GPIO25 IRQ or SMI# Generation. If this bit set to 1, enable GPIO25 to generate IRQ or SMI#. 4 EN_GP24IRQ R/W VSB3V Enable GPIO24 IRQ or SMI# Generation. If this bit set to 1, enable GPIO24 to generate IRQ or SMI#. 3 EN_GP23IRQ R/W VSB3V Enable GPIO23 IRQ or SMI# Generation. If this bit set to 1, enable GPIO23 to generate IRQ or SMI#. 2 EN_GP22IRQ R/W VSB3V Enable GPIO22 IRQ or SMI# Generation. If this bit set to 1, enable GPIO22 to generate IRQ or SMI#. 1 EN_GP21IRQ R/W VSB3V Enable GPIO21 IRQ or SMI# Generation. If this bit set to 1, enable GPIO21 to generate IRQ or SMI#. 0 EN_GP20IRQ R/W VSB3V Enable GPIO20 IRQ or SMI# Generation. If this bit set to 1, enable GPIO20 to generate IRQ or SMI#. - 28 - July, 2007 V0.24P 7.34 Output Driving Enable – Index 0x2B Power-on default [7:0] =0000_0000b Bit 7 Name R/W PWR EN_GP27_OBUF R/W VSB3V Description Enable GPIO27 drive high buffer. If this bit is set to 0, the pin GPIO27 will be I/OD pin, if set to 1 the pin GPIO17 is I/O pin. 6 EN_GP26_OBUF R/W VSB3V Enable GPIO26 drive high buffer. If this bit is set to 0, the pin GPIO26 will be I/OD pin, if set to 1 the pin GPIO26 is I/O pin. 5 EN_GP26_OBUF R/W VSB3V Enable GPIO26 drive high buffer. If this bit is set to 0, the pin GPIO26 will be I/OD pin, if set to 1 the pin GPIO26 is I/O pin. 4 EN_GP24_OBUF R/W VSB3V Enable GPIO24 drive high buffer. If this bit is set to 0, the pin GPIO24 will be I/OD pin, if set to 1 the pin GPIO24 is I/O pin. 3 EN_GP23_OBUF R/W VSB3V Enable GPIO23 drive high buffer. If this bit is set to 0, the pin GPIO23 will be I/OD pin, if set to 1 the pin GPIO23 is I/O pin. 2 EN_GP22_OBUF R/W VSB3V Enable GPIO22 drive high buffer. If this bit is set to 0, the pin GPIO22 will be I/OD pin, if set to 1 the pin GPIO22 is I/O pin. 1 EN_GP21_OBUF R/W VSB3V Enable GPIO21 drive high buffer. If this bit is set to 0, the pin GPIO21 will be I/OD pin, if set to 1 the pin GPIO21 is I/O pin. 0 EN_GP20_OBUF R/W VSB3V Enable GPIO20 drive high buffer. If this bit is set to 0, the pin GPIO20 will be I/OD pin, if set to 1 the pin GPIO20 is I/O pin. 7.35 Output Driving Enable – Index 0x2C Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 DB_TIME27_SEL R/W VSB3V Select GPIO27 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 6 DB_TIME26_SEL R/W VSB3V Select GPIO26 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 5 DB_TIME25_SEL R/W VSB3V Select GPIO25 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 4 DB_TIME24_SEL R/W VSB3V Select GPIO24 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 3 DB_TIME23_SEL R/W VSB3V Select GPIO23 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 2 DB_TIME22_SEL R/W VSB3V Select GPIO22 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). - 29 - July, 2007 V0.24P 1 DB_TIME21_SEL R/W VSB3V Select GPIO21 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 0 DB_TIME20_SEL R/W VSB3V Select GPIO20 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 7.36 VID on the fly offset Register – Index 30h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-5 Reserved RO VSB3V Reserved. Read return 0 4-0 VID_OFFSET R/W VSB3V VID offset register. The offset value is representative in 2’s complement. The real VID value will be added by this offset and then will be put into VID_OUT(when EN_OTF is set). The offset ranges from -16 to +15. 0Fh : +15. 01h : +1. 00h : +0. 1Fh : -1. 1Eh : -2. 10h : -16. 7.37 VID Output Data Register – Index 31h Power-on default [7:0] =0000_0000b Bit 7 Name EN_VIDOUT R/W PWR R/W VSB3V Description Enable VIDOUT. If set to one and VID output key is asserted referred as VIDKEY, the VIDOUT_DATA will output to these pins of VIDOUT. This bit is supplied by VSB3V and reset by the VSB3V power good or RSTOUT is asserted or SLOTOCC# is asserted. 6 VIDKEY_OK RO VSB3V When the sequential key is programmed to register 22H. this bit will set to 1. if program exit sequential key to register 22H, this bit read back will be 0 5:0 VIDOUT_DATA R/W VSB3V VIDOUT Data. These bits is mapping to VIDOUT[4:0] if EN_VIDOUT is enable. These bits power is supplied by VSB3V for keeping data when VDD3V power is lose. - 30 - July, 2007 V0.24P 7.38 VIDKEY Protection Register – Index 32h Power-on default [7:0] =0000_0000b Bit 7-0 Name VIDKEY R/W PWR R/W VSB3V Description VID Key for protection the VIDOUT. If would like to program VID Output Data Register, the sequential key should be programmed first. The VID Output Register is disable in the default (VSB3V power on). The sequential keys are defined as 0x32, 0x5d, 0x42, 0xac. And the exit key is 0x35. 7.39 VID Input Latch Register – Index 33h Power-on default [7:0] =000x_xxxxb Bit Name R/W PWR Description 7-6 Reserved RO -- Reserved, read return 0. 5-0 LVIDIN RO VSB3V VIDIN data. 7.40 RSTOUT Control Register – Index 34h Power-on default [7:0] =0000_0000b Bit Name R/W 7-3 Reserved RO 2 SEL_RST_2S R/W PWR VSB3V Description When set this bit to 1, the RSTOUT low pulse width is 2 Sec, if set to 0 the low pulse width is 100ms. 1 RSTOUT_OINV R/W VSB3V RSTOUT# output level inverting. When write 1, the output pin will be inverted. Default is low active when time is out. 0 STS_RSTOUT R/W VSB3V Indicate RSTOUT is occurred. Write 1 to clear this bit. Writing 0 is invalid. 7.41 RSTOUT Control Register – Index 35h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description - 31 - July, 2007 V0.24P 7 RST_ENABLE R/W VSB3V Enable RESET Output Timer. If set to 1, the RSTOUT timer will be started. When RSTOUT# is asserted, low pulse is occurred, the VID will re-latched and disable EN_VIDOUT. The status of Reset Out is stored in CR02.b1. 6-0 WD1_PTIME R/W VSB3V RSTOUT Pre-counter time in second. 000_0000b – 0 second (Default) 000_0001b – 1 second 000_0010b – 2 seconds : 111_1111b – 127 seconds 7.42 Watchdog Timer Control Register – Index 36h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7 Reserved RO VSB3V Reserved. Read will return 0. 6 STS_WD_TMO R/W VSB3V Watchdog is timeout. When the watchdog is timeout, this bit will be set to UT one. If set to 1, write 1 will clear this bit. Write 0, no effect. 5 WD_ENABLE R/W VSB3V Enable watchdog timer. 4 WD_PULSE R/W VSB3V Watchdog output level or pulse. If set 0 (default), the pin of watchdog is level output. If write 1, the pin will output with a pulse. 3 WD_UNIT R/W VSB3V Watchdog unit select. Default 0 is select second. Write 1 to select minute. 2 WD_HACTIVE R/W VSB3V Program WD output level. If set to 1 and watchdog asserted, the pin will be high. If set to 0 and watchdog asserted, this pin will drive low(default). 1-0 WD_PSWIDTH R/W VSB3V Watchdog pulse width selection. If the pin output is selected to pulse mode. The pulse width can be choice. 00b – 1m second. 01b – 20m second. 10b – 100m second 11b – 4 second The is flexible reset out with watchdog 7.43 Watchdog Timer Range Register – Index 37h Power-on default [7:0] =0000_0000b - 32 - July, 2007 V0.24P Bit 7-0 Name WD_TIME R/W PWR Description R/W VSB3V Watchdog timing range from 0 ~ 255. The unit is either second or minute programmed by the watchdog timer control register bit3. 7.44 GPIO3x Output Control Register – Index 40h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_OCTRL R/W VSB3V GPIO 33 output control 2 GP32_OCTRL R/W VSB3V GPIO 32 output control 1 GP31_OCTRL R/W VSB3V GPIO 31 output control 0 GP30_OCTRL R/W VSB3V GPIO 30 output control 7.45 GPIO3x Output Data Register – Index 41h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_ODATA R/W VSB3V GPIO 33 output data. 2 GP32_ODATA R/W VSB3V GPIO 32 output data. 1 GP31_ODATA R/W VSB3V GPIO 31 output data. 0 GP30_ODATA R/W VSB3V GPIO 30 output data. 7.46 GPIO3x Input Status Register – Index 42h Power-on default [7:0] =xxxx_xxxxb Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_PSTS RO VSB3V Read the GPIO33 data on the pin. 2 GP32_PSTS RO VSB3V Read the GPIO32 data on the pin. 1 GP31_PSTS RO VSB3V Read the GPIO31 data on the pin. - 33 - July, 2007 V0.24P 0 GP30_PSTS RO VSB3V Read the GPIO30 data on the pin. 7.47 GPIO3x Level/Pulse Control Register – Index 43h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_OMODE R/W VSB3V GPIO 33 output mode. 0 – level, 1 – pulse. 2 GP32_OMODE R/W VSB3V GPIO 32 output mode. 0 – level, 1 – pulse. 1 GP31_OMODE R/W VSB3V GPIO 31 output mode. 0 – level, 1 – pulse. 0 GP37_OMODE R/W VSB3V GPIO 30 output mode. 0 – level, 1 – pulse. 7.48 GPIO3x Pulse Width Control Register – Index 44h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7:2 Reserved R/W VSB3V Reserved. Read return 0. 1:0 GP3_PLSWD[1:0 R/W VSB3V GPIO3x pulse width. If set the GPIO3x to pulse mode, the pulse width ] can be defined as follows. 00b – 500us (Default) 01b – 1ms 10b – 20ms 11b – 100ms 7.49 GPIO3x Input De-bounce Register – Index 46h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_ENDB R/W VSB3V Enable GPIO33 input de-bounce with 7u or 25ms second that selected by 0x4C bit3. - 34 - July, 2007 V0.24P 2 GP32_ENDB R/W VSB3V Enable GPIO32 input de-bounce with 7u or 25ms second that selected by 0x4C bit2. 1 GP31_ENDB R/W VSB3V Enable GPIO31 input de-bounce with 7u or 25ms second that selected by 0x4C bit1. 0 GP30_ENDB R/W VSB3V Enable GPIO30 input de-bounce with 7u or 25ms second that selected by 0x4C bit0. 7.50 GPIO3x Pulse Inverse Register – Index 47h Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 GP33_PULSINV R/W VSB3V GPIO33 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR44. 2 GP32_PULSINV R/W VSB3V GPIO32 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR44. 1 GP31_PULSINV R/W VSB3V GPIO 31 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR44. 0 GP30_PULSINV R/W VSB3V GPIO30 Pulse inversed. If the pulse inverse is selected, the output pulse is high pulse. Default low pulse. The pulse width is defined in CR44. 7.51 GP3x Edge Detector Enable Register – Index 0x48 Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 EN_GP33EDGE R/W VSB3V Enable GPIO33 Edge Detector. If set to 1, enable GPIO33 edge detection. Default is disable. 2 EN_GP32EDGE R/W VSB3V Enable GPIO32 Edge Detector. If set to 1, enable GPIO32 edge detection. Default is disable. 1 EN_GP31EDGE R/W VSB3V Enable GPIO31 Edge Detector. If set to 1, enable GPIO31 edge detection. Default is disable. - 35 - July, 2007 V0.24P 0 EN_GP30EDGE R/W VSB3V Enable GPIO30 Edge Detector. If set to 1, enable GPIO30 edge detection. Default is disable. 7.52 Edge Detector Status Register – Index 0x49 Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 STS_GP33EDGE R/W VSB3V Indicate GPIO33 Edge Status. If set to 1, the edge of GPIO33 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 2 STS_GP32EDGE R/W VSB3V Indicate GPIO32 Edge Status. If set to 1, the edge of GPIO32 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 1 STS_GP31EDGE R/W VSB3V Indicate GPIO31 Edge Status. If set to 1, the edge of GPIO31 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 0 STS_GP30EDGE R/W VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO30 has occurred. Write 1 to clear this bit. Writing 0 is invalid. 7.53 IRQ or SMI# Enable Register – Index 0x4A Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 EN_GP33IRQ R/W VSB3V Enable GPIO33 IRQ or SMI# Generation. If this bit set to 1, enable GPIO33 to generate IRQ or SMI#. 2 EN_GP32IRQ R/W VSB3V Enable GPIO32 IRQ or SMI# Generation. If this bit set to 1, enable GPIO32 to generate IRQ or SMI#. 1 EN_GP31IRQ R/W VSB3V Enable GPIO31 IRQ or SMI# Generation. If this bit set to 1, enable GPIO31 to generate IRQ or SMI#. 0 EN_GP30IRQ R/W VSB3V Enable GPIO30 IRQ or SMI# Generation. If this bit set to 1, enable GPIO30 - 36 - July, 2007 V0.24P to generate IRQ or SMI#. 7.54 Output Driving Enable – Index 0x4C Power-on default [7:0] =0000_0000b Bit Name R/W PWR Description 7-4 Reserved RO VSB3V Read back will be zero 3 DB_TIME33_SEL R/W VSB3V Select GPIO33 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 2 DB_TIME32_SEL R/W VSB3V Select GPIO32 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 1 DB_TIME31_SEL R/W VSB3V Select GPIO31 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 0 DB_TIME30_SEL R/W VSB3V Select GPIO30 input de-bounce time. If set to 1 de-bounce time is 25ms else if set to 0 de-bounce time is 7u(default). 7.55 CHIPID(1) Register – Index 5Ah Power-on default [7:0] =0000_0011b Bit 7-0 Name CHIPID R/W RO PWR VSB3V Description Chip ID, High byte (8’h03). 7.56 CHIPID(2) Register – Index 5Bh Power-on default [7:0] =0000_0001b Bit 7-0 Name CHIPID R/W RO PWR VSB3V Description Chip ID, Low byte (8’h01). - 37 - July, 2007 V0.24P 7.57 VENDOR ID(1) Register – Index 5Dh Power-on default [7:0] =0001_1001b Bit 7-0 Name VENDOR1 R/W RO PWR VSB3V Description Vendor ID, 8’h19 7.58 VENDOR ID(2) Register – Index 5Eh Power-on default [7:0] =0011_0100b Bit 7-0 Name VENDOR2 R/W RO PWR VSB3V Description Vendor ID, 8h34 8. Electron Characteristic 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage -0.5 to 4.0 V Input Voltage -0.5 to 5.5 V Operating Temperature 0 to +70 °C Storage Temperature -55 to +150 °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8.2 DC Characteristics (Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage VIL 0.8 - 38 - V July, 2007 V0.24P Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL 2.0 V 0.4 V IOL = 12 mA V IOH = - 12 mA +1 µA VIN = VDD -1 µA VIN = 0V 2.4 I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Vt- 0.5 0.8 Input High Threshold Voltage Vt+ 1.6 2.0 Hysteresis VTH 0.5 1.2 Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL 1.1 V VDD = 3.3 V V VDD = 3.3 V V VDD = 3.3 V V IOL = 12 mA V IOH = - 12 mA +1 µA VIN = VDD -1 µA VIN = 0V 2.4 0.4 2.4 - 39 - July, 2007 V0.24P 8.2 DC Characteristics, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage VOL Output High Voltage VOH 0.4 V IOL = 12 mA V IOH = -12 mA V IOL = 8 mA V IOL = 12 mA 0.4 V IOL = 16 mA 0.8 V 2.4 OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 OD16 - Open-drain output pin with sink capability of 16 mA Output Low Voltage VOL INt - TTL level input pin Input Low Voltage VIL Input High Voltage VIH Input High Leakage ILIH +1 µA VIN = VDD Input Low Leakage ILIL -1 µA VIN = 0 V 2.0 V INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 3.3V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 3.3V Hysteresis VTH 0.5 1.2 V VDD = 3.3 V Input High Leakage ILIH +1 µA VIN = VDD Input Low Leakage ILIL -1 µA VIN = 0 V - 40 - July, 2007 V0.24P 8.3 AC Characteristics t t SCL t R R SCL t t HD;SDA t HD;DAT SU;STO SDA IN VALID DATA t SU;DAT SDA OUT Serial Bus Timing Diagram Serial Bus Timing PARAMETER SYMBOL MIN. SCL clock period t-SCL 10 uS Start condition hold time tHD;SDA 4.7 uS Stop condition setup-up time tSU;STO 4.7 uS DATA to SCL setup time tSU;DAT 120 nS DATA to SCL hold time tHD;DAT 5 nS SCL and SDA rise time tR 1.0 uS SCL and SDA fall time tF 300 nS - 41 - MAX. UNIT July, 2007 V0.24P 9. Ordering Information Part Number Package Type Production Flow F75121R 28 PIN SSOP Commercial, 0°C to +70°C F75121RG 28 PIN SSOP Green Package Commercial, 0°C to +70°C 10. Package Dimensions Symbol Dimension in mm Min Nom Max Min Nom Max A 1.35 1.63 1.75 0.053 0.064 0.069 A1 0.10 0.15 0.25 0.004 0.006 0.010 A2 0.50 0.059 B 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 e 0.635 BASIC 0.025BASIC D 9.80 9.91 10.01 0.386 0.390 0.394 E 5.79 5.99 6.20 0.228 0.236 0.244 E1 3.81 3.91 3.99 0.150 0.154 0.157 L 0.41 0.635 1.27 0.016 0.025 0.050 H 0.25 0.50 0.010 ZD θ - 42 - Dimension in inch 0.838 REF 0 0 0.020 0.033 REF 0 8 0 0 0 8 July, 2007 V0.24P Feature Integration Technology Inc. Headquarters Taipei Office 3F-7, No 36, Tai Yuan St., Bldg. K4, 7F, No.700, Chung Cheng Rd., Chupei City, Hsinchu, Taiwan 302, R.O.C. Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 886-3-5600168 TEL : 866-2-8227-8027 FAX : 886-3-5600166 FAX : 866-2-8227-8037 www: http://www.fintek.com.tw Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner - 43 - July, 2007 V0.24P