www.fairchildsemi.com FMS3818 Triple Video D/A Converters 3 x 8 bit, 180 Ms/s Features Description • • • • • The FMS3818 is a low-cost triple D/A converter, tailored to fit graphics and video applications where speed is critical. ±2.5% gain matching ±0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3 Volt power supply CMOS-level inputs are converted to analog current outputs that can drive 25–37.5Ω loads corresponding to doubly-terminated 50–75Ω loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications the internal 1.25V reference voltage can be overridden by the VREF input. Applications • PC Graphics • Video signal conversion – RGB – YCBCR – Composite, Y, C Few external components are required, just the current reference resistor, current output load resistors, bypass capacitors and decoupling capacitors. Package is a 48-lead LQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70°C. Block Diagram SYNC SYNC BLANK G7-0 B7-0 R7-0 IOS 8 8 bit D/A Converter IOG 8 8 bit D/A Converter IOB 8 8 bit D/A Converter IOR CLK +1.25V Ref COMP RREF VREF REV. 1.2.3 December 2004 FMS3818 DATA SHEET Functional Description Within the FMS3818 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert these currents to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates sync current from IOS for sync-ongreen video signals. VDDA IOS VDDA BLANK gates the D/A inputs. If BLANK = H, the D/A inputs control the output currents to be added to the output blanking level. If BLANK = L, data inputs and the pedestal are disabled. D/A Outputs Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK SYNC G7-0 Typical LSB current step is 73.2 µA. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. VDDA B7-0 To implement a doubly-terminated 75Ω transmission line, a shunt 75Ω resistor should be placed adjacent to the analog output pin. With a terminated 75Ω line connected to the analog output, the load on the FMS3818 current source is 37.5Ω. VDDA R7-0 The FMS3818 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the RREF resistor should be doubled. Figure 1. FMS3818 Current Source Structure Digital Inputs Incoming GBR data is registered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of CLK after a delay, tDO. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip. data: 700 mV max. sync: 307 mV Figure 2. Nominal Output Levels 2 Voltage Reference Full scale current is a multiple of the current ISET through an external resistor, RSET connected between the RREF pin and GND. Voltage across RSET is the reference voltage, VREF, which can be derived from either the 1.25 volt internal bandgap reference or an external voltage reference connected to VREF. To minimize noise, a 0.1µF capacitor should be connected between VREF and ground. ISET is mirrored to each of the GBR output current sources. To minimize noise, a 0.1µF capacitor should be connected between the COMP pin and the analog supply voltage VDDA. Power and Ground Required power is a single +3.3 Volt supply. To minimize power supply induced noise, analog +3.3V should be connected to VDDD and VDDA pins with 0.1 and 0.01 µF decoupling capacitors placed adjacent to each VDD pin or pin pair. High slew-rate digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. REV. 1.2.3 December 2004 DATA SHEET FMS3818 Table 1. Output Voltage Coding VREF = 1.25 V, RREF = 348 Ω, RL = 37.5 Ω RGB7-0 (MSB…LSB) SYNC BLANK VRED, VBLUE (mV) VGREEN (mV) 1111 1111 1 1 700 1,007 1111 1111 0 1 700 700 1111 1110 1 1 697 1,004 1111 1101 1 1 695 1,001 • • • • • • • • • • 1000 0000 1 1 351 658 0111 1111 1 1 349 656 0111 1111 0 1 349 349 • • • • • • • • • • 0000 0010 1 1 5 312 0000 0001 1 1 3 310 0000 0000 1 1 0 307 0000 0000 0 1 0 0 XXXX XXXX 1 0 0 307 XXXX XXXX 0 0 0 0 Pin Assignments 48 47 46 45 44 43 42 41 40 39 38 37 GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC LQFP Package 1 2 3 4 5 6 7 8 9 10 11 12 FMS3818 36 35 34 33 32 31 30 29 28 27 26 25 RREF VREF COMP IOR IOG VDDA VDDA IOB GND GND CLK NC NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC 13 14 15 16 17 18 19 20 21 22 23 24 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDDD REV. 1.2.3 December 2004 3 FMS3818 DATA SHEET Pin Descriptions Pin Name Pin Number Value Pin Function Description Clock and Data Inputs CLK 26 CMOS Clock Input. Pixel data is registered on the rising edge of CLK. CLK should be driven by a dedicated buffer to avoid reflection induced jitter, overshoot, and undershoot. R7-0 G7-0 B7-0 47-40 9-2 23-16 CMOS Red, Green, and Blue Pixel Data Inputs. RGB digital inputs are registered on the rising edge of CLK. SYNC 11 CMOS Sync Pulse Input. Bringing SYNC LOW, disables a current source which superimposes a sync pulse on the IOG output. SYNC and pixel data are registered on the rising edge of CLK. SYNC does not override any other data and should be used only during the blanking interval. If sync pulses are not required, SYNC should be connected to GND. BLANK 10 CMOS Blanking Input. When BLANK is LOW, pixel data inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK. 33 32 29 0.700 Vp-p Red, Green, and Blue Current Outputs. Current source outputs can drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses can be added to the green output. When SYNC is HIGH, the current added to IOG is: Controls Video Outputs IOR IOG IOB IOS = 2.33 (VREF / RREF) Voltage Reference VREF 35 +1.25 V Voltage Reference Input/Output. Internal 1.25V voltage reference is available on this pin. An external +1.25 Volt reference may be applied to this pin to override the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. RREF 36 348 Ω Current-set Resistor Node. Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 5.31 (VREF/IFS) where IFS is the full-scale output current (amps) from the D/A converter (without sync). Sync is 0.439 IFS. D/A full-scale current may also be calculated from: IFS = VFS/RL Where VFS is the full-scale voltage level and RL is the total resistive load (ohms) on each D/A converter. COMP 4 34 0.1 µF Compensation Capacitor Node. A 0.1 µF ceramic capacitor must be connected between COMP and VDD to stabilize internal bias circuitry. REV. 1.2.3 December 2004 DATA SHEET FMS3818 Pin Descriptions (continued) Pin Name Pin Number Value Pin Function Description Power, Ground VDDA 30, 31 +3.3V Analog Supply Voltage. VDDD 12 +3.3V Digital Supply Voltage. GND 1, 14, 15, 27, 28, 38, 39, 48 0.0V Ground. NC 13, 24, 25, 37 — REV. 1.2.3 December 2004 No Connect 5 FMS3818 DATA SHEET Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Min Typ Max Unit Power Supply Voltage VDDA (Measured to GND) -0.5 4 V VDDD (Measured to GND) -0.5 4 V Applied Voltage (Measured to GND)2 -0.5 VDDD + 0.5 V Forced Current3,4 -5.0 5.0 mA -0.5 VDDA + 0.5 V -10.0 10.0 mA -0.5 VDDA + 0.5 V -60.0 60.0 mA unlimited sec. 110 °C Junction 150 °C Lead Soldering (10 seconds) 300 °C Vapor Phase Soldering (1 minute) 220 °C 150 °C Digital Inputs Analog Inputs Applied Voltage (Measured to GND)2 Forced Current3,4 Analog Outputs Applied Voltage (Measured to GND)2 3,4 Forced Current Short Circuit Duration (single output in HIGH state to ground) Temperature Operating, Ambient -20 Storage -65 Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter Min Nom Max Units VDD Power Supply Voltage 3.0 3.3 3.6 V VREF Reference Voltage, External 1.0 1.25 1.5 V CC Compensation Capacitor 0.1 µF RL Output Load 37.5 Ω TA Ambient Temperature, Still Air 0 70 °C Test Rank Definitions Rank 6 P Production tested at 25°C. D Guaranteed by design over full temperature range. C Guaranteed by characterization and design over full temperature range. T Target specification, pending characterization. REV. 1.2.3 December 2004 DATA SHEET FMS3818 Electrical Characteristics1 Parameter Temp Test Rank Min Typ Max Unit FMS3818 25°C P FMS3818 Full C 90 Full D 300 mW 0.8 V +1 µA +1 µA Power Supply Currents IDD Supply Current Power Dissipation 80 mA Digital Inputs VIH Input Voltage, HIGH Full PC VIL Input Voltage, LOW Full PC IIH Input Current, HIGH Full PC -1 IIL Input Current, LOW -1 CI Input Capacitance Full PC 25°C D 2.5 V 4 pF Analog Outputs Output Current 25°C PC RO Output Resistance 25°C C 40 30 mA kΩ CO Output Capacitance 25°C D 7 pF Output Voltage Full PC Temperature Coefficient Full CT Reference Output VREF 1.135 1.25 1.365 V ppm/°C Note: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. Switching Characteristics1 Parameter Temp Test Rank Min Typ Max Unit 180 Ms/s Clock Input Conversion rate FMS3818 Full C tPWH Pulse-width HIGH Full C 2 ns tPWL Pulse-width LOW Full C 2 ns FMS3818 25°C P 1.5 ns FMS3818 Full C 2 ns FMS3818 25°C P 0.6 ns FMS3818 Full C 0.6 ns Data Inputs tS tH Setup Hold Data Outputs2 tD Clock to Output Delay Full C 1.6 ns tR Rise Time Full C 0.6 ns tF Fall Time Full C 0.4 ns tSET Settling Time C 2.5 ns tSKEW Skew C 0.3 ns Notes: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. 2. With 50Ω doubly terminated load with internal 1.25V reference. REV. 1.2.3 December 2004 7 FMS3818 DATA SHEET DC Performance1 Parameter Resolution DNL INL Differential Non-Linearity Error Test Rank Min Full D 8 Typ1 Max P -0.5 +0.5 Full C -0.5 +0.5 25°C P -0.5 +0.5 Full C -0.5 +0.5 Full PC Full PC Absolute Gain Error Full PC -3.5 Full-scale Output Current1 Full C 18.0 25°C P Full-scale Output Current Full PC Power Supply Rejection Ratio (DC) Full C Integral Non-Linearity Error Gain Matching Error 1 2 -2.5 18.7 0 LSB LSB 0.01 %FS +2.5 %FS +3.5 %FS 19.4 mA +0.01 %/% 18.7 -0.01 Unit bits 25°C Offset Error PSRR Temp mA Thermal θJC Resistance, Junction-to-Case θJA Resistance, Junction-to-Ambient °C /W D 91 °C /W Notes: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. RREF = 348Ω. 2. With internal reference. Trim RSET to calibrate full-scale current. AC Performance1 Temp Test Rank 7 C 20 pVsec DAC-to-DAC Crosstalk 25°C C 30 dB Data Feedthrough 25°C C 50 dB Clock Feedthrough 25°C C 60 dB Parameter Min Typ1 Max Unit Analog Outputs Glitch Energy Note: 1. Specified under normal operation conditions: VDDA = VDDD = 3.3V with external 1.25V reference. 8 REV. 1.2.3 December 2004 DATA SHEET FMS3818 Timing Diagram tPWL 1/fS tPWH CLK tH tS PIXEL DATA & CONTROLS DataN DataN+1 DataN+2 3%/FS 90% tD tSET tF OUTPUT 50% Applications Information tR 10% 2. The power plane for the FMS3818 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the FMS3818 is the same as that of the system's digital circuitry, power to the FMS3818 should be decoupled with 0.1µF and 0.01µF capacitors and isolated with a ferrite bead. It is important that the FMS3818 power supply is well-regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The FMS3818 has separate analog and digital circuits. To keep digital system noise away from the D/A converter, it is recommended that power supply voltages come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the FMS3818, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the FMS3818 and its related analog circuitry can have an adverse effect on performance. Printed Circuit Board Layout 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Figure 4 illustrates a typical FMS3818 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage reference source. Grounding Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The FMS3818 should be located near the board edge, close to the analog output connectors. REV. 1.2.3 December 2004 Improved Transition Times Output shunt capacitance dominates slowing of output transition times, whereas series inductance causes a small amount of ringing that affects overshoot and settling time. With a doubly terminated 75Ω load, transition times can be improved by matching the capacitive impedance output of the FMS3818. Output capacitance can be matched with a 220 nH inductor in series with the 75Ω source termination. 9 FMS3818 DATA SHEET U1 FMS3818 IOG IOB IOR W1 COAX 32 R1 75 W2 COAX 29 R2 75 W3 COAX 33 R3 75 L1 220nH R4 75 L2 220nH R5 75 L3 220nH R6 75 Figure 3. Schematic, FMS3818 Transition Time Sharpening Circuit 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -5.00 Gout (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5.00 0.00 5.00 10.00 15.00 20.00 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5.00 0.00 5.00 10.00 Time (ns) Time (ns) Figure 4. Unmatched tR. Figure 5. Matched tR. 0.00 5.00 10.00 Time (ns) Figure 6. Unmatched tF. 10 glitches at 25 and 37.5 ns, corresponding to secondary and tertiary reflections. Inductor values should be selected to match the length and type of the cable. Gout (V) Rout (V) Rout (V) A 220 nH inductor trims the performance of a 4 ft cable, quite well. In Figures 4 through 7, the glitch at 12.5 ns, is due to a reflection from the source. Not shown, are smaller 15.00 20.00 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -5.00 0.00 5.00 10.00 15.00 20.00 15.00 20.00 Time (ns) Figure 7. Matched tF. REV. 1.2.3 December 2004 DATA SHEET FMS3818 +3.3V 0.1 µF 10 µF 0.01µF 0.1µF VDDD RED PIXEL INPUT R7-0 GREEN PIXEL INPUT G7-0 BLUE PIXEL INPUT B7-0 CLOCK SYNC BLANK GND VDDA Red IOG FMS38XX ZO=75Ω IOR IOB 75Ω 75Ω ZO=75Ω 75Ω Blue ZO=75Ω 75Ω 75Ω Triple 8-bit D/A Converter VDDA COMP CLK SYNC BLANK 75Ω Green w/Sync 0.1µF 3.3kΩ (only required with external reference) VREF RREF 348Ω LM185-1.2 (Optional) 0.1µF Figure 8. Typical Interface Circuit Related Products • FMS3110/3115 Triple 10-bit 150 Msps D/A Converters • FMS9884A 3 x 8 bit 140 Ms/s A/D Converter REV. 1.2.3 December 2004 11 FMS3818 DATA SHEET Mechanical Dimensions 48-Lead LQFP Package Inches Symbol Min. A A1 A2 B D/E D1/E1 e L N ND α ccc Millimeters Max. .055 .063 .001 .005 .053 .057 .006 .010 .346 .362 .268 .284 .019 BSC .017 .029 48 12 0° 7° .004 Min. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. Max. 1.40 1.60 .05 .15 1.35 1.45 .17 .27 8.8 9.2 6.8 7.2 .50 BSC .45 .75 48 12 0° 7° 0.08 2. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Pin 1 identifier is optional. 7 4. Dimension N: Number of terminals. 5. Dimension ND: Number of terminals per package edge. 2 6. "L" is the length of terminal for soldering to a substrate. 7. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm. 6 4 5 D D1 e PIN 1 IDENTIFIER E E1 C L α 0.063" Ref (1.60mm) See Lead Detail A Base Plane A2 B A1 Seating Plane -CLEAD COPLANARITY ccc 12 C REV. 1.2.3 December 2004 FMS3818 DATA SHEET Ordering Information Product Number Conversion Rate FMS3818KRC 180 Ms/s FMS3818KRC_NL 180 Ms/s Lead Free Yes Temperature Range Screening Package Package Marking 0°C to 70°C Commercial 48-Lead LQFP 3818KRC 0°C to 70°C Commercial 48-Lead LQFP 3818KRC NL DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 2001 Fairchild Semiconductor Corporation