CADEKA TMC3033KRC80

www.cadeka.com
TMC3033
Triple Video D/A Converter
10 bit, 80 Msps
Features
Description
•
•
•
•
•
•
The TMC3033 is a high-speed triple 10-bit D/A converter
especially suited for video and graphics applications.
It offers 10-bit resolution, TTL-compatible inputs, low
power consumption, and requires only a single +3.3 Volt
±5% power supply. It has single-ended current outputs,
SYNC and BLANK control inputs, and a separate current
source for adding sync pulses to the Green D/A converter
output. It is ideal for generating analog RGB from digital
RGB and driving computer display and video monitors.
Three speed grades are available: 30, 50, and 80 Msps.
10-bit resolution
80, 50, and 30 megapixels per second
Sync and blank controls
Sync on green D/A output
1.0V p-p video into 37.5Ω or 75Ω load
Enhancement of ADV7122
– Internal bandgap voltage reference
– Double-buffered data for low distortion
• TTL-compatible inputs
• Low glitch energy
• Single +3.3 Volt ±5% power supply
The TMC3033 triple D/A converter is available in a 44-lead
plastic J-leaded PLCC and 48-lead plastic LQFP package.
It is fabricated on a sub-micron CMOS process with performance guaranteed from 0°C to 70°C.
Applications
• Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Block Diagram
SYNC
BLANK
G9-0
B9-0
R9-0
10
10 bit
D/A Converter
IOG
10
10 bit
D/A Converter
IOB
10
10 bit
D/A Converter
IOR
CLK
+1.235V
Ref
COMP
RREF
VREF
65-3003-01
Rev. 1.0.0
TMC3033
PRODUCT SPECIFICATION
Functional Description
The TMC3033 is a low-cost triple 10-bit CMOS D/A
converter designed to directly drive computer CRT displays
and video transmission lines at pixel rates of up to 80 Msps.
It comprises three identical 10-bit D/A converters with
registered data inputs, common clock, and internal voltage
reference. An independent current source allows sync to be
added to the green D/A converter output.
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
changes tDO after the rising edge of CLK. There is one stage
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3033 are 80, 50, and 30 MHz.
SYNC and BLANK
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
source which is connected to the green D/A converter. This
connection adds a 40 IRE sync pulse to the D/A output and
brings that D/A output to 0.0 Volts during the sync tip.
SYNC and BLANK are registered on the rising edge of
CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
65-3003-02
Figure 1. Nominal Output Levels
2
D/A Outputs
Each D/A output is a current source. To obtain a voltage output a resistor must be connected to ground. Output voltage of
the D/A converters depends upon this resistor, the reference
voltage, and the value of the gain-setting resistor connected
between RREF and GND.
Normally, a source termination resistor of 75 Ohms is connected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be connected with another 75 Ohm termination resistor at the far
end of the cable. This “double termination” presents the D/A
converter with a net resistive load of 37.5 Ohms.
The TMC3033 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the value of the resistor on RREF should be
increased.
Voltage Reference
The TMC3033 has an internal bandgap voltage reference
of +1.235 Volts. An external voltage reference may be
connected to the VREF pin, overriding the internal voltage
reference. All three D/A converters are driven from the same
reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
The TMC3033 D/A converter requires a single +3.3 Volt
power supply. The analog (VDD) power supply voltage
should be decoupled to GND to reduce power supply
induced noise. 0.1µF decoupling capacitors should be placed
as close as possible to the power pins.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
PRODUCT SPECIFICATION
TMC3033
Table 1. Output Voltage versus Input Code, SYNC, and BLANK
VREF = 1.235 V, RREF = 572 Ω, RL = 37.5 Ω
Red and Blue D/As
Green D/A
RGB9-0
(MSB...LSB)
SYNC
BLANK
VOUT
SYNC
BLANK
VOUT
11 1111 1111
X
1
0.7140
1
1
1.0000
11 1111 1110
X
1
0.7134
1
1
0.9994
11 1111 1101
X
1
0.7127
1
1
0.9987
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 0000 0000
X
1
0.3843
1
1
0.6703
01 1111 1111
X
1
0.3837
1
1
0.6697
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
X
1
0.0553
1
1
0.3413
00 0000 0001
X
1
0.0546
1
1
0.3406
00 0000 0000
X
1
0.0540
1
1
0.3400
xx xxxx xxxx
X
0
0.0000
1
0
0.2860
xx xxxx xxxx
X
0
0.0000
0
0
0.0000
9
37
10
36
PLCC
35
11
TMC3033
12
34
28
27
26
25
24
29
23
30
17
22
31
16
21
32
15
20
14
19
33
18
13
RREF
VREF
COMP
IOR
IOG
VDD
VDD
IOB
GND
GND
CLK
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
SYNC
VDD
1
2
3
4
5
6
7
8
9
10
11
12
LQFP
TMC3033
36
35
34
33
32
31
30
29
28
27
26
25
RREF
VREF
COMP
IOR
IOG
OV DD
VDD
IOB
GND
GND
CLOCK
NC
13
14
15
16
17
18
19
20
21
22
23
24
38
NC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
NC
39
8
48
47
46
45
44
43
42
41
40
39
38
37
40
41
42
43
1
44
2
3
4
7
VDD
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
SYNC
5
6
G0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
G0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
NC
Pin Assignments
3
TMC3033
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name
PLCC
LQFP
Value
Description
Clock and Pixel I/O
CLK
29
26
TTL
Clock. The clock input is TTL-compatible and all pixel data
is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
R9-0
5, 4, 3, 2, 1,
44, 43, 42,
41, 40
47, 46, 45,
44, 43, 42,
41, 40, 39,
38, 37
TTL
Red pixel data inputs. The Red digital input is TTLcompatible and registered on the rising edge of CLK.
G9-0
15, 14, 13, 48, 9, 8, 7, 6,
12, 11, 10, 9, 5, 4, 3, 2, 1
8, 7, 6
TTL
Green pixel data inputs. The Green digital input is TTLcompatible and registered on the rising edge of CLK.
B9-0
28, 27, 26,
25, 24, 23,
22, 21, 20,
19
23, 22, 21,
20, 19, 18,
17, 16, 15,
14
TTL
Blue pixel data inputs. The Blue digital input is TTLcompatible and registered on the rising edge of CLK.
17
11
TTL
Sync pulse Input. Bringing SYNC LOW, turns off a 40
IRE (7.62 mA) current source which forms a sync pulse on
the Green D/A converter output. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during
the blanking interval.
Controls
SYNC
Since this is a single-supply D/A and all signals are
positive-going, sync is added to the bottom of the Green
D/A range. So turning SYNC OFF means turning the
current source ON. When a sync pulse is desired, the
current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC
should be connected to GND.
BLANK
16
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are
ignored and the D/A converter outputs are driven to the
blanking level. BLANK is registered on the rising edge of
CLK and has the same pipeline latency as SYNC.
IOR
36
33
0.714 Vp-p
Red D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
IOG
35
32
1 V p-p
Green D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Sync pulses may be added to the Green D/A output.
IOB
32
29
0.714 Vp-p
Blue D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Video Outputs
4
PRODUCT SPECIFICATION
TMC3033
Pin Descriptions (continued)
Pin Number
Pin Name
PLCC
LQFP
Value
Description
Voltage Reference
VREF
38
35
+1.235 V
Voltage Reference output/input. An internal voltage
source of +1.235 Volts is output on this pin. An external
+1.235 Volt reference may be applied here which
overrides the internal reference. Decoupling VREF to GND
with a 0.1µF ceramic capacitor is required.
RREF
39
36
572 Ω
Current-setting resistor. The full-scale output current of
each D/A converter is determined by the value of the
resistor connected between RREF and GND. The nominal
value for RREF is found from:
RREF = 9.1( VREF/IFS),
but is optimized to be 572 Ω. IFS is the full-scale (white)
output current (in amps) from an output without sync. Sync
current is 0.4 * IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/ RL
Where VFS is the white voltage level and RL is the total
resistive load (in ohms) on each D/A converter. VFS is the
blank to full-scale voltage.
COMP
37
34
0.1 µF
Compensation capacitor. A 0.1 µF ceramic capacitor
must be connected between COMP and VDD to stabilize
internal bias circuitry.
Power and Ground
VDD
18, 33, 34
12, 30, 31
+3.3 V
Power supply
GND
30, 31
27, 28
0.0 V
Ground
Equivalent Circuits
VDD
VDD
p
Digital
Input
n
p
VDD
n
OUT
GND
GND
27014C
Figure 2. Equivalent Digital Input Circuit
27013B
Figure 3. Equivalent Analog Output Circuit
5
TMC3033
PRODUCT SPECIFICATION
Equivalent Circuits (continued)
VDD
p
p
RREF
VREF
27012B
GND
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
7.0
V
-0.5
VDD + 0.5
V
-10.0
10.0
mA
Applied Voltage (measured to GND)2
-0.5
VDD + 0.5
V
Forced Current3,4
-60.0
60.0
mA
infinite
second
110
°C
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
Power Supply Voltage
VDD (Measured to GND)
Inputs
Applied Voltage (measured to GND)2
Forced
Current3,4
Outputs
Short Circuit Duration (single output in HIGH state to ground)
Temperature
Operating, Ambient
Storage
-20
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
PRODUCT SPECIFICATION
TMC3033
Operating Conditions
Parameter
VDD
Power Supply Voltage
fS
Conversion Rate
Min
Nom
Max
3.135
3.3
Units
3.465
V
TMC3033-30
30
Msps
TMC3033-50
50
Msps
TMC3033-80
80
Msps
tPWH
CLK Pulsewidth, HIGH
5.2
ns
tPWL
CLK Pulsewidth, LOW
5.2
ns
ts
Input Data Setup Time
3.6
ns
th
Input Date Hold Time
2
ns
VREF
Reference Voltage, External
CC
Compensation Capacitor
RL
Output Load
VIH
Input Voltage, Logic HIGH
2.0
VDD
V
VIL
Input Voltage, Logic LOW
GND
0.8
V
TA
Ambient Temperature, Still Air
0
70
°C
Max
Units
TMC3033-30
90
mA
TMC3033-50
95
TMC3033-80
132
1.0
1.235
1.5
V
µF
0.1
Ω
37.5
Electrical Characteristics
Conditions3
Parameter
IDD
PD
Power Supply
Total Power
Current2
Dissipation2
Min
Typ1
VDD = Max
VDD = Max
TMC3033-30
300
TMC3033-50
315
TMC3033-80
435
100
mW
RO
Output Resistance
kΩ
CO
Output Capacitance
IOUT = 0mA
30
pF
IIH
Input Current, HIGH
VDD = Max, VIN = 2.4V
-1
µA
IIL
Input Current, LOW
VDD = Max, VIN = 0.4V
1
µA
IREF
VREF Input Bias Current
±100
µA
VREF
Reference Voltage Output
VOC
Output Compliance
CDI
Digital Input Capacitance
0
1.235
Referred to VDD
-0.4
V
0
+1.5
V
4
10
pF
Notes:
1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C.
2. Minimum/Maximum values with VDD = Max and TA = Min.
3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω
7
TMC3033
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions2
VDD = Min
Min
Typ1
Max
Units
10
15
ns
1
2
ns
tD
Clock to Output Delay
tSKEW
Output Skew
tR
Output Risetime
10% to 90% of Full Scale
3
4
ns
tF
Output Falltime
90% to 10% of Full Scale
3
4
ns
tSET
Output Settling Time
to 3%/FS
15
ns
Notes:
1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω.
System Performance Characteristics
Conditions2
Parameter
Typ1
Max
Units
VDD, VREF = Nom
±0.1
±0.25
%/FS
Min
ELI
Integral Linearity Error
ELD
Differential Linearity Error
VDD, VREF = Nom
±0.1
±0.25
%/FS
EDM
DAC to DAC Matching
VDD, VREF = Nom
7
10
%
VOF
Output Offset Current
VDD = Max, R, G, B = 000h
20
mA
PSR
Power Supply Rejection
0.05
%/%
Notes:
1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω.
Timing Diagram
t PWL
1/f S
t PWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
tD
OUTPUT
50%
t SET
tF
tR
10%
65-3003-03
8
PRODUCT SPECIFICATION
TMC3033
Applications Discussion
Figure 4 illustrates a typical TMC3033 interface circuit.
In this example, an optional 1.2 Volt bandgap reference is
connected to the VREF output, overriding the internal voltage reference source.
Grounding
It is important that the TMC3033 power supply is wellregulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video signals at the output of the circuit. The TMC3033 has separate
analog and digital circuits. To keep digital system noise from
the D/A converter, it is recommended that power
supply voltages (VDD) come from the system analog power
source and all ground connections (GND) be made to the
analog ground plane. Power supply pins should be individually decoupled at the pin.
the power supply for the TMC3033 is the same as that of
the system's digital circuitry, power to the TMC3033
should be decoupled with 0.1µF and 0.01µF capacitors
and isolated with a ferrite bead.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the TMC3033, the
voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the
TMC3033 and its related analog circuitry can have an
adverse effect on performance.
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1.
Keep the critical analog traces (VREF, IREF, COMP,
IOR, IOG, IOB) as short as possible and as far as possible from all digital signals. The TMC3033 should be
located near the board edge, close to the analog output
connectors.
2.
The power plane for the TMC3033 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the VDD pins. If
Related Products
•
•
•
•
•
•
•
•
•
•
•
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+3.3V
10µF
0.1µF
VDD
RED PIXEL
INPUT
R9-0
GREEN PIXEL
INPUT
G9-0
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
B9-0
GND
Red
IO R
IO G
TMC3033
IO B
ZO=75Ω
75Ω
Green
75Ω
Blue
ZO=75Ω
75Ω
75Ω
75Ω
Triple 10-bit
D/A Converter
+3.3V
COMP
CLK
SYNC
BLANK
ZO=75Ω
75Ω
0.1µF
3.3kΩ
572Ω
LM185-1.2
(Optional)
VREF
RREF
0.1µF
65-3033-04
Figure 4. Typical Interface Circuit
9
TMC3033
PRODUCT SPECIFICATION
Mechanical Dimensions – 44-Lead PLCC Package
Inches
Symbol
Min.
A
A1
A2
B
B1
D/E
D1/E1
D3/E3
e
J
ND/NE
N
ccc
Max.
.165
.180
.090
.120
.020
—
.013
.021
.026
.032
.685
.695
.650
.656
.500 BSC
.050 BSC
.042
.056
11
44
—
.004
Millimeters
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Max.
4.19
4.57
2.29
3.05
.51
—
.33
.53
.66
.81
17.40
17.65
16.51
16.66
12.7 BSC
1.27 BSC
1.07
1.42
11
44
—
0.10
2. Corner and edge chamfer (J) = 45°
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
3
2
E
E1
D
J
D1
D3/E3
B1
J
e
A
A1
A2
B
–C–
LEAD COPLANARITY
ccc C
10
PRODUCT SPECIFICATION
TMC3033
Mechanical Dimensions – 48-Lead LQFP Package
Inches
Symbol
Min.
A
A1
A2
B
D/E
D1/E1
e
L
N
ND
α
ccc
Millimeters
Max.
.055
.063
.001
.005
.053
.057
.006
.010
.346
.362
.268
.284
.019 BSC
.017
.029
48
12
0°
7°
.004
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Max.
1.40
1.60
.05
.15
1.35
1.45
.17
.27
8.8
9.2
6.8
7.2
.50 BSC
.45
.75
48
12
0°
7°
0.08
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
6
4
5
8. To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E E1
C
L
α
0.063" Ref (1.60mm)
See Lead Detail
A
Base Plane
A2
B
A1
Seating Plane
-CLEAD COPLANARITY
ccc
C
11
TMC3033
PRODUCT SPECIFICATION
Ordering Information
Product Number
Conversion
Rate (Msps)
Temperature
Range
Screening
Package
Package
Marking
TMC3033R2C30
30 Msps
TA = 0°C to 70°C
Commercial
44-Lead PLCC
3033R2C30
TMC3033R2C50
50 Msps
TA = 0°C to 70°C
Commercial
44-Lead PLCC
3033R2C50
TMC3033R2C80
80 Msps
TA = 0°C to 70°C
Commercial
44-Lead PLCC
3033R2C80
TMC3033KRC30
30 Msps
TA = 0°C to 70°C
Commercial
48-Lead LQFP
3033KRC30
TMC3033KRC50
50 Msps
TA = 0°C to 70°C
Commercial
48-Lead LQFP
3033KRC50
TMC3033KRC80
80 Msps
TA = 0°C to 70°C
Commercial
48-Lead LQFP
3033KRC80
3/3/99 0.0m 001
Stock#DS30003033