CADEKA TMC3503R2C50

www.cadeka.com
TMC3503
Triple Video D/A Converter
8 bit, 80 Msps, 5V
Features
Description
•
•
•
•
•
•
•
The TMC3503 is a high-speed triple 8-bit D/A converter
especially suited for video and graphics applications.
It offers 8-bit resolution, TTL-compatible inputs, low power
consumption, a power-down sleep mode, and requires only a
single +5 Volt power supply. It has single-ended current
outputs, SYNC and BLANK control inputs, and a separate
current source for adding sync pulses to any D/A converter
output. WHITE and SLEEP control inputs are available on
PLCC parts. It is ideal for generating analog RGB from
digital RGB and driving computer display and video monitors. Three speed grades are available: 30, 50, and 80 Msps.
•
•
•
•
8-bit resolution
80, 50, and 30 megapixels per second
±0.5 LSB linearity error
Sync, blank, and white controls
Independent sync current output
1.0V p-p video into 37.5Ω or 75Ω load
Enhancemenet of ADV7120
– Internal bandgap voltage reference
– Double-buffered data for low distortion
– Power-down sleep mode
Double-buffered data for low distortion
TTL-compatible inputs
Low glitch energy
Single +5 Volt power supply
The TMC3503 triple D/A converter is available in a 44-lead
plastic J-leaded PLCC. It is also available in a 48-lead plastic
LQFP package. It is fabricated on a sub-micron CMOS
process with performance guaranteed from 0°C to 70°C.
Applications
• Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Block Diagram
SYNC
BLANK
WHITE [PLCC only]
G7-0
B7-0
R7-0
SYNC
IOS
[LQFP only]
8
8 bit D/A
Converter
IOG
8
8 bit D/A
Converter
IOB
8
8 bit D/A
Converter
IOR
SLEEP [PLCC only]
CLOCK
+1.235V
Ref
COMP
RREF
VREF
65-3503-01
REV. 1.02 11/24/99
TMC3503
PRODUCT SPECIFICATION
Functional Description
The TMC3503 is a low-cost triple 8-bit CMOS D/A converter designed to directly drive computer CRT displays at
pixel rates up to 80 Msps. It comprises three identical 8-bit
D/A converters with registered data inputs, common clock,
and internal voltage reference. An independent current
source allows sync to be added to any D/A converter output.
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
changes tDO after the rising edge of CLK. There is one stage
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3503 are 80, 50, and 30 MHz.
SYNC and BLANK
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
source which is brought off the chip through the IOS pin.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
65-3503-02
Figure 1. Nominal Output Levels
IOS may be connected to any one D/A output, or used independently. It is commonly tied to the green D/A converter for
“Sync on Green” operation. This connection adds a 40 IRE
sync pulse to the D/A output and brings that D/A output to
0.0 Volts during the sync tip. SYNC and BLANK are registered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
WHITE
The WHITE control drives all three D/As to full-scale, overriding the data inputs. It is overridden by the BLANK input,
and is independent of SYNC.
2
SLEEP
The SLEEP control, when HIGH, places the TMC3503 in a
power-down state. This function operates asynchronously.
D/A Outputs
Each D/A output is a current source. To obtain a voltage output, a resistor must be connected to ground. Output voltage
depends upon this external resistor, the reference voltage,
and the value of the gain-setting resistor connected between
RREF and GND.
Normally, a source termination resistor of 75 Ohms is connected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be connected with another 75 Ohm termination resistor at the far
end of the cable. This "double termination" presents the D/A
converter with a net resistive load of 37.5 Ohms.
The TMC3503 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the value of the resistor on RREF should be
increased.
Voltage Reference
The TMC3503 has an internal bandgap voltage reference of
+1.235 Volts. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. All three D/A converters are driven from the same
reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
The TMC3503 D/A converter requires a single +5.0 Volt
power supply. The analog (VDD) power supply voltage
should be decoupled to GND to reduce power supply
induced noise. 0.1µF decoupling capacitors should be placed
as close as possible to the power pins.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Table 1. Output Voltage versus Input Code, SYNC, BLANK, and WHITE
VREF = 1.235 V, RREF = 590 Ω, RL = 37.5 Ω
All D/As
D/A with IOS Connected
RGB7-0
(MSB…LSB)
SYNC
BLANK
WHITE
VOUT
SYNC
BLANK
WHITE
VOUT
XXXX XXXX
X
1
1
0.714
1
1
1
1.000
1111 1111
X
1
0
0.714
1
1
0
1.000
1111 1110
X
1
0
0.711
1
1
0
0.997
1111 1101
X
1
0
0.709
1
1
0
0.995
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000 0000
X
1
0
0.385
1
1
0
0.671
1111 1111
X
1
0
0.383
1
1
0
0.669
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0000 0010
X
1
0
0.059
1
1
0
0.345
0000 0001
X
1
0
0.057
1
1
0
0.343
0000 0000
X
1
0
0.054
1
1
0
0.340
XXXX XXXX
X
0
X
0.000
1
0
X
0.286
XXXX XXXX
X
0
X
0.000
0
0
X
0.000
Pin Assignments
PLCC Package
GND
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
NC
38
9
37
10
36
35
11
TMC3503
34
28
27
26
25
24
29
23
30
17
22
31
16
21
15
20
32
19
33
14
18
13
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
VDD
1
2
3
4
5
6
7
8
9
10
11
12
TMC3503
36
35
34
33
32
31
30
29
28
27
26
25
RREF
VREF
COMP
IOR
IOG
OVDD
VDD
IOB
GND
GND
CLOCK
NC
13
14
15
16
17
18
19
20
21
22
23
24
12
IOR
IOG
IOS
VDD
VDD
VDD
IOB
GND
GND
GND
GND
65-3503-03
65-3503-06
NC
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
NC
39
8
48
47
46
45
44
43
42
41
40
39
38
37
40
41
42
43
1
44
2
3
4
7
B0
B1
B2
B3
B4
B5
B6
B7
WHITE
CLK
SLEEP
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
VDD
5
6
R7
R6
R5
R4
R3
R2
R1
R0
RREF
VREF
COMP
LQFP Package
Notes (LQFP Package Only):
1. Pin functions White and Sleep are not available.
2. IOS function is tied internally to IOG pin.
REV. 1.02 11/24/99
3
TMC3503
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin Number
LQFP
PLCC
Value
Pin Function Description
Clock and Pixel I/O
CLK
26
27
TTL
Clock Input. The clock input is TTL-compatible and all pixel
data is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid reflection
induced jitter, overshoot, and undershoot.
R7-0
G7-0
B7-0
47-40
9-2
23-16
6-1, 44-43
14-7
25-18
TTL
Red, Green, and Blue Pixel Inputs. The R, G, and B digital
inputs are TTL-compatible and registered on the rising edge of
CLK.
SYNC
11
16
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE
(7.62 mA) current source which forms a sync pulse on any D/A
converter output connected to IOS. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during the
blanking interval. If the system does not require sync pulses,
SYNC and IOS should be connected to GND.
BLANK
10
15
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored
and the D/A converter outputs are driven to the blanking level.
BLANK is registered on the rising edge of CLK and has the
same two-pipe latency as SYNC and Data.
WHITE
—
26
TTL
Force Full Scale Input. When WHITE is HIGH, pixel inputs are
ignored and the D/A converter outputs are driven to their fullscale output level. A BLANK input overwrites a WHITE input.
WHITE is register on the rising edge of CLK and has the same
two-pipe latency as SYNC and Data.
SLEEP
—
28
TTL
Power-down Control Input. When HIGH, SLEEP places the D/
A converter in a low-power-dissipation mode. The D/A current
sources and the digital processing are disabled. The last data
loaded into the input and D/A registers is retained. This control is
asynchronous.
33
32
29
39
38
33
0.714 Vp-p
Red, Green, and Blue Data Outputs. The current source
outputs of the D/A converters are capable of driving RS-343A/
SMPTE-170M compatible levels into doubly-terminated 75 Ohm
lines. Sync pulses may be added to any D/A output.
32
37
0.714 Vp-p
SYNC Current Output. When this pin is connected to any of the
D/A converter outputs, a 40 IRE offset is added to the video
level. When the SYNC input is LOW, the current is turned off,
bring the sync tip voltage to 0.0V. If no sync pulse is required,
IOS should be grounded. When SYNC is HIGH, the current
flowing out of IOS is:
Controls
Video Outputs
IOR
IOG
IOB
IOS
(connected
to IOG)
IOS = 3.64 (VREF / RREF)
Voltage Reference
VREF
4
35
41
+1.235 V
Voltage Reference Input/Output. An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt
reference may be applied here which overrides the internal
reference. Decoupling VREF to GND with a 0.1µF ceramic
capacitor is required.
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Pin Descriptions (continued)
Pin Number
Pin
Name
LQFP
PLCC
Value
Pin Function Description
RREF
36
42
590 Ω
Current-setting Resistor. The full-scale output current of each
D/A converter is determined by the value of the resistor
connected between RREF and GND. The nominal value for
RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (amps) from the
D/A converter (without sync). Sync is 0.4 IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total resistive
load (ohms) on each D/A converter. VFS is the blank to full-scale
voltage.
COMP
34
40
0.1 µF
Compensation Capacitor. A 0.1 µF ceramic capacitor must be
connected between COMP and VDD to stabilize internal bias
circuitry.
Power, Ground
VDD
12, 30, 31 17, 34–36
+5 V
Power Supply.
GND
1, 14, 15,
27, 28, 38,
39, 48
29–32
0.0V
Ground.
NC
13, 24, 25,
37
—
—
No Connect
Equivalent Circuits
VDD
VDD
p
Digital
Input
n
p
VDD
n
OUT
GND
GND
27014D
27013B
Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit
REV. 1.02 11/24/99
5
TMC3503
PRODUCT SPECIFICATION
Equivalent Circuits (continued)
VDD
p
p
RREF
VREF
27012B
GND
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
-0.5
7.0
V
-0.5
VDD + 0.5
V
-10.0
10.0
mA
Applied Voltage (measured to GND)2
-0.5
VDD + 0.5
V
Forced Current3,4
-60.0
60.0
mA
infinite
second
110
°C
Junction
150
°C
Lead Soldering (10 seconds)
300
°C
Vapor Phase Soldering (1 minute)
220
°C
150
°C
Power Supply Voltage
VDD (Measured to GND)
Inputs
Applied Voltage (measured to GND)2
Forced
Current3,4
Outputs
Short Circuit Duration (single output in HIGH state to ground)
Temperature
Operating, Ambient
Storage
-20
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Operating Conditions
Parameter
VDD
Power Supply Voltage
fS
Conversion Rate
Min
Nom
Max
4.75
5.0
Units
5.25
V
TMC3503-30
30
Msps
TMC3503-50
50
Msps
TMC3503-80
80
Msps
tPWH
CLK Pulsewidth, HIGH
4
ns
tPWL
CLK Pulsewidth, LOW
4
ns
ts
Input Data Setup Time
3
ns
th
Input Date Hold Time
2
ns
VREF
Reference Voltage, External
CC
Compensation Capacitor
RL
Output Load
VIH
Input Voltage, Logic HIGH
2.0
VDD
V
VIL
Input Voltage, Logic LOW
GND
0.8
V
TA
Ambient Temperature, Still Air
0
70
°C
Max
Units
100
100
125
mA
mA
mA
3
mA
525
525
655
mW
mW
mW
1.0
1.235
1.5
0.1
V
µF
Ω
37.5
Electrical Characteristics
Conditions3
Parameter
IDD
Power Supply
Current2
Power Supply Current,
Sleep Mode
VDD = Max
PD
Total Power Dissipation2
VDD = Max
TMC3503-30
TMC3503-50
TMC3503-80
Output Resistance
CO
Output Capacitance
Typ1
VDD = Max
TMC3503-30
TMC3503-50
TMC3503-80
IDDS
RO
Min
100
kΩ
IOUT = 0mA
30
pF
IIH
Input Current, HIGH
VDD = Max, VIN = 2.4V
-1
µA
IIL
Input Current, LOW
VDD = Max, VIN = 0.4V
1
µA
IREF
VREF Input Bias Current
±100
µA
VREF
Reference Voltage Output
VOC
Output Compliance
CDI
Digital Input Capacitance
0
1.235
Referred to VDD
-0.4
V
0
+1.5
V
4
10
pF
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C
2. Minimum/Maximum values with VDD = Max and TA = Min
3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω
REV. 1.02 11/24/99
7
TMC3503
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions2
VDD = Min
Min
Typ1
Max
10
15
ns
1
2
ns
Units
tD
Clock to Output Delay
tSKEW
Output Skew
tR
Output Risetime
10% to 90% of Full Scale
2
3
ns
tF
Output Falltime
90% to 10% of Full Scale
2
3
ns
tSET
Output Settling Time
to 3%/FS
15
ns
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
System Performance Characteristics
Conditions2
Parameter
Min
Typ1
Max
Units
ELI
Integral Linearity Error
VDD, VREF = Nom
±0.2
±0.3
%/FS
ELD
Differential Linearity Error
VDD, VREF = Nom
±0.2
±0.3
%/FS
EDM
DAC to DAC Matching
VDD, VREF = Nom
3
10
%
EG
Absolute Gain Error
VDD, VREF = Nom
TCEG
Gain Error Tempco
VDD, VREF = Nom
IOFF
Output Off Current
VDD = Max, R, G, B = 000h
SYNC = BLANK = 0
PSRR
Power Supply Rejection
Ratio
TBD
TBD
%/FS
PPM/°C
20
nA
0.05
%/%
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
Timing Diagram
t PWL
1/f S
t PWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
tD
OUTPUT
50%
t SET
tF
tR
10%
65-3503-04
8
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Application Notes
Figure 4 illustrates a typical TMC3503 interface circuit. In
this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage
reference source.
1.
Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG, IOB) as short as possible and as far as
possible from all digital signals. The TMC3503 should
be located near the board edge, close to the analog output connectors.
It is important that the TMC3503 power supply is well-regulated and free of high-frequency noise. Careful power supply
decoupling will ensure the highest quality video signals at
the output of the circuit. The TMC3503 has separate analog
and digital circuits. To keep digital system noise from the
D/A converter, it is recommended that power supply voltages
(VDD) come from the system analog power source and all
ground connections (GND) be made to the analog ground
plane. Power supply pins should be individually decoupled
at the pin.
2.
The power plane for the TMC3503 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the VDD pins. If
the power supply for the TMC3503 is the same as that of
the system's digital circuitry, power to the TMC3503
should be decoupled with 0.1µF and 0.01µF capacitors
and isolated with a ferrite bead.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
Printed Circuit Board Layout
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the TMC3503, the
voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the
TMC3503 and its related analog circuitry can have an
adverse effect on performance.
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Grounding
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following suggestions when doing the layout:
+5V
10µF
0.1µF
VDD
RED PIXEL
INPUT
R7-0
GREEN PIXEL
INPUT
G7-0
BLUE PIXEL
INPUT
B7-0
CLOCK
SYNC
BLANK
WHITE
SLEEP
GND
TMC3503
Red
IO R
IO S
IO G
IO B
ZO=75Ω
75Ω
75Ω
ZO=75Ω
75Ω
Blue
ZO=75Ω
75Ω
75Ω
Triple 8-bit
D/A Converter
+5V
COMP
CLK
SYNC
BLANK
WHITE
SLEEP
75Ω
Green w/Sync
0.1µF
3.3kΩ
590Ω
LM185-1.2
(Optional)
VREF
RREF
0.1µF
65-3503-05
Figure 4. Typical Interface Circuit
REV. 1.02 11/24/99
9
TMC3503
PRODUCT SPECIFICATION
Related Products
•
•
•
•
•
•
•
•
•
•
•
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TMC1275 40 Msps CMOS 8-bit A/D Converter
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10
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Notes:
REV. 1.02 11/24/99
11
TMC3503
PRODUCT SPECIFICATION
Mechanical Dimensions – 44-pin PLCC Package
Inches
Symbol
Min.
A
A1
A2
B
B1
D/E
D1/E1
D3/E3
e
J
ND/NE
N
ccc
Max.
.165
.180
.090
.120
.020
—
.013
.021
.026
.032
.685
.695
.650
.656
.500 BSC
.050 BSC
.042
.056
11
44
—
.004
Millimeters
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Max.
4.19
4.57
2.29
3.05
.51
—
.33
.53
.66
.81
17.40
17.65
16.51
16.66
12.7 BSC
1.27 BSC
1.07
1.42
11
44
—
0.10
2. Corner and edge chamfer (J) = 45°
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
3
2
E
E1
D
J
D1
D3/E3
B1
J
e
A
A1
A2
B
–C–
LEAD COPLANARITY
ccc C
12
REV. 1.02 11/24/99
PRODUCT SPECIFICATION
TMC3503
Mechanical Dimensions – 48-pin LQFP Package
Inches
Symbol
Min.
A
A1
A2
B
D/E
D1/E1
e
L
N
ND
α
ccc
Millimeters
Max.
.055
.063
.001
.005
.053
.057
.006
.010
.346
.362
.268
.284
.019 BSC
.017
.029
48
12
0°
7°
.004
Min.
Notes:
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Max.
1.40
1.60
.05
.15
1.35
1.45
.17
.27
8.8
9.2
6.8
7.2
.50 BSC
.45
.75
48
12
0°
7°
0.08
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
6
4
5
8. To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E E1
C
L
α
0.063" Ref (1.60mm)
See Lead Detail
A
Base Plane
A2
B
A1
Seating Plane
-CLEAD COPLANARITY
ccc
REV. 1.02 11/24/99
C
13
TMC3503
PRODUCT SPECIFICATION
Ordering Information
Product Number
Conversion
Rate (Msps)
Temperature Range
Screening
Package
Package
Marking
TMC3503R2C30
30 Msps
TA = 0˚C to 70˚C
Commercial
44-Lead PLCC
3503R2C30
TMC3503R2C50
50 Msps
TA = 0˚C to 70˚C
Commercial
44-Lead PLCC
3503R2C50
TMC3503R2C80
80 Msps
TA = 0˚C to 70˚C
Commercial
44-Lead PLCC
3503R2C80
TMC3503KRC30
30 Msps
TA = 0˚C to 70˚C
Commercial
48-Lead LQFP
3503KRC30
TMC3503KRC50
50 Msps
TA = 0˚C to 70˚C
Commercial
48-Lead LQFP
3503KRC50
TMC3503KRC80
80 Msps
TA = 0˚C to 70˚C
Commercial
48-Lead LQFP
3503KRC80
11/24/99 0.0m 005
Stock#DS30003503