G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Features : Description : ∗ ∗ ∗ ∗ ∗ The GLT41016 is a 65,536 x 16 bit highperformance CMOS dynamic random access memory. The GLT41016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41016 accepts 256-cycle refresh in 4ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 12ns. The GLT41016 is best suited for graphics, and DSP applications requiring high performance memories. 65,536 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. ∗ 256 refresh cycles per 4ms. ∗ Available in 40-pin 400 mil SOJ and 40/44 pin TSOP (II). ∗ Single 5.0V±10% Power Supply. ∗ All inputs and Outputs are TTL compatible. ∗ Extended Data-Out(EDO) Page Mode operation. HIGH PERFORMANCE 30 35 40 45 Max. RAS Access Time, (tRAC) 30 ns 35 ns 40 ns 45 ns Max. Column Address Access Time, (tAA) 15 ns 18 ns 20 ns 22 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 12 ns 13 ns 15 ns 18 ns Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 75 ns 80 ns Max. CAS Access Time (tCAC) 10 ns 11 ns 12 ns 12 ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -1- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Pin Configuration : GLT41016 SOJ Top View TSOP(Type II) Top View Pin Descriptions: Name A0 - A7 Function RAS Address Inputs Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE DQ0 - DQ15 VCC VSS NC Output Enable Data Inputs / Outputs +5V Power Supply Ground No Connection G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -2- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Absolute Maximum Ratings* Capacitance* TA=25°C, VCC=5V±10%, VSS=0V Operating Temperature, TA (ambient) Max. Parameter Symbol .......................................-0°C to +70°C 5 Address Input Storage Temperature(plastic)....-55°C to +150°C CIN1 Voltage Relative to VSS...............-1.0V to + 7.0V CIN2 7 RAS , LCAS , UCAS , WE , OE Short Circuit Output Current......................50mA 7 Data Input/ Output Power Dissipation......................................1.0W COUT Unit pF pF pF *Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested can adversely affect device reliability. Electrical Specifications l l l CAS means UCAS and LCAS . All voltages are referenced to GND. After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -3- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Extended Data Output (EDO) Page Mode The EDO page mode is a kind of page mode with enhanced features. The two major features of the EDO page mode are as follows. 1. Data output time is extended. In the EDO page mode, the output data is held to the next CAS cycle‘s falling edge, instead of the rising edge. For this reason, valid data output time in the EDO page mode is extended compared with the fast page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the EDO page mode, the timing margin in read cycle is larger than of the fast page mode even if the CAS cycle time becomes shorter. 2. The CAS cycle time in the EDO page mode is shorter than that in the fast page mode. In the EDO page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. Taking a device whose tRAC is 60ns as an example, the CAS cycle time in the EDO page mode is 25ns while that in the fast page mode is 40ns. In the EDO page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The EDO page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -4- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Truth Table: GLT41016 Function Standby RAS H CASL CASH H→X H→X WE X OE X ADDRESS DQs Notes High-Z Read: Word L L L H L ROW/COL Data Out Read: Lower Byte L L H H L Read: Upper Byte L H L H L Write: Word(Early Write) L L L L X ROW/COL Lower Byte,DataOut Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,DataOut ROW/COL Data-In Write: Lower Byte (Early) L L H L X Write: Upper Byte (Early) L H L L X Read Write L L L H→L L→H ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In EDO-Page- 1st Cycle L H→L H→L H L ROW/COL Data-Out Mode Read 2nd Cycle L H→L H→L H L EDO-Page- 1st Cycle L H→L H→L L X Mode Write 2nd Cycle L H→L H→L L X EDO-Page- 1st Cycle L H→L H→L H→L L→H 2nd Cycle L H→L H→L H→L L→H Read L→H→L L L H L ROW/COL Data-Out Write L→H→L L L L L X ROW/COL Data-In H H X X H→L L L X X COL Data-Out ROW/COL Data-In COL Data-In ROW/COL Data-Out,Data-In 1,2 1 1 2 2 1,2 Mode ReadWrite Hidden Refresh RAS -Only Refresh CBR Refresh COL ROW Data-Out,Data-In 1 2,3 High-Z High-Z Notes: 1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ). G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -5- 1,2 4 G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified. Sym . Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE ICC1 ICC2 Standby Current,(TTL) ICC3 Refresh Current, RAS -Only ICC4 Operating Current, EDO Page Mode Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) CAS Before RAS Min. LCAS at VIH tRC = tRC (min.) RAS at VIL, RAS , UCAS , LCAS address cycling: tRC = tRC (min.) Max. Unit Notes +10 µA -10 +10 µA 180 170 160 150 RAS , UCAS , LCAS at VIH other inputs ≥VSS RAS cycling, UCAS , Typ -10 tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRC = tRC (min.) UCAS , LCAS address cycling: tPC = tPC(min.) ICC5 Refresh Current, Access Time 4 tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns 180 170 160 150 180 170 160 150 180 170 160 150 ICC6 Standby Current, (CMOS) RAS ≥VCC-0.2V, UCAS ≥VCC-0.2V, mA 1,2 mA mA 2 mA 1,2 mA 1 2 mA +0.8 VCC+1 0.4 V V V V LCAS ≥VCC-0.2V, All other inputs VSS VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5mA 2.4 3 3 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -6- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) AC Characteristics TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V An initial pause of 100 µs and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 30 35 40 45 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Read or Write Cycle Time tRC 65 70 75 80 ns Read Modify Write Cycle Time tRWC 90 95 100 103 ns RAS Precharge Time tRP 25 25 25 30 ns RAS Pulse Width tRAS 30 100k 35 100k 40 100k 45 100k ns Access Time from RAS tRAC 30 35 40 45 ns 1,2,3 tCAC 10 11 12 12 ns 1,5,10 tAA 15 18 20 22 ns 1,5,6 Access Time from CAS Access Time from Column Address CAS to Output Low-Z tCLZ 0 CAS to Output High-Z tCEZ 3 RAS Hold Time tRSH 10 12 12 13 ns RAS Hold Time Referenced to OE tROH 7 8 8 9 ns CAS Hold Time tCSH 25 30 34 40 ns CAS Pulse Width tCAS 6 10k 6 10k 6 10K 7 10K ns RAS to CAS Delay Time tRCD 13 20 17 24 18 28 18 33 ns RAS to Column Address Delay Time tRAD 10 15 12 17 13 20 13 23 ns tCRP 5 5 5 5 ns tASR 0 0 0 0 ns Row Address Hold Time tRAH 6 7 8 8 ns Column Address Set-Up Time tASC 0 0 0 0 ns Column Address Hold Time tCAH 6 6 6 6 ns tRAL 15 18 20 23 ns CAS to RAS Precharge Time Row Address Set-Up Time Column Address to RAS Lead Time Column Address Hold Time Referenced to 0 8 3 0 8 3 0 8 3 ns 8 ns 7 tAR 26 30 34 39 ns RAS Read Command Set-Up Time tRCS 0 0 0 0 ns Read Command Hold Time Referenced to CAS tRCH 0 0 0 0 ns 4 Read Command Hold Time Referenced to RAS RRH Write Command Set-Up Time tWCS t 0 0 0 0 ns 4 0 0 0 0 ns 8,9 Write Command Hold Time tWCH 6 6 6 6 ns Write Command Pulse Width tWP 6 6 6 6 ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -7- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) AC Characteristics 30 35 40 45 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Write Command to RAS Lead Time tRWL 10 11 12 12 ns tCWL 10 11 12 12 ns Write Command to CAS Lead Time Data Set-Up Time tDS 0 0 0 0 ns Data Hold Time tDH 6 7 8 8 ns Data Hold Time Referenced to RAS tDHR 26 31 36 41 ns RAS to WE Delay Time tRWD 44 49 54 59 ns tCWD 22 23 24 24 ns tAWD 25 30 32 34 ns tRPC 0 0 0 0 ns CAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Precharge Time Access Time from CAS Precharge EDO Page Mode Cycle Time tCPA tPC EDO Page Mode Read-Modify-Write Cycle Time tPRWC 17 20 22 24 ns 12 13 15 18 ns 43 47 50 52 ns 5 5 7 ns CAS Precharge Time (EDO Page Mode) tCP 5 RAS Pulse Width (EDO Page Mode Only) tRASP 30 100k 35 100k 40 100k 45 100k ns Access Time from OE tOEA OE to Data Delay Time tOED 8 OE to Output High-Z tOEZ 3 OE Command Hold Time tOEH 6 6 7 7 ns Data Output Hold after CAS low tDOH 3 3 3 5 ns RAS to Output High-Z tREZ 3 8 3 8 3 8 3 8 ns WE to Output High-Z tWEZ 3 10 3 10 3 10 3 10 ns OE to CAS Hold Time tOCH 8 8 8 8 ns CAS Hold Time to OE tCHO 8 8 8 8 ns OE Precharge Time tOEP 8 8 8 8 ns CAS Set-Up Time for CAS -before- RAS Cycle tCSR 10 10 10 10 ns tCHR 10 10 10 10 ns tT 1.5 CAS Hold Time for CAS -before- RAS Cycle Transition Time Refresh Period 10 tREF 11 8 8 50 4 3 2 12 8 8 50 4 3 2 12 8 8 50 4 3 2 ns ns 8 ns 50 ns 4 ms G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -8- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Notes: 1. Measure with a load equivalent to two TTL inputs and 50 pF. 2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tAA, tCAC and tCPA. 6. Assumes that tRAD ≥ tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE . 11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -9- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Read CYCLE Note : DIN = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 10 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Early Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 11 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) OE Controlled Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 12 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Read - Modify - Write Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 13 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Read Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 14 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 15 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 16 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) CAS - Before - RAS Refresh Cycle RAS-Only Refresh Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 17 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Hidden Refresh Cycle ( Read ) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 18 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 19 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) CAS -Before- RAS Refresh Counter Test Cycle Read Cycle Write Cycle Read-Modify-Write Ordering Information G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 20 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Part Number GLT41016-30J4 GLT41016-35J4 GLT41016-40J4 GLT41016-45J4 GLT41016-30TC GLT41016-35TC GLT41016-40TC GLT41016-45TC SPEED 30ns 35ns 40ns 45ns 30ns 35ns 40ns 45ns POWER Normal Normal Normal Normal Normal Normal Normal Normal FEATURE EDO EDO EDO EDO EDO EDO EDO EDO PACKAGE SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L Parts Numbers (Top Mark) Definition : GLT 4 10 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note 16 - 40 J4 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 21 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Package Information 400mil 40 pin Small Outline J-form Package (SOJ) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 22 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) 40/44 Lead Thin Small Outline Package TSOP(Type II) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 23 -