GLT41116 64k x 16 CMOS Dynamic RAM with Fast Page Mode FEATURES ◆ 65,536 words by 16 bits organization. ◆ Fast access time and cycle time. ◆ Dual CAS input. ◆ Low power dissipation. ◆ Read-Modify-Write, RAS-Only Refresh, CAS-before-RAS Refresh, Hidden Refresh and Test Mode Capability. ◆ 256 refresh cycles per 4ms. ◆ Available in 40-Pin 400 mil SOJ, and 40/44-Pin TSOP (Type II). ◆ Single 5.0V± 10% Power Supply. ◆ All inputs and Outputs are TTL compatible. ◆ Fast Page Mode operation. GENERAL DESCRIPTION The GLT41116 is a 65,536 x 16 bit high-performance CMOS dynamic random access memory. The GLT41116 offers Fast Page mode, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41116 has symmetric address and accepts 256-cycle refresh in 4ms interval. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256x16 bits, within a page, with cycle times as short as 18ns. The GLT41116 is best suited for graphics, and DSP applications requiring high performance memories. July 1998 (Rev. 1) 1 GLT41116 FUNCTIONAL BLOCK DIAGRAM Column Decoder ••• 256 ••• Sense Amplifier Row Address Buffer X[7:0] A[7:0] x8 x8 Data Input Buffer x8 x8 Data Output Buffer x8 x8 Data Input Buffer x8 DQ[7:0] Memory Array 256 x 256 x 16 DQ[15:8] VCC GND CAS-before-RAS Counter RAS LCAS UCAS WE Clock Generator Lower Byte Control Upper Byte Control OE Figure 1. GLT41116 64 x 16 CMOS Signal Descriptions Symbol Type A0 - A7 Input Address Inputs RAS Input Row address strobe UCAS Input Column address strobe/upper byte control Description LCAS Input Column address strobe/lower byte control WE Input Write enable OE Input Output enable DQ[15:0] Input Data inputs/outputs VCC Input +5V power supply VSS Input Ground NC Input No connection 2 Data Output Buffer x 16 ••• 256 x 16 ••• ••• 256 ••• Y[7:0] Row Decoder Column Address Buffer x8 G-LINK Technology July 1998 (Rev. 1) GLT41116 Truth Table Function Address RAS CASL CASH WE OE DQ Notes H H→X H→X X X High-Z Read: Word Row/Col L L L H l Data Out Read: Lower Byte Row/Col L L H H L Lower Byte, Data-Out Upper Byte, High-Z Read: Upper Byte Row/Col L H L H L Lower Byte, High-Z Upper Byte, Data Out Write: Word (Early Write) Row/Col L L L L X Data-In Write: Lower Byte (Early) Row/Col L L H L X Lower Byte, Data-In Upper Byte, High-Z Write: Upper Byte (Early) Row/Col L H L L X Lower Byte, High-Z Upper Byte, Data-In Read Write Row/Col L L L H→L L→H Data-Out, Data-In 1st Cycle Row/Col L H→L H→L H L Data-Out [1] 2nd Cycle Col L H→L H→L L X Data-Out [1] 1st Cycle Row/Col L H→L H→L L X Data-In [2] 2nd Cycle Col L H→L H→L L X Data-In [2] 1st Cycle Row/Col L H→L H→L H→L L→H Data-Out, Data-In [1] [2] 2nd Cycle Col L H→L H→L H→L L→H Data-Out, Data-In [1] [2] Read Row/Col L→H→L L L H L Data-Out Write Row/Col L→H→L L L L X Data-In L H H X X High-Z H→L L L X X High-Z Stand By Fast-Page Mode Read Fast-Page Mode Write Fast-Page Mode Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh 1. 2. 3. 4. Row [1] [2] [1] [2] [3] [4] These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). EARLY WRITE Only. At least one of the two CAS signals must be active (UCAS or LCAS). G-LINK Technology July 1998 (Rev. 1) 3 GLT41116 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Parameter Rating -0°C to +70°C Operating Temperature, TA (ambient) -55°C to +125°C Storage Temperature (plastic) Voltage Relative to VSS -1.0V to +7.0V Short Circuit Output Current‘ 50 mA Power Dissipitation 1.0 W 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance [1] Symbol Parameter Max Units CIN1 Address Input 5 pF CIN2 RAS, LCAS, UCAS, WE, OE 7 pF COUT Data Input/Output 7 pF 1. Capacitance is sampled and not 100% tested DC Characteristics (TA = 0°C to 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise specified) -30 Symbol Parameter Conditions -35 -40 -45 Min Max Min Max Min Max Min Max Units -10 +10 -10 +10 -10 +10 -10 +10 µA +10 +10 µA 170 160 150 mA 2 2 2 2 mA RAS cycling, UCAS, LCAS at VIH tRC = tRC (min.) 180 170 160 150 mA [2] Operating Current, EDO Page Mode RAS at VIL, UCAS, LCAS address cycling: tPC = tPC (min.) 180 170 160 150 mA [1] [2] ICC5 Refresh Current, CASbefore-RAS RAS, UCAS, LCAS address cycling: tRC = tRC (min.) 180 170 160 150 mA [1] ICC6 Standby Current, (CMOS) RAS ≥ VCC -0.2V, UCS ≥ VCC -0.2V, LCAS ≥ VCC -0.2V, All other inputs ≥ VCC 2 2 2 2 mA VIL Input Low Voltage ILI Input Leakage Current (any input pin) 0V ≤ VIN ≤ 5.5V (All other pins not under test = 0V) ILO Output Leakage Current (for High-Z State) 0V ≤ VOUT ≤ 5.5V Output is disabled (Hiz) +10 +10 ICC1 Operating Current, Random READ/WRITE tRC = tRC (min.) 180 ICC2 Standby Current, (TTL) RAS, UCAS, LCAS at VIH other inputs ≥ VSS ICC3 Refresh Current, RASOnly ICC4 VIH Input High Voltage VOL Output Low Voltage IOL = 4.2 mA VOH Output High Voltage IOH = -5 mA -1 +0.8 -1 +0.8 -1 +0.8 -1 +0.8 V 2.4 VCC +1 2.4 VCC +1 2.4 VCC +1 2.4 VCC +1 V 0.4 V 0.4 2.4 0.4 2.4 0.4 2.4 2.4 Notes [1] [2] [3] V 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC (max) is measured with a maximum of one transition per address cycle in random READ/WRITE and Fast-Page Mode. 3. Specified VIL (min) is steady state operation. During transitions VIL (min) may undershoot to -1.0V for a period not to exceed 20 ns. All AC parameter are measured with VIL (min) ≥ VSS and VIH (max) ≤ VCC. 4 G-LINK Technology July 1998 (Rev. 1) GLT41116 AC Characteristics (0 °C ≤ TA ≤ 70 °C, VCC = 5.0V ± 10%) [1] -30 Parameter -35 -40 -45 Min Max Min Max Min Max Min Max Units tRC 65 – 70 – 75 – 80 – ns Read Modify Write Cycle Time tRWC 80 – 99 – 105 – 110 – ns Access Time for RAS tRAC – 30 – 35 – 40 – 45 ns [3] [4] Access Time for CAS tCAC – 10 11 – 12 – – 12 ns [3] [4] Access TIme from Column Address tAA – 15 – 18 – 20 – 22 ns [3] [4] CAS to output ion Low-Z tCLZ 0 – 0 – 0 – 0 – ns [3] Read/Write Cycle Time Symbol [2] Notes Output buffer turn-off delay from CAS tOFF 3 8 3 8 3 8 3 8 ns [5] Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 ns [2] RAS Precharge Time tRP 25 – 25 – 25 – 25 – ns RAS Pulse Width tRAS 30 100k 35 100k 40 100k 45 100k ns RAS Hold Time tRSH 10 – 12 – 12 – 13 – ns CAS Hold Time tCSH 30 – 36 – 40 – 46 – ns CAS Pulse Width tCAS 10 10k 12 10k 12 10k 13 10k ns RAS to CAS Delay Time tRCD 13 20 17 24 18 28 18 33 ns [4] RAS to Column Address Delay Time tRAD 10 15 12 17 13 20 12 23 ns [4] CAS To RAS Precharge Time tCPRP 5 – 5 – 5 – 5 – ns [6] Row Address Setup TIme tASR 0 – 0 – 0 – 0 – ns Row Address Hold Time tRAH 6 – 6 – 6 – 6 – ns Column Address Setup Time tASC 26 – 30 – 34 – 39 – ns Column Address Hold Time tCAH 15 – 18 – 20 – 23 – ns Column Address Hold Time Referenced to RAS tAR 26 – 30 – 34 – 39 – ns Column Address Lead Time Referenced to RAS tRAL 15 – 18 – 20 – 23 – ns Read Command Setup Time tRCS 0 – 0 – 0 – 0 – ns Read Command Hold Time Referenced to RAS tRRH 0 – 0 – 0 – 0 – ns [7] Read Command Hold Time Referenced to CAS tRCH 0 – 0 – 0 – 0 – ns [7] WE Hold Time Referenced to CAS tWCH 6 – 6 – 6 – 6 – ns [8] Write Command Hold time Referenced to RAS tWCR 26 – 30 – 34 – 39 – ns [9] WE Pulse Width tWP 6 – 6 – 6 – 6 – ns [8] WE Lead Time Referenced to RAS tRWL 10 – 11 – 12 – 12 – ns WE Lead Time Referenced to CAS tCWL 10 – 11 – 12 – 12 – ns Data-In Setup Time tDS 0 – 0 – 0 – 0 – ns Data-In Hold Time tDH 7 – 6 – 8 – 8 – ns [10] [10] Data Hold Time Referenced to RAS tDHR 27 – 31 – 36 – 41 – ns [11] WE Setup Time tWCS 0 – 0 – 0 – 0 – ns [9] RAS to WE Delay Time tRWD 47 – 58 – 63 – 68 – ns [9] CAS to WE Delay Time tCWD 24 – 29 – 30 – 30 – ns [9] Column Address to WE Delay Time tAWD 29 – 36 – 38 – 40 – ns [9] CAS Setup TIme (CAS Before RAS Refresh) tCSR 5 – 5 – 5 – 5 – ns CAS Hold Time (CAS Before RAS Refresh) tCHR 10 – 10 – 10 – 10 – ns RAS to CAS Precharge Time tRPC 5 – 5 – 5 – 5 – ns CAS Precharge Time (CBR Counter Test Cycle) tCPT 20 – 20 – 20 – 20 – ns Access Time From CAS Precharge tCPA – 18 – 21 – 23 – 25 ns Fast Page Mode Read/Write Cycle Time tPC 18 – 21 – 23 – 25 – ns G-LINK Technology July 1998 (Rev. 1) [3] 5 GLT41116 AC Characteristics (0 °C ≤ TA ≤ 70 °C, VCC = 5.0V ± 10%) [1] -30 Parameter Symbol Min [2] -35 Max Min -40 Max Min -45 Max Min Max Units Fast Page Mode Read Modify Write Cycle Time tPRWC 48 – 60 – 53 – 65 – ns CAS Precharge Time (Fast Page Mode) tCP 6 – 6 – 7 – 7 – ns RAS Pulse Width (Fast PAge Mode) tRASP 30 100k 35 100k 40 100k 45 100k ns RAS Hold Time From CAS Precharge tRHCP 25 – 25 – 25 – 30 – ns Access Time From OE tOEA – 10 – 11 – 12 – 12 ns OE to Delay Time tOED 8 – 8 – 8 – 8 – ns Output Buffer Turn-off Delay Time From OE tOEZ 3 – 3 8 3 8 3 8 ns OE Hold Time tOEH 6 – 6 – 7 – 7 – ns WE Hold Time (Hidden Refresh Cycle) tWHR 15 – 15 – 15 – 15 Refresh Time (256 Cycles) tREF – 4 – 4 – 4 – 4 ms Notes [5] ns 1. An initial pause of 100 µs is required after power-up followed by any 8 RAS only Refresh or CAS before RAS Refresh Cycles to initialize the internal circuit. 2. VIH (min) and VIL (min) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max), AC measurements assume tT = 3 ns. 3. Measured with an equivalent to 2 TTL loads and 100 pF. 4. For read cycles, the access time is defined as follows: Input Conditions tRAD ≤ tRAD (max.) and tRCD ≤ tRCD (max.) Access Time tRAC (Max.) tRAD (max.) < tRAD and tRCD ≤ tRCD (max.) tAA (Max.) tRCD (max). < tRCD tCAC (Max.) tRAD (max.) and tRCD (max.) indicate the points which the access time changes and are not the limits of operation. tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to VOH or VOL. tCRP (min.) requirement should be applicable for RAS, CAS cycle preceded by any cycles. Either tRCH (min.) or tRRH (min) must be satisfied for a read cycle. tWP (min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH (min.) should be satisfied. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS ≥ tWCS (min.), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD (min.), tRWD ≥ tRWD (min.) and tAWD ≥ tAWD (min.), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 10. This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write orr read modify write cycles. 11. tAR, tWCR, and tDHR are referenced to tRAD(max.). 5. 6. 7. 8. 9. 6 G-LINK Technology July 1998 (Rev. 1) GLT41116 1 2 3 4 5 6 7 8 9 A5 A6 10 tKHKH CLK tKHKL tEVKH tKHEX tCVKH tKHCX tKLKH CKE CE ADV/LD R/W BWn tAVKH ADDRESS tKHAX A1 A2 A3 A4 tKHQV tDVKH D/Q tKHDX D (A1) tKHQX1 D (A2) D (A2+1) tGLQV tKHQX Q (A3) Q (A4) tGHQZ A7 tKHQZ Q (A4+1) tGLQX D (A5) D (A6) D (A7) tKHQX OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A1+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT Don’t Care NOTE: 1. For this waveform, ZZ is tied LOW. 2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. Undefined Figure 2. Read/Write Timing G-LINK Technology July 1998 (Rev. 1) 7 GLT41116 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CKE CE ADV/LD R/Wn BWn ADDRESS A5 tKHQZ tKHQX D/Q D (A1) WRITE D(A1) READ Q(A2) STALL READ Q(A1) Q (A2) WRITE D(A2) Q (A3) STALL D (A4) NOP READ Q(A3) D (A5) DESELECT Don’t Care NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE being used to create a “pause.” A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. Figure 3. NOP, STALL and DESELECT Timing 8 G-LINK Technology July 1998 (Rev. 1) Continue DESELECT Undefined GLT41116 PACKAGING INFORMATION VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Top View 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS Figure 4. 40-Pin 400 mil Plastic SOJ Pin Assignment VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS Top View NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 Figure 5. 44/40-Pin 400 mil TSOP (TypeII) Pin Assignment G-LINK Technology July 1998 (Rev. 1) 9 GLT41116 SEATING PLANE 0.95 TYP 40 20 21 26.03 ± 0.13 1 10.16 ± 0.13 1.27 0.81 MAX. +0.07 0.43 -0.05 11.17 ± 0.13 3.6 ± 0.25 2.35 TYP 0.65 MIN. 9.3 ± 0.25 Dimensions in millimeters +0.07 0.2 -0.05 Figure 6. 40-Pin 400 mil SOJ Package Dimensions 10 G-LINK Technology July 1998 (Rev. 1) 0.18 M GLT41116 18.41 ± 0.1 A 44 10.76 ± 0.2 11.76 ± 0.2 10.1 ± 0.1 23 1 0.81 TYP 0.05 ~ 0.25 0.95 ± 0.05 22 0.37 +0.08 -0.07 0.16 M 0.17 ± 0.05 0.8 0.5 ± 0.1 0.8± 0.2 1.2 MAX Detail A SEATING PLANE Dimensions in Inches (millimeters) Figure 7. 40/44-Pin TSOP (Type II) Package Dimensions G-LINK Technology July 1998 (Rev. 1) 11 GLT41116 ORDERING INFO Speed Power Feature GLT4116-30J4 Part Number 30 ns Normal FPM 40-Pin 400 mil SOJ GLT4116-35J4 35 ns Normal FPM 40-Pin 400 mil SOJ GLT4116-40J4 40 ns Normal FPM 40-Pin 400 mil SOJ GLT4116-45J4 45 ns Normal FPM 40-Pin 400 mil SOJ GLT4116-30TC 30 ns Normal FPM 44-Pin 400 mil TSOP GLT4116-35TC 35 ns Normal FPM 44-Pin 400 mil TSOP GLT4116-40TC 40 ns Normal FPM 44-Pin 400 mil TSOP GLT4116-45TC 45 ns Normal FPM 44-Pin 400 mil TSOP 12 G-LINK Technology July 1998 (Rev. 1) Package GLT41116 Notes: G-LINK Technology July 1998 (Rev. 1) 13 GLT41116 Notes: 14 G-LINK Technology July 1998 (Rev. 1) GLT41116 Notes: G-LINK Technology July 1998 (Rev. 1) 15 GLT41116 www.glinktech.com G-LINK Technology 1753 South Main Street Milpitas, California, 95035, USA TEL: 408-240-1380 • FAX: 408-240-1385 G-LINK Technology Corporation, Taiwan 6F, No. 24-2, Industry E. Rd. IV Science-Based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: 03-578-2833 • FAX: 03-578-5820 © 2001 G-LINK Technology All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology. Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given. G-LINK Technology reserves the right to change products or specifications without notice. The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for G-LINK applications assistance, customer’s product design, or infringement of patents arising from use of semiconductor devices in such systems’ designs. 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