ETC GLT625608

G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Features :
Description :
GLT625608 is a 262,144-bit static random access
∗ Available in 70/100ns(MAX.)
∗ Automatic power-down when chip disabled memory organized as 32,768 words by 8 bits and
operates from a single 5 volt supply. Inputs and
∗ Low power consumption:
∗
∗
∗
∗
∗
∗
∗
∗
GLT625608
-467.5mW(Max.) Operating
-500µW(Max.)Standby
TTL compatible interface levels
Single 5V power supply
Fully static operation
Three state outputs
256K bit EPROM pin compatible
Data Retention as low as 2V
Industrial Grade (-40°C~85°C) available.
Pin Configurations:
GLT625608
three-state outputs are TTL compatible and allow for
direct interfacing with system I/O bus. The
GLT625608 is available in a standard 330 mil SOP
packages. Other packages will also available upon
request.
Function Block Diagram :
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-1-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Pin Descriptions:
Name
Function
A0 - A14
Address Inputs
Write Enable
Output Enable
Chip Enable
Data Input/Output
Power Supply (+5V)
Ground
WE
OE
CE
I/O0-I/O7
Vcc
GND
Truth Table:
Mode
Not Selected
( Power down )
Output Disabled
Read
Write
WE
CE
OE
I/O Operation
Supply Current
X
H
X
H
H
L
L
L
L
H
L
X
High Z
High Z
High Z
DOUT
DIN
ISB,ISB1
ISB,ISB1
ICC
ICC
ICC
NOTE: X : H or L
Absolute Maximum Ratings:
Operation Range :
RANGE
Ambient Temperature
Under Bias...................................-10°C to +80°C
Storage Temperature(plastic)....-55°C to +125°C
Voltage Relative to GND.............-0.5V to + 7.0V
Data Output Current..................................50mA
Power Dissipation......................................1.0W
1.Stresses greater than those listed under ABSOLUTE
MAXIMUM RATING may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Commercial
Industrial
AMBIENT
TEMPERATURE
0°C to + 70°C
-40°C to 85°C
Vcc
5V ± 10%
5V ± 10%
Capaccitance(1)(TA=25°°C,F=1.0MHZ )
SYMBOL
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
capacitance
CONDIT
IONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0
8
pF
1.This parameter is guaranteed and tested.
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-2-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
DC Characteristics
Sym.
Parameter
VIL
VIH
ILI
ILO
VOL
VOH
ICC
Test Conditions
Guaranteed Input Low
Voltage (2)(3)
Guaranteed Input High
Voltage (2)
Input Leakage Current
VCC=Max., VIN=0V to VCC
Output Leakage Current V =Max., CE ≥V
CC
IH
Output Low Voltage
VCC=Min.,IOL =8mA
Output High Voltage
VCC=Min., IOH =-4mA
Operating Power Supply V =Max., CE ≤V ,
CC
IL
Current
I =0mA., F=F (3)
I/O
ICCSB Standby Power Supply
Current
Min. Typ(1)
Max.
Unit
-0.3
-
+0.8
V
2.2
-
VCC+0.3
V
-5
-5
-
5
5
µA
µA
2.4
-
-
0.4
100
V
V
mA
max
-
VCC=Max., CE ≥VIH,
II/O=0mA., F=Fmax(3)
-
20
mA
ICCSB1 Power Down Power
Supply Current
10
10
mA
VCC=Max., CE ≥VCC.-0.2V,
VIN≥VCC. -0.2V or
1. Typical characteristics are at VCC=5V, TA=25°C.
2. These are absolute values with repeat to device ground and all overshoots due to system or
tester noise are included.
3. FMAX=1/tRC.
Data Retention
Sym.
VDR
ICCDR
tCDR
tR
Parameter
Test Conditions
VCC for Data retention CE ≥ V -0.2V
CC
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
Data Retention
CE ≥ V - 0.2V
DR
Current
VIN ≥ VDR - 0.2V or VIN ≤ 0.2V
Chip Deselect to Data
Retention Time
See Retention Waveform
Operating Recovery
Time
Min. Typ Max. Unit
2.0
-
-
V
-
2
50
µA(1)
)
0
-
-
ns
tRC(2)
-
-
ns
1. VDR = 3V, TA = Specified
2. tRC = Read Cycle Time
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-3-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Low VCC Data Retention Waveform ( CE Controlled )
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
0V to 3.0V
3ns
1.5V
AC Test Loads and Waveforms
Ω
Ω
Ω
Ω
Ω
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-4-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
AC Electrical Characteristics
Read Cycle
JEDEC
Parameter
Name
Parameter
Name
625608-70
tAVAX
tAVQV
tELQV
tGLQV
tELQZ
tGLQX
tEHQZ
tGHQZ
tAXQX
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Deselect to Output in Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
625608-10
Min.
Max.
Min.
Max.
Unit
70
5
5
0
0
5
70
70
40
30
30
-
100
10
5
0
0
10
100
100
50
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-5-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Switching Waveforms (Read Cycle)
READ CYCLE 1(1,2,4)
READ CYCLE 2(1,3,4)
READ CYCLE 3(1)
Notes:
1. WE is High for READ Cycle.
2. Device is continuously selected OE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. CE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1b. This parameter is
guaranteed but not 100% tested.
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-6-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
AC Electrical Characteristics
Write Cycle
JEDEC
Parameter
Name
tAVAX
tELWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
625608-70
Parameter
Name
tWC
tCW
tAS
tAW
tWP
tWR1
tWHZ
tDW
tDH
tOHZ
tOW
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
625608-10
Min.
Max.
Min.
Max.
Unit
70
65
0
65
55
5
0
35
0
0
5
30
30
-
100
90
0
90
75
5
0
40
0
0
5
35
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms (Write Cycle)
WRITE CYCLE 1(1)
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-7-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
WRITE CYCLE 2(1,6)
Note:
1.
WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE active and WE low. All
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, outputs remain in a high impedance state.
6. OE is continuously low ( OE =VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low is high during this period, I/O pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ±200mV from steady state with CL=5pF.
11. tCW is measured from CE going low to the end of write.
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-8-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Ordering Information
Part Number
SPEED
POWER
PACKAGE
GLT625608-10J3
GLT625608-70J3
GLT625608-10TS
GLT625608-70TS
GLT625608-10TC
GLT625608-70TC
GLT625608-10FB
GLT625608-70FB
10ns
70ns
10ns
70ns
10ns
70ns
10ns
70ns
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
SOJ 300mil 28L
SOJ 300mil 28L
TSOPI 28L
TSOPI 28L
TSOPII 28L
TSOPII 28L
SOP 330mil 28L
SOP 330mil 28L
Parts Numbers (Top Mark) Definition :
GLT 6 256
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
08
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
I - 10 TC
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
-9-
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
Package Information
300mil 28 Lead Small Outline J-form Package (SOJ)
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
- 10 -
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
28 L (8 × 13.4 mm ) Thin Small Outline Package (TSOP) Type I
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
- 11 -
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
28 L (8 × 20 mm ) Thin Small Outline Package (TSOP) Type I
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
- 12 -
G -LINK
GLT625608
32K x 8 SLOW SPEED CMOS STATIC RAM
Feb, 2001(Rev. 1.1)
330mil 28 Lead Thin Small Outline(Gull-Wing) Package (SOP)
G-Link Technology Corporation
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F,No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Tawian.
- 13 -