UTRON Rev. 1.3 UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY REVISION DESCRIPTION Preliminary Rev. 0.5 Original. Rev.1.0 1.Separate Industrial and Commercial SPEC. 2.New waveforms. 3.Add access time 55ns range. 4.The symbols CE1# and OE# and WE# are revised as. CE1 and OE and WE . Rev.1.1 1.Revised access time 55/70/100ns -Rev 1.0: 55ns(max) for Vcc=3.0V~3.6V 70/100 ns(max) for Vcc=2.7V~3.6V 2.Revised “SYMBOL” : CE1 CE 3.Revised ABSOLUTE MAXIMUM RATINGS - VTERM : -0.3 to 4.6 -0.5 to 4.6V - PD : 1.0~1.5 1W - IOUT : 50 20mA 4.Revised DC CHARACTERISTICS - VIH : 2.0 2.2V 5.Revised AC CHARACTERISTICS - tOH & tBLZ : 5 10ns 6.Revised 48-pin TFBGA package outline dimension： -ball diameter : 0.3mm 0.35mm Rev.1.2 1. Revised Standby current (LL-Version) : 3uA(typ) 2uA(typ) 2. Revised operating current (Iccmax) : 45/35/25mA 40/30/25mA 3. Revised DC CHARACTERISTICS : a. Operating Power Supply Current (Icc) 55ns (max) : 45 40mA 70ns (typ) : 25 20mA, 70ns (max) : 35 30mA 100ns (Typ) : 20 16mA b. Standby current(CMOS) : LL-version (typ) : 3 2uA, 25 20uA Rev.1.3 1. Revised VOH(Typ) : NA 2.7V 2. Add VIH(max)=VCC+2.0V for pulse width less than 10ns. VIL(min)=VSS-2.0V for pulse width less than 10ns. 3. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Draft Date Mar, 2001 Aug 7,2001 Nov 8 ,2002 Dec 3,2002 May 6,2003 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 FEATURES GENERAL DESCRIPTION Fast access time : 55/70/100ns CMOS low power operating Operating current : 40/30/25 (Icc,max.) Standby current : 20uA (TYP.) L-version 2uA (TYP.) LL-version Single 2.7V~3.6V power supply Operation temperature: Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage:1.5V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 48-pin 6mm × 8mm TFBGA The UT62L25716(I) is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. The UT62L25716(I) operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L25716(I) is designed for low power system applications. It is particularly well suited for use in high-density low power system applications. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K X 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE2 CE OE WE CONTROL CIRCUIT LB UB UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS Rev. 1.3 SRAM PIN DESCRIPTION PIN CONFIGURATION A LB OE A0 A1 A2 CE2 I/O9 UB A3 A4 CE I/O1 I/O10 I/O11 A5 A6 I/O2 I/O3 Vss I/O12 A17 A7 I/O4 Vcc Vcc I/O13 NC A16 I/O5 Vss I/O15 I/O14 A14 A15 I/O6 I/O7 I/O16 NC A12 A13 WE I/O8 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 B C D E F G H SYMBOL A0 - A17 I/O1 - I/O16 CE , CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input WE OE Write Enable Input LB UB VCC VSS NC Lower-byte Control Output Enable Input Upper-byte Control Power Supply Ground No Connection TFBGA TRUTH TABLE MODE CE CE2 OE H X X X L X X X X L H H Output Disable L H H L H L Read L H L L H L L H X Write L H X L H X Note: H = VIH, L=VIL, X = Don't care. Standby WE LB UB X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT DOUT High – Z DOUT DOUT DIN High – Z DIN High – Z DIN DIN SUPPLY CURRENT ISB, ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Vcc = 2.7V~3.6V, TA = -40℃ to 85℃(I)) PARAMETER SYMBOL TEST CONDITION Power Voltage VCC ＊1 Input High Voltage VIH ＊2 Input Low Voltage VIL Input Leakage Current ILI VSS ≦VIN ≦VCC Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disable Output High Voltage VOH IOH= -1mA Output Low Voltage VOL IOL= 2.1mA Cycle time=min, 100%duty Operating Power ICC I/O=0mA, CE =VIL Supply Current Average Operation Current ICC1 100%duty,II/O=0mA, CE ≦0.2V, other pins at 0.2V or Vcc-0.2V ICC2 Standby Current (TTL) ISB Standby Current (CMOS) ISB1 CE =VIH, other pins =VIL or VIH CE =VCC-0.2V other pins at 0.2V or Vcc-0.2V 55 70 100 Tcycle= 1µs Tcycle= 500ns -L -LL MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V V 2.2 VCC+0.3 -0.2 0.6 V -1 1 µA -1 1 µA 2.2 2.7 V 0.4 V 30 40 mA 20 30 mA 16 25 mA - 4 5 mA - 8 10 mA - 0.3 20 2 0.5 80 20 mA µA µA Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA/2.1mA AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = -40℃ to 85℃(I)) (1) READ CYCLE PARAMETER SYMBOL UT62L25716(I)-55 MIN. MAX. Read Cycle Time tRC 55 Address Access Time tAA 55 Chip Enable Access Time tACE 55 Output Enable Access Time tOE 30 Chip Enable to Output in Low Z tCLZ* 10 Output Enable to Output in Low Z tOLZ* 5 Chip Disable to Output in High Z tCHZ* 20 Output Disable to Output in High Z tOHZ* 20 Output Hold from Address Change tOH 10 tBA 55 LB , UB Access Time t 25 BHZ LB , UB to High-Z Output tBLZ 10 LB , UB to Low-Z Output UT62L25716(I)-70 MIN. 70 10 5 10 10 MAX. 70 70 35 25 25 70 30 - UT62L25716(I)-100 MIN. 100 10 5 10 10 UNIT MAX. 100 100 50 30 30 100 40 - ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE SYMBOL UT62L25716(I)-55 MIN. MAX. Write Cycle Time tWC 55 Address Valid to End of Write tAW 50 Chip Enable to End of Write tCW 50 Address Set-up Time tAS 0 Write Pulse Width tWP 45 Write Recovery Time tWR 0 Data to Write Time Overlap tDW 25 Data Hold from End of Write Time tDH 0 Output Active from End of Write tOW* 5 Write to Output in High Z tWHZ* 30 tBW 45 LB , UB Valid to End of Write PARAMETER UT62L25716(I)-70 MIN. 70 60 60 0 55 0 30 0 5 60 MAX. 30 - UT62L25716(I)-100 UNIT MIN. 100 80 80 0 70 0 40 0 5 80 MAX. 40 - * These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80046 ns ns ns ns ns ns ns ns ns ns ns UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE CE2 tBA LB , UB t BHZ tBLZ OE tOE t CHZ tCLZ tOLZ Dout tOHZ t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, CE2=high, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW CE2 t AS tW P tW R WE tBW LB , UB t W HZ t OW High-Z Dout (4) (4) tDW tDH Din Data Valid WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W CE2 tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR CE2 tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃(I)) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧VCC-0.2V or CE2≦0.2V Vcc=1.5V -L - LL CE ≧VCC-0.2V or CE2≦0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 1 0.5 50 20 µA µA 0 - - ms 5 - - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V VCC CE2 VCC(min.) VCC(min.) tCDR tR VIL CE2 ≦ 0.2V VIL Low Vcc Data Retention Waveform (3) ( LB , UB controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR LB,UB VIH tR LB,UB ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 VIH P80046 UTRON Rev. 1.3 UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80046 UTRON UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.3 ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. UT62L25716BS-55LI UT62L25716BS-55LLI UT62L25716BS-70LI UT62L25716BS-70LLI UT62L25716BS-100LI UT62L25716BS-100LLI ACCESS TIME ( ns ) 55 55 70 70 100 100 STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA ORDERING INFORMATION (for lead free product) INDUSTRIAL TEMPERATURE PART NO. UT62L25716BSL-55LI UT62L25716BSL-55LLI UT62L25716BSL-70LI UT62L25716BSL-70LLI UT62L25716BSL-100LI UT62L25716BSL-100LLI ACCESS TIME ( ns ) 55 55 70 70 100 100 STANDBY CURRENT ( µA ) typ. 20 2 20 2 20 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 PACKAGE 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA 48 PIN BGA P80046 UTRON Rev. 1.3 UT62L25716(I) 256K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80046