GM71C17803C GM71CS17803CL 2,097,152 WORDS x 8 BIT CMOS DYNAMIC RAM Description Features The GM71C(S)17803C/CL is the new generation dynamic RAM organized 2,097,152 x 8 bit. GM71C(S)17803C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)17803C/CL offers Extended Data out(EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)17803C/CL to be packaged in standard 400 mil 28 pin plastic SOJ, and standard 400mil 28pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. * 2,097,152 Words x 8 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time tRAC tCAC 50 60 70 GM71C(S)17803C/CL-5 GM71C(S)17803C/CL-6 GM71C(S)17803C/CL-7 28 TSOP II 28 SOJ VCC 1 28 VSS VCC 1 VSS 28 VSS I/O0 2 27 I/O7 I/O0 2 I/O7 27 I/O7 I/O1 3 26 I/O6 I/O1 3 I/O6 26 I/O6 I/O2 4 25 I/O5 I/O2 4 I/O5 25 I/O5 I/O3 5 24 I/O4 I/O3 5 I/O4 24 I/O4 WE 6 23 CAS WE 6 CAS 23 CAS RAS NC 7 22 OE RAS 7 22 OE 8 21 A9 NC 8 21 A9 A10 9 20 A8 A10 9 20 A8 A0 10 19 A7 A0 10 19 A7 A1 11 18 A6 A1 11 18 A6 A2 12 17 A5 A2 12 17 A5 A3 13 16 A4 A3 13 15 VSS VCC 14 (Top View) Rev 0.1 / Apr’01 tRC tHPC 84 104 124 20 25 30 * Low Power Active : 715/660/605/550mW (MAX) Standby : 11mW (CMOS level : MAX) 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L- version) * Battery Back Up Operation (L- version) * Self Refresh Operation (L-version) Pin Configuration VCC 14 13 15 18 (Unit: ns) 16 A4 VSS 15 VSS GM71C17803C GM71CS17803CL Pin Description Pin Function Pin Function A0-A10 Address Inputs WE Read/Write Enable A0-A10 Refresh Address Inputs OE Output Enable I/O0-I/O7 Data-In/Out VCC Power (+5V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe NC No Connection Ordering Information Type No. Access Time Package GM71C(S)17803CJ/CLJ -5 GM71C(S)17803CJ/CLJ -6 GM71C(S)17803CJ/CLJ -7 50ns 60ns 70ns 400 Mil 28 Pin Plastic SOJ GM71C(S)17803CT/CLT -5 GM71C(S)17803CT/CLT -6 GM71C(S)17803CT/CLT -7 50ns 60ns 70ns 400 Mil 28 Pin Plastic TSOP II Absolute Maximum Ratings* Symbol Parameter Rating Unit TA Ambient Temperature under Bias TSTG Storage Temperature (Plastic) VIN/VOUT Voltage on any Pin Relative to VSS -1.0 ~ +7.0 V VCC Supply voltage Relative to VSS -1.0 ~ +7.0 V IOUT Short Circuit Output Current 50 mA PT Power Dissipation 1.0 W 0 ~ +70 C -55 ~ +125 C Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Recommended DC Operating Conditions (TA = 0 ~ +70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - 6.0 V VIL Input Low Voltage -1.0 - 0.8 V Note: All voltage referred to Vss. Rev 0.1 / Apr’01 GM71C17803C GM71CS17803CL DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C) Symbol Parameter Min Max Unit VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.0 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V 50ns - 130 60ns - 120 70ns - 110 - 2 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) mA Note 1, 2 mA RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) 50ns - 130 60ns - 120 70ns - 110 EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) 50ns - 130 60ns - 120 70ns - 110 - 1 mA - 150 uA 50ns - 130 60ns - 120 70ns - 110 - 500 uA 4,5 - 5 mA 1 - 300 uA 5 Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) Battery Back Up Operating Current(Standby with CBR Refresh) (CBR refresh, tRC=62.5us, tRAS<=0.3us, DOUT=High-Z ,CMOS interface) Standby Current RAS = VIH CAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT=High-Z) mA 2 mA 1, 3 mA IL(I) Input Leakage Current Any Input (0V<=VIN<= 6V) -10 10 uA IL(O) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 6V) -10 10 uA Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2V) while RAS = L (<=0.2V). 5. L-version. Rev 0.1 / Apr’01 5 GM71C17803C GM71CS17803CL Capacitance (VCC = 5V+/-10%, TA = 25C) Symbol Parameter Min Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Vss = 0V Note 1, 2, 18) Test Conditions Input rise and fall times : 2 ns Input timing reference levels : 0.8V, 2.4V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-6 C/CL-7 C/CL-5 Unit Note Min Max Min Max Min Max tRC Random Read or Write Cycle Time 84 - 104 - 124 - ns tRP RAS Precharge Time 30 - 40 - 50 - ns tCP CAS Precharge Time 7 - 10 - 13 - ns tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 ns tCAS CAS Pulse Width 7 10,000 10 10,000 13 10,000 ns tASR Row Address Set up Time 0 - 0 - 0 - ns tRAH Row Address Hold Time 7 - 10 - 10 - ns tASC Column Address Set-up Time 0 - 0 - 0 - ns tCAH tRCD tRAD tRSH tCSH Column Address Hold Time 7 - 10 - 13 - ns 11 37 14 45 14 52 ns 3 9 25 12 30 12 35 ns 4 RAS Hold Time 10 - 13 - 13 - ns CAS Hold Time 35 - 40 - 45 - ns tCRP tODD CAS to RAS Precharge Time 5 - 5 - 5 - ns 13 - 15 - 18 - ns 5 tDZO tDZC tT OE Delay Time from DIN 0 - 0 - 0 - ns 6 CAS Delay Time from DIN 0 - 0 - 0 - ns 6 Transition Time (Rise and Fall) 2 50 2 50 2 50 ns 7 RAS to CAS Delay Time RAS to Column Address Delay Time OE to DIN Delay Time Rev 0.1 / Apr’01 GM71C17803C GM71CS17803CL Read Cycle Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-5 C/CL-6 C/CL-7 Min Max Unit Note Min Max Min Max tRAC Access Time from RAS - 50 - 60 - 70 ns 8,9 tCAC Access Time from CAS - 13 - 15 - 18 ns 9,10,17 tAA Access Time from Address - 25 - 30 - 35 ns 9,11,17 tOAC Access Time from OE - 13 - 15 - 18 ns 9 tRCS Read Command Setup Time 0 - 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns 12 tRRH tRAL Read Command Hold Time to RAS 5 - 5 - 5 - ns 12 Column Address to RAS Lead Time 25 - 30 - 35 - ns tCAL Column Address to CAS Lead Time 15 - 18 - 23 - ns tCLZ CAS to Output in Low-Z 0 - 0 - 0 - ns tOH Output Data Hold Time 3 - 3 - 3 - ns tOHO Output Data Hold Time from OE 3 - 3 - 3 - ns tOFF Output Buffer Turn-off Time - 13 - 15 - 15 ns 13 tOEZ Output Buffer Turn-off Time to OE - 13 - 15 - 15 ns 13 tCDD CAS to DIN Delay Time 13 - 15 - 18 - ns 5 tRCHR Read Command Hold Time from RAS 50 - 60 - 70 - ns tOHR Output Data hold Time from RAS 3 - 3 - 3 - ns tOFR Output Buffer turn off to RAS - 13 - 15 - 15 ns tWEZ Output Buffer turn off to WE - 13 - 15 - 15 ns tWDD WE to DIN Delay Time 13 - 15 - 18 - ns tRDD RAS to DIN Delay Time 13 - 15 - 18 - ns Rev 0.1 / Apr’01 GM71C17803C GM71CS17803CL Write Cycle GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-6 C/CL-7 C/CL-5 Symbol Parameter Min Max Min Max Min Max Unit Note 14 tWCS Write Command Setup Time 0 - 0 - 0 - ns tWCH Write Command Hold Time 7 - 10 - 13 - ns tWP Write Command Pulse Width 7 - 10 - 10 - ns tRWL Write Command to RAS Lead Time 7 - 10 - 13 - ns tCWL Write Command to CAS Lead Time 7 - 10 - 13 - ns tDS tDH Data-in Setup Time 0 - 0 - 0 - ns 15 Data-in Hold Time 7 - 10 - 13 - ns 15 Unit Note Read- Modify-Write Cycle Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-6 C/CL-7 C/CL-5 Min Max Min Max Min Max tRWC Read-Modify-Write Cycle Time tRWD 111 - 136 - 161 - ns RAS to WE Delay Time 67 - 79 - 92 - ns 14 tCWD CAS to WE Delay Time 30 - 34 - 40 - ns 14 tAWD Column Address to WE Delay Time 42 - 49 - 57 - ns 14 tOEH OE Hold Time from WE 13 - 15 - 18 - ns Refresh Cycle Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-5 C/CL-6 C/CL-7 Unit Min Max Min Max Min Max tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - ns tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 7 - 10 - 10 - ns tWRP WE Setup Time (CAS-before-RAS Refresh Cycle) 0 - 0 - 0 - ns tWRH WE Hold Time (CAS-before-RAS Refresh Cycle) 10 - 10 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns Rev 0.1 / Apr’01 Note GM71C17803C GM71CS17803CL EDO Page Mode Cycle Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-5 C/CL-6 C/CL-7 Unit Note ns 19 ns 16 9,17 Min Max Min Max Min Max tHPC EDO Page Mode Cycle Time tRASP EDO Page Mode RAS Pulse Width - tACP tRHCP Access Time from CAS Precharge - 30 - 35 - 40 ns RAS Hold Time from CAS Precharge 30 - 35 - 40 - ns tDOH tCOL Output data Hold Time from CAS low 3 - 3 - 3 ns CAS Hold Time referred OE 7 - 10 - 13 ns tCOP CAS to OE Setup Time 5 - 5 - 5 ns tRCHP Read command Hold Time from CAS Precharge 30 - 35 - 40 ns 20 100,000 25 - 100,000 30 - 100,000 9 EDO Page Mode Read-Modify-Write Cycle Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-5 C/CL-6 C/CL-7 Min Max Min Unit Note Max Min Max tHPRWC EDO Page Mode Read-Modify-Write Cycle Time 57 - 68 - 79 - ns tCPW WE Delay Time from CAS Precharge 45 - 54 - 62 - ns 14 Unit Note Refresh Symbol Parameter GM71C(S)17803 GM71C(S)17803 GM71C(S)17803 C/CL-6 C/CL-7 C/CL-5 Min Max Min Max Min Max tREF Refresh period - 32 - 32 - 32 ms tREF Refresh period (L -Series) - 128 - 128 - 128 ms 2048 cycles 2048 cycles Self Refresh Mode ( L-version ) Symbol Parameter GM71CS17803 CL-5 GM71CS17803 CL-5 GM71CS17803 CL-5 Unit Min Max Min Max Min Max tRASS RAS Pulse Width ( Self-refresh ) tRPS RAS Precharge Time ( Self-refresh ) tCHS CAS Hold Time ( Self-refresh ) Rev 0.1 / Apr’01 100 - 100 - 100 - µs 90 - 110 - 130 - ns -50 - -50 - -50 - ns Note GM71C17803C GM71CS17803CL Notes: 1. AC Measurements assume tT = 2ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS only refresh or CAS-beforeRAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100pF. 10. Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max). 11. Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD , tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min) and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read modify write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in a delayed write or a read modify write cycle. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance): if tOEH<=tCWL, invalid data will be out at each I/O. 19. tHPC (min ) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1)(2) ),minimum value of CAS cycle( tCAS + tCP + 2tT) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle(1) and (2). Rev 0.1 / Apr’01 GM71C17803C GM71CS17803CL Package Dimensions Unit: Inches (mm) 28 SOJ 0.025(0.64) 0.366(9.30) MIN 0.375(9.55) MAX 0.435(11.06) MIN 0.445(11.30) MAX 0.395(10.03) MIN 0.405(10.29) MAX MIN 0.083(2.10) 0.710(18.04) MIN MIN 0.720(18.30) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) TYP 0.026(0.66) MIN 0.032(0.81) MAX 0.015(0.38) MIN 0.020(0.50) MAX 28 TSOP (TYPE II) 0.455(11.56) MIN 0.720(18.28) MIN 0.008(0.21) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX Rev 0.1 / Apr’01 0.016(0.40) MIN 0.024(0.60) MAX 0.004(0.12) MIN 0.730(18.54) MAX 0.012(0.30) MIN 0.020(0.50) MAX o 0.471(11.96) MAX 0.394(10.03) MIN 0.405(10.29) MAX 0~5 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX