GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841ET/ELT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 143 Mhz. Features * PC133/PC100/PC66 Compatible -7(143MHz)/-75(133MHz)/-8(125MHz) -7K(PC100,2-2-2)/-7J(PC100,3-2-2) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 143/133/125/100MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh / Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit * JEDEC Standard 54Pin 400mil TSOP II Package Pin Configuration VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Name CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ VCC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask V CC for DQ V SS for DQ Power for internal circuit Ground for internal circuit No Connection This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any -1responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Apr.01 GM72V66841ET/ELT Block Diagram A0 to A13 A0 to A8 4096 row x 512 column x 8 bit Bank 3 4096 row x 512 column x 8 bit Control logic & timing generator DQM Output buffer DQ0 to DQ7 Rev. 1.1/Apr.01 Bank 2 Memory array CAS Input buffer Column decoder Sense amplifier & I/O bus 4096 row x 512 column x 8 bit Memory array RAS Bank 1 Row decoder CS 4096 row x 512 column x 8 bit Memory array CKE Bank 0 Refresh counter Row decoder Column decoder Sense amplifier & I/O bus Memory array Row decoder Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Row decoder Row address counter WE Column address buffer CLK Column address counter A0 to A13 -2- GM72V66841ET/ELT Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT -0.5 to Vcc+0.5 (<= 4.6 (max)) V 1 Supply voltage relative to V SS V CC -0.5 to +4.6 V 1 Short circuit output current I OUT 50 mA PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Power dissipation Notes : 1. Respect to VS S Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Symbol Min Max Unit Note V CC, VCCQ 3.0 3.6 V 1 V SS, VSSQ 0 0 V Input high voltage V IH 2.0 Vcc+0.3 V 1, 2 Input low voltage V IL -0.3 0.8 V 1,3 Supply voltage Notes : 1. All voltage referred to V SS. 2. V IH (max) = 5.6V for pulse width <= 3ns 3. V IL (min) = -2.0V for pulse width <= 3ns Rev. 1.1/Apr.01 -3- GM72V66841ET/ELT DC Characteristics (Ta = 0 to 70C, VCC , VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) Parameter Operating current I CC1 Standby current in power down I CC2P Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) -7 - 75 -8 -7K -7J Max Max Max Max Max 85 85 80 80 80 Symbol Unit Test conditions 2 mA mA 2 I CC2PS mA 0.4 Burst length= 1 t RC = min CKE = V IL, t CK = 12 ns CKE=V IL, t CK= infinity 6 6,8 mA CKE,CS = V IH, t CK = 12ns 4 I CC2NS 12 mA CKE = V IH, t CK = infinity 4 1,2,5 2,6 I CC3P 6 mA Active standby current in power down (input signal stable) I CC3PS 5 mA CKE = V IL, t CK = infinity I CC3N 30 mA CKE,CS = V IH, t CK = 12 ns, DQ = High-Z Active standby current in non power down I CC3NS (input signal stable) 20 mA CKE = V IH, t CK = infinity 120 mA t CK = min ( CL= 2 ) I CC4 ( CL= 3 ) I CC4 Refresh current I CC5 Self refresh current I CC6 150 150 150 160 120 120 mA 0.4 BL = 4 1,2,4 2,9 1,2,3 mA t RC = min 3 V IH >=VCC - 0.2 V IL <=0.2V 7 mA 1 Rev. 1.1/Apr.01 5 15 CKE = V IL, t CK = 12 ns, DQ = High-Z Burst operating current 1, 2, 3 I CC2N Active standby current in power down Active standby current in non power down Notes 7,8 -4- GM72V66841ET/ELT DC Characteristics (Ta = 0 to 70C, VCC , VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) (Continued) - 7, - 75, - 8, - 7K, - 7J Parameter Symbol Unit Test conditions Min Max Input leakage current I LI -1 1 uA 0 <=Vin <=VCC Output leakage current I LO -1.5 1.5 uA 0<=Vout<=VCC DQ = disable Output high voltage V OH 2.4 - V I OH = -2 mA Output low voltage V OL - 0.4 V I OL =2 mA Notes Notes : 1. ICC depends on output load condition when the device is selected. I CC ( max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. L-Version. 9. Input signals are VI H or V IL fixed. Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V +/-0.3 V) Parameter Symbol Min. Max. Unit Notes Input capacitance (CLK) CI1 2.5 4 pF 1, 3, 4 Input capacitance (Signals) CI2 2.5 5 pF 1, 3, 4 Output capacitance (DQ) CO 4.0 6.5 pF 1, 2, 3, 4 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = VI H to disable Dout. 3. This parameter is sampled and not 100% tested. 4. Measured with 1.4 V bias and 200mV swing at the pin under measurement. Rev. 1.1/Apr.01 -5- GM72V66841ET/ELT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) -7 Parameter - 75 -8 - 7K - 7J Symbol Unit Notes Min Max Min Max Min Max Min Max Min Max (CL=2) t CK t CK t CKH t CKL t AC t AC t OH 10 - 10 - 10 - 10 - 15 - 7 - 7.5 - 8 - 10 - 10 - 2.5 - 2.5 - 3 - 3 - 3 2.5 - 2.5 - 3 - 3 - - 6 - 6 - 6 - - 5.4 - 5.4 - 6 2.7 - 2.7 - 3 t LZ 1.5 - 1.5 - t HZ - 5.4 - 1.5 - 0.8 CKE setup time t DS t DH t AS t AH t CES CKE setup time for power down exit System clock cycle time ns 1 - ns 1 3 - ns 1 6 - 8 ns 1, 2 - 6 - 6 - 3 - 3 - ns 1, 2 2 - 2 - 2 - ns 1, 2, 3 5.4 - 6 - 6 - 6 ns 1, 4 1.5 - 2 - 2 - 2 - ns 1 - 0.8 - 1 - 1 - 1 - ns 1 1.5 - 1.5 - 2 - 2 - 2 - ns 1 0.8 - 0.8 - 1 - 1 - 1 - ns 1 1.5 - 1.5 - 2 - 2 - 2 - ns 1, 5 t CESP 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE hold time t CEH 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command (CS, RAS, CAS, WE, DQM) setup time t CS 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command (CS, RAS, CAS, WE, DQM) hold time t CH 0.8 - 0.8 - 1 - 1 - 1 - ns 1 t RC 62 - 65 - 68 - 70 - 70 - ns 1 t RAS 42 120000 45 120000 48 120000 50 120000 50 120000 ns 1 t RCD 20 - 20 - 20 - 20 - 20 - ns 1 t RP 20 - 20 - 20 - 20 - 20 - ns 1 (CL=3) CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Rev. 1.1/Apr.01 -6- GM72V66841ET/ELT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/-0.3 V, VSS, VSSQ = 0 V) (Continued) -7 Parameter - 75 -8 - 7K - 7J Symbol Unit Notes Min Max Min Max Min Max Min Max Min Max Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Refresh period t RWL 7 - 7.5 - 8 - 10 - 10 - ns 1 t RRD 14 - 15 - 16 - 20 - 20 - ns 1 t REF - 64 - 64 - 64 - 64 - 64 ms Notes : 1. AC measurement assumes t T = 1ns. Reference level for timing of input signals is 1.40V. If tT is longer than 1ns,transition time compensation should be considered. 2. Access time is measured at 1.40V. Load condition is C L = 50pF without termination. 3. t LZ (min)defines the time at which the outputs achieves the low impedance state. 4. t HZ (max)defines the time at which the outputs achieves the high impedance state. 5. t CES define CKE setup time to CKE rising edge except Power down exit command. Test Condition • Input and output-timing reference levels: 1.4V • Input waveform and output load: See following figures I/O input 2.4V 80% 0.4V 20% OPEN CL tT Rev. 1.1/Apr.01 tT -7- GM72V66841ET/ELT Relationship Between Frequency and Minimum Latency -7 Parameter frequency(MHz) Symbol tCK (ns) -75 -8 -7K -7J 143 100 133 100 125 100 100 100 100 66 Notes 7 10 7.5 10 8 10 10 10 10 15 l RCD 3 2 3 2 3 2 2 2 2 2 1 l RC 9 7 9 7 9 7 7 7 7 6 = [l RAS + lRP ], 1 l RAS 6 5 6 5 6 5 5 5 5 4 1 l RP 3 2 3 2 3 2 2 2 2 2 1 l RWL 1 1 1 1 1 1 1 1 1 1 1 l RRD 2 2 2 2 2 2 2 2 2 2 1 l SREX 1 1 1 1 1 2 1 1 1 2 l APW 4 3 4 3 4 3 3 3 3 3 = [l RWL + lRP ], 1 l SEC 9 7 9 7 9 7 7 7 7 6 = [l RC ] l HZP l HZP - 2 - 2 - 2 2 2 - 2 3 3 3 3 3 3 3 3 3 3 l APR 1 1 1 1 1 1 1 1 1 1 l EP l EP - -1 - -1 - -1 -1 -1 - -1 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 l CCD 1 1 1 1 1 1 1 1 1 1 l WCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS to command disable l DID l DOD l CLE l RSA l CDD 0 0 0 0 0 0 0 0 0 0 Power down exit to command input l PEC 1 1 1 1 1 1 1 1 1 1 Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command Rev. 1.1/Apr.01 -8- GM72V66841ET/ELT Relationship Between Frequency and Minimum Latency Parameter -7 -8 - 7K - 7J Symbol 143 100 133 100 125 100 100 100 100 frequency(MHz) tCK (ns) Burst stop to output valid data hold Burst stop to output high impedance -75 (CL=2) (CL=3) (CL=2) (CL=3) Burst stop to write data ignore l BSR l BSR l BSH l BSH l BSW 66 7 10 7.5 10 8 10 10 10 10 15 - 1 - 1 - 1 1 1 - 1 2 2 2 2 2 2 2 2 2 2 - 2 - 2 - 2 2 2 - 2 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 Notes Notes : 1. l RCD to l RRD are recommended value. Rev. 1.1/Apr.01 -9- GM72V66841ET/ELT Package Dimensions GM72V66841ET/ELT Series (TTP-54D) Unit: (mm) Preliminary 22.22 22.72 Max 28 10.16 54 1 0.80 27 +0.10 - 0.05 0.30 0.28 +/- 0.05 0.13 M 0.80 11.76 +/- 0.20 0.91 MAX Dimension including the plating thickness Base material dimension Rev. 1.1/Apr.01 0.50 +/- 0.10 Hitachi Code TTP-54D JEDEC Code - EIAJ Code - Weight(reference value) 0.53g 0.68 0.13 +/- 0.05 0.125 +/- 0.04 0.10 0.145 +/- 0.05 1.20 MAX 0 ~。 5 -10-