8Mx72 bits PC100/PC133 SDRAM Registered DIMM based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh GMM2739230EPTG Description Features The GMM2739230EPTG is a 8M x 72bits Synchronous Dynamic RAM MODULE which is assembled 9 pieces of 8M x 8bits Synchronous DRAMs in 54 pin TSOP II package, 2 pieces of 16 bits Register in 48 pin TSSOP package, one clock distribution PLL in 24 pin SOP and one 2048 bit EEPROM in 8 pin TSSOP package mounted on a 168 pin printed circuit board with decoupling capacitors. The GMM2739230EPTG is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others which are requested compact size. The GMM2739230EPTG provides common data inputs and outputs. GMM2739230EPTG (Double Side) * PC133/PC100/PC66 Compatible -7(143MHz)/-75(133MHz)/8(125MHz) -7K(PC100,2-2-2)/7J(PC100,3-2-2) * 3.3V +/- 0.3V Power supply * Maximum Clock frequency 100/125/133/143 MHz * LVTTL Interface * Burst read/write operation and burst read/ single write operation capability * Programmable burst length ; 1, 2, 4, 8, Full page * Programmable burst sequence Sequential / Interleave * Full Page burst length capability Sequential burst Burst stop capability * Programmable CAS Latency ; 2, 3 * CKE power down mode * Input / Output data masking * 4096 Refresh Cycles / 64ms * Auto refresh / Self refresh Capability * Serial Presence Detect with EEPROM Pin Name (Top) (Bottom) CK0, 1, 2, 3 CKE0 S0, 2 RAS CAS WE A0 ~ A11 BA0,1 REGE DQ0 ~ 63 CB0 ~ 7 DQMB0 ~ 7 V CC V SS NC V REF SDA SCL SA0 ~ 2 WP DU Clock input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Bank Address input Register Enable Data input / output Check Bits Data input / output Mask Power for internal circuit Ground for internal circuit No Connect Power Supply for Reference Serial Data input/ output Serial Clock Address in EEPROM Write Protect for SPD Don't Use This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Apr.01 1 GMM2739230EPTG Pin Configuration Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VSS 29 DQMB1 57 DQ18 85 VSS 2 DQ0 30 S0 58 DQ19 86 3 DQ1 31 DU 59 VCC 4 DQ2 32 VSS 60 DQ20 5 DQ3 33 A0 61 NC 6 VCC 34 A2 62 *VREF, NC 90 7 DQ4 35 A4 63 *CKE1 8 DQ5 36 A6 64 VSS 9 DQ6 37 A8 65 10 DQ7 38 A10/AP 11 DQ8 39 12 VSS 40 13 DQ9 14 Pin Symbol Pin Symbol 113 DQMB5 141 DQ50 DQ32 114 *S1 142 DQ51 87 DQ33 115 RAS 143 VCC 88 DQ34 116 VSS 144 DQ52 89 DQ35 117 A1 145 NC VCC 118 A3 146 *VREF, NC 91 DQ36 119 A5 147 REGE 92 DQ37 120 A7 148 VSS DQ21 93 DQ38 121 A9 149 DQ53 66 DQ22 94 DQ39 122 BA0 150 DQ54 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55 VCC 68 VSS 96 VSS 124 VCC 152 VSS 41 VCC 69 DQ24 97 DQ41 125 CK1 153 DQ56 DQ10 42 CK0 70 DQ25 98 DQ42 126 *A12 154 DQ57 15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58 16 DQ12 44 DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 S2 73 VCC 101 DQ45 129 *S3 157 VCC 18 VCC 46 DQMB2 74 DQ28 102 VCC 130 DQMB6 158 DQ60 19 DQ14 47 DQMB3 75 DQ29 103 DQ46 131 DQMB7 159 DQ61 20 DQ15 48 DU 76 DQ30 104 DQ47 132 *A13 160 DQ62 21 CB0 49 VCC 77 DQ31 105 CB4 133 VCC 161 DQ63 22 CB1 50 NC 78 VSS 106 CB5 134 NC 162 VSS 23 VSS 51 NC 79 CK2 107 VSS 135 NC 163 CK3 24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC 25 NC 53 CB3 81 WP 109 NC 137 CB7 165 SA0 26 VCC 54 VSS 82 SDA 110 VCC 138 VSS 166 SA1 27 WE 55 DQ16 83 SCL 111 CAS 139 DQ48 167 SA2 28 DQMB0 56 DQ17 84 VCC 112 DQMB4 140 DQ49 168 VCC * These pins are not used in this module Rev. 1.1/Apr.01 2 GMM2739230EPTG Block Diagram S0 0 1 2 3 4 5 6 7 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ DQ DQ DQ DQ DQ DQ DQ DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB0 DQ DQ DQ DQ DQ DQ DQ DQ DQMB1 CS U0 CS DQMB5 U1 CS DQ DQ DQ DQ DQ DQ DQ DQ 32 33 34 35 36 37 38 39 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ DQ DQ DQ DQ DQ DQ DQ 40 41 42 43 44 45 46 47 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ53 DQ 54 DQ 55 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ DQ DQ DQ DQ DQ DQ DQ DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB4 DQMB6 U2 CS U5 CS U6 CS U7 S2 DQMB2 DQMB3 24 25 26 27 28 29 30 31 CS DQMB7 U3 CS U8 CS U0 - U8 U0 - U8 U0 - U8 U0 - U8 U0 - U8 U0 - U8 A0 ~ A11, BA0,1 U4 RAS CAS Register CKE0, DQMB0~7 WE S0,2 10ohm CK0 PLL 10ohm 56 57 58 59 60 61 62 63 12pF PCK REGE Vcc 10kohm CK1,2,3 12pF SCL V CC V SS Capacitor two 0.0022uF and one 0.22uF per SDRAM Serial PD A1 SDA WP A2 U0 ~ U8 A0 U0 ~ U8 SA0 SA1 SA2 Vss 47kohm Rev. 1.1/Apr.01 3 GMM2739230EPTG Pin Description Pin Name CK0, 1, 2, 3 (input pins) CKE0 (input pin) S0, 2 (input pins) RAS, CAS and WE (input pins) A0 ~ A11 (input pins) DESCRIPTION CK is the master clock input to this pin. The other input signals are referred at CK rising edge. This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. When S is Low, the command input cycle becomes valid. When S is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CK rising edge. Column address is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 is precharged. BA0,1 (input pin) BA0,1 are bank select signal. If BA0 is Low and BA1 is High, bank 0 is selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is High, bank 3 is selected. DQ0 ~ DQ63 CB0 ~ CB7 (I/O pins) Data is input and output from these pins. These pins are the same as those of a conventional DRAMs. Data is not latched in the register. DQMB0 ~ DQMB7 (input pins) DQMB controls input/output buffers. Read operation: If DQMB is High, The output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. V CC 3.3 V is applied. (VCC is for the internal circuit) V SS Ground is connected. (VSS is for the internal circuit) REGE (register enable pin) NC Rev. 1.1/Apr.01 If REGE input is high, permits the DIMM to operate in `registered mode`. If REGE input is low, permits the DIMM to operate in `buffered mode`. No Connection pins. 4 GMM2739230EPTG Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT -0.5 to Vcc+0.5 (<= 4.6 (max)) V 1 Supply voltage relative to V SS V CC -0.5 to +4.6 V 1 Short circuit output current I OUT 50 mA PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Power dissipation Notes : 1. Respect to VS S Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Symbol Min Max Unit Note V CC, VCCQ 3.0 3.6 V 1 V SS, VSSQ 0 0 V Input high voltage V IH 2.0 Vcc+0.3 V 1, 2 Input low voltage V IL -0.3 0.8 V 1,3 Supply voltage Notes : 1. All voltage referred to V SS. 2. V IH (max) = 5.6V for pulse width <= 3ns 3. V IL (min) = -2.0V for pulse width <= 3ns Registered DIMM Operation 1. All control and address signals are registered on-DIMM register and hence delayed by one cycle in arriving at the SDRAMs. But data is not registered in the register. 2. CAS latency defines the delay from when a READ command is registered on a rising clock edge to when the data from that READ command becomes available at the outputs. Do not confuse DIMM CAS latency with the SDRAM CAS latency which is one clock less. Rev. 1.1/Apr.01 5 GMM2739230EPTG DC Characteristics (Ta = 0 to 70C, VCC , VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) Parameter -7 - 75 -8 -7K -7J Max Max Max Max Max Symbol Unit Test conditions Burst length= 1 t RC = min CKE = V IL, t CK = 12 ns Notes Operating current I CC1 760 760 720 720 720 mA Standby current in power down I CC2P 20 20 20 20 20 mA I CC2PS 20 20 20 20 20 mA CKE=V IL, t CK= infinity 6 I CC2N 150 150 150 150 150 mA CKE,CS = V IH, t CK = 12ns 4 I CC2NS 50 50 50 50 50 mA CKE = V IH, t CK = infinity 4 1,2,5 2,6 Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) Active standby current in power down I CC3P 60 60 60 60 60 mA CKE = V IL, t CK = 12 ns, DQ = High-Z Active standby current in power down (input signal stable) I CC3PS 50 50 50 50 50 mA CKE = V IL, t CK = infinity I CC3N 300 300 300 300 300 mA CKE,CS = V IH, t CK = 12 ns, DQ = High-Z Active standby current in non power down I CC3NS (input signal stable) 200 200 200 200 200 mA CKE = V IH, t CK = infinity t CK = min Active standby current in non power down Burst operating current 1, 2, 3 5 1,2,4 2,8 ( CL= 2 ) I CC4 1100 1100 1100 1100 1100 mA ( CL= 3 ) I CC4 1400 1400 1400 1100 1100 mA Refresh current I CC5 1000 1000 1000 1000 1000 mA t RC = min 3 Self refresh current I CC6 10 10 10 10 10 mA V IH >=VCC - 0.2 V IL <=0.2V 7 Rev. 1.1/Apr.01 BL = 4 1,2,3 6 GMM2739230EPTG - 7, - 75, - 8, - 7K, - 7J Parameter Symbol Unit Test conditions Min Max Input leakage current I LI -1 1 uA 0 <=Vin <=VCC Output leakage current I LO -1.5 1.5 uA 0<=Vout<=VCC DQ = disable Output high voltage V OH 2.4 - V I OH = -2 mA Output low voltage V OL - 0.4 V I OL =2 mA Notes Notes : 1. ICC depends on output load condition when the device is selected. I CC ( max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. Input signals are VI H or V IL fixed. Capacitance (Ta = 25C, VCC, VCCQ = 3.3V +/- 0.3V) Symbol Parameter Min Max Unit Notes CI1 Input capacitance (A0 ~ A11, BA0, BA1) 7 10 pF 1, 3 CI2 Input capacitance (RAS, CAS, WE, CKE0) 15 17 pF 1, 3 CI3 Input capacitance (CK0, CK1, CK2, CK3) 33 35 pF 1, 3 CI4 Input capacitance (S0,S2) 7 10 pF 1, 3 CI6 Input capacitance (DQMB0,1,2,3,4,5,6,7) 7 38 pF 1, 3 CI/O I/O capacitance (DQ0 ~ 63, CB0 ~ 7) 7 14 pF 1, 2, 3 Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. Rev. 1.1/Apr.01 7 GMM2739230EPTG AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) -7 Parameter - 75 -8 - 7K - 7J Symbol Unit Notes Min Max Min Max Min Max Min Max Min Max (CL=2) t CK t CK t CKH t CKL t AC t AC t OH 10 - 10 - 10 - 10 - 15 - 7 - 7.5 - 8 - 10 - 10 - 2.5 - 2.5 - 3 - 3 - 3 2.5 - 2.5 - 3 - 3 - - 6 - 6 - 6 - - 5.4 - 5.4 - 6 2.7 - 2.7 - 3 t LZ 1.5 - 1.5 - t HZ - 5.4 - 1.5 - 0.8 CKE setup time t DS t DH t AS t AH t CES CKE setup time for power down exit System clock cycle time ns 1 - ns 1 3 - ns 1 6 - 8 ns 1, 2 - 6 - 6 - 3 - 3 - ns 1, 2 2 - 2 - 2 - ns 1, 2, 3 5.4 - 6 - 6 - 6 ns 1, 4 1.5 - 2 - 2 - 2 - ns 1 - 0.8 - 1 - 1 - 1 - ns 1 1.5 - 1.5 - 2 - 2 - 2 - ns 1 0.8 - 0.8 - 1 - 1 - 1 - ns 1 1.5 - 1.5 - 2 - 2 - 2 - ns 1, 5 t CESP 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE hold time t CEH 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command (CS, RAS, CAS, WE, DQM) setup time t CS 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command (CS, RAS, CAS, WE, DQM) hold time t CH 0.8 - 0.8 - 1 - 1 - 1 - ns 1 t RC 62 - 65 - 68 - 70 - 70 - ns 1 t RAS 42 120000 45 120000 48 120000 50 120000 50 120000 ns 1 t RCD 20 - 20 - 20 - 20 - 20 - ns 1 t RP 20 - 20 - 20 - 20 - 20 - ns 1 (CL=3) CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Rev. 1.1/Apr.01 8 GMM2739230EPTG AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/-0.3 V, VSS, VSSQ = 0 V) (Continued) -7 Parameter - 75 -8 - 7K - 7J Symbol Unit Notes Min Max Min Max Min Max Min Max Min Max Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Refresh period PLL Stabilization time t RWL 7 - 7.5 - 8 - 10 - 10 - ns 1 t RRD 14 - 15 - 16 - 20 - 20 - ns 1 t REF t STAB - 64 - 64 - 64 - 64 - 64 ms 200 - 200 - 200 - 200 - 200 - us 6 Notes : 1. AC measurement assumes t T = 1ns. Reference level for timing of input signals is 1.40V. If tT is longer than 1ns,transition time compensation should be considered. 2. Access time is measured at 1.40V. Load condition is C L = 50pF without termination. 3. t LZ (min)defines the time at which the outputs achieves the low impedance state. 4. t HZ (max)defines the time at which the outputs achieves the high impedance state. 5. t CES define CKE setup time to CKE rising edge except Power down exit command. 6. The on-DIMM PLL must be given enough clock cycles to stabilize ( tSTAB) before any operation can be guaranteed. Test Condition • Input and output-timing reference levels: 1.4V • Input waveform and output load: See following figures I/O input 2.4V 80% 0.4V 20% OPEN CL tT Rev. 1.1/Apr.01 tT 9 GMM2739230EPTG Relationship Between Frequency and Minimum Latency -7 Parameter frequency(MHz) Symbol tCK (ns) -75 -8 -7K -7J 143 100 133 100 125 100 100 100 100 66 Notes 7 10 7.5 10 8 10 10 10 10 15 l RCD 3 2 3 2 3 2 2 2 2 2 1 l RC 9 7 9 7 9 7 7 7 7 6 = [l RAS + lRP ], 1 l RAS 6 5 6 5 6 5 5 5 5 4 1 l RP 3 2 3 2 3 2 2 2 2 2 1 l RWL 1 1 1 1 1 1 1 1 1 1 1 l RRD 2 2 2 2 2 2 2 2 2 2 1 l SREX 1 1 1 1 1 2 1 1 1 2 l APW 4 3 4 3 4 3 3 3 3 3 = [l RWL + lRP ], 1 l SEC 9 7 9 7 9 7 7 7 7 6 = [l RC ] l HZP l HZP - 2 - 2 - 2 2 2 - 2 3 3 3 3 3 3 3 3 3 3 l APR 1 1 1 1 1 1 1 1 1 1 l EP l EP - -1 - -1 - -1 -1 -1 - -1 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 l CCD 1 1 1 1 1 1 1 1 1 1 l WCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS to command disable l DID l DOD l CLE l RSA l CDD 0 0 0 0 0 0 0 0 0 0 Power down exit to command input l PEC 1 1 1 1 1 1 1 1 1 1 Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command Rev. 1.1/Apr.01 10 GMM2739230EPTG Relationship Between Frequency and Minimum Latency Parameter -7 -8 - 7K - 7J Symbol 143 100 133 100 125 100 100 100 100 frequency(MHz) tCK (ns) Burst stop to output valid data hold Burst stop to output high impedance -75 (CL=2) (CL=3) (CL=2) (CL=3) Burst stop to write data ignore l BSR l BSR l BSH l BSH l BSW 66 7 10 7.5 10 8 10 10 10 10 15 - 1 - 1 - 1 1 1 - 1 2 2 2 2 2 2 2 2 2 2 - 2 - 2 - 2 2 2 - 2 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 Notes Notes : 1. l RCD to l RRD are recommended value. Rev. 1.1/Apr.01 11 GMM2739230EPTG Unit: mil (mm) * (1 mil = 1/1000 inches) Package Dimension 700(17.78) 1500(38.10) 157.48(4.0) 5250(133.35) 1 84 "C"1450(36.83) 450(11.43) "B" 2150(54.61) "A" 250(6.35) 1700(43.18) 4550(115.57) 157.48(4.0) max. 5013.78(127.35) 157.48(4.0) min. (Front Side) 168 85 (Rear Side) 39.37(1.0) 39.37(1.0) R78.74 (2.0) 125(3.175) 50(1.27) 125(3.175) 39.37(1.0) DETAIL "C" 78.74(2.0) DETAIL "B" 100(2.54) min. R78.74 (2.0) 5.9(0.15) 122.83(3.12) 78.74(2.0) 50(1.27) DETAIL "A" NOTE : 1. Tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. Thickness includes Plating and / or Metallization. Rev. 1.1/Apr.01 12