HA5351 Data Sheet May 1999 File Number 3690.7 64ns Sample and Hold Amplifier Features The HA5351 is a fast acquisition, wide bandwidth sample and hold amplifier, built with the Intersil HBC-10 BiCMOS process. This sample and hold amplifier offers a combination of desirable features; fast acquisition time (70ns to 0.01% maximum), excellent DC precision and extremely low power dissipation, making it ideal for use in systems that sample multiple signals and require low power. • Fast Acquisition to 0.01% . . . . . . . . . . . . . . . . . 70ns (Max) The HA5351 is in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. In unity gain the HA5351 is completely selfcontained and requires no external components. The onchip 15pF hold capacitor is completely isolated to minimizing droop rate and reduce sensitivity to pedestal error. The HA5351 is available in 8 lead PDIP and SOIC packages for minimizing board space and ease of layout. • Low Pedestal Error . . . . . . . . . . . . . . . . . . . . ±10mV (Max) • Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . 2µV/µs (Max) • Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . . 40MHz • Low Power Dissipation . . . . . . . . . . . . . . . 220mW (Max) • Total Harmonic Distortion (Hold Mode) . . . . . . . . . -72dBc - (VIN = 5VP-P at 1MHz) • Fully Differential Inputs • On Chip Hold Capacitor Applications • Synchronous Sampling Ordering Information PART NUMBER (BRAND) • Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . ±2mV (Max) TEMP. RANGE (oC) PKG. NO. PACKAGE • Wide Bandwidth A/D Conversion • Deglitching HA5351IP -40 to 85 8 Ld PDIP E8.3 • Peak Detection HA5351IB (H5351) -40 to 85 8 Ld SOIC M8.15 • High Speed DC Restore Pinout Functional Diagram V+ 6 HA5351 (PDIP, SOIC) TOP VIEW) V3 15pF -IN 8 + AV GM 1 +IN S/H 4 + OUT - +IN 1 8 -IN NC 2 7 GND V- 3 6 V+ OUT 4 5 S/H CTRL 5 BUFFER HA5351 7 GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA5351 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . +11V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Voltage Between Sample and Hold Control and Ground . . . . . +5.5V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . ±37mA Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = fc0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified Electrical Specifications HA5351I TEMP. (oC) MIN TYP MAX UNITS Input Voltage Range Full -2.5 - +2.5 V Input Resistance (Note 2) 25 100 500 - kΩ Input Capacitance 25 - - 5 pF Input Offset Voltage 25 -2 - 2 mV Full -3.0 - 3.0 mV Full - 15 - µV/oC PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS Offset Voltage Temperature Coefficient Bias Current Full - 2.5 5 µA Offset Current Full -1.5 - +1.5 µA Common Mode Range Full -2.5 - +2.5 V Full 60 80 - dB ±2.5V, Note 3 Common Mode Rejection Ratio TRANSFER CHARACTERISTICS VOUT = ±2.5V Large Signal Voltage Gain Unity Gain -3dB Bandwidth 25 95 108 - dB Full 85 - - dB 25 - 40 - MHz TRANSIENT RESPONSE Rise Time 200mV Step 25 - 8.5 - ns Overshoot 200mV Step 25 0 - 30 % Slew Rate 5V Step Full 88 105 - V/µs 25, 85 2.1 - 5.0 V -40 2.4 - 5.0 V VIL Full 0 - 0.8 V DIGITAL INPUT CHARACTERISTICS Input Voltage VIH VIL = 0V Full -1.0 - 1.0 µA VIH = 5V Full -1.0 - 1.0 µA Output Voltage RL = 510Ω Full -3.0 - +3.0 V Output Current RL = 100Ω 25, 85 20 25 - mA -40 15 - - mA Input Current OUTPUT CHARACTERISTICS 2 HA5351 Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = fc0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS HA5351I TEMP. (oC) MIN TYP MAX UNITS Full Power Bandwidth 5VP-P, AV = +1, -3dB Full - 13 - MHz Output Resistance Hold Mode 25 - 0.02 - Ω Total Output Noise (DC to 10MHz) Sample Mode 25 - 325 - µVRMS Hold Mode 25 - 325 - µVRMS VIN = 4.5VP-P, fIN = 100kHz 25 - -80 - dBc DISTORTION CHARACTERISTICS SAMPLE MODE Total Harmonic Distortion Signal to Noise Ratio (RMS Signal to RMS Noise) VIN = 5VP-P, fIN = 1MHz 25 - -74 - dBc VIN = 1VP-P, fIN = 10MHz 25 - -57 - dBc VIN = 4.5VP-P, fIN = 100kHz 25 - 73 - dB VIN = 4.5VP-P, fIN = 100kHz, fS ≅ 100kHz 25 - -78 - dBc VIN = 5VP-P, fIN = 1MHz, fS ≅ 1MHz 25 - -72 - dBc VIN = 1VP-P, fIN = 10MHz, fS ≅ 1MHz 25 - -51 - dBc VIN = 4.5VP-P, fIN = 100kHz, fS ≅ 100kHz 25 - 70 - dB 0V to 2.0V Step to ±1mV 25 - 53 - ns 0V to 2.0V Step to 0.01% (±200µV) 25 - 64 70 ns -2.5V to +2.5V Step to 0.01% (±500µV) 25 - 90 100 ns 25 - 0.3 - µV/µs HOLD MODE (50% Duty Cycle S/H) Total Harmonic Distortion Signal to Noise Ratio (RMS Signal to RMS Noise) SAMPLE AND HOLD CHARACTERISTICS Acquisition Time Droop Rate Full -2 - 2 µV/µs Hold Step Error VIL = 0V, VIH = 4.0V, tR = 5ns Full -10 - +10 mV Hold Mode Settling Time To ±1mV 25 - 50 - ns Hold Mode Feedthrough 5VP-P, 500kHz, Sine 25 - 72 - dB EADT (Effective Aperture Delay Time) 25 - +1 - ns Aperture Time (Note 2) 25 - 10 - ns Aperture Uncertainty 25 - 10 20 ps Positive Supply Current Full - 20 22 mA Negative Supply Current Full - 20 22 mA Full 60 74 - dB POWER SUPPLY CHARACTERISTICS PSRR 10% Delta NOTES: 2. Derived from Computer Simulation only, not tested. 3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V. 3 HA5351 Typical Performance Curves 0.1 OUTPUT (V) OUTPUT (V) 2 0 0.0 -0.1 -2 0 100 200 300 TIME (ns) 400 500 200 FIGURE 1. LARGE SIGNAL RESPONSE 400 TIME (ns) 600 FIGURE 2. SMALL SIGNAL RESPONSE 2 60 0 40.163156MHz -3dB -4 GAIN 0dB AT 21.34MHz 20 0 -30 -60 0 -90 -120 -6 PHASE -119.86 DEG -20 -8 100K 1M 10M 1K 100M 10K FREQUENCY (Hz) 100K 1M -150 PHASE (DEGREES) -2 GAIN (dB) GAIN (dB) 40 -180 100M 10M FREQUENCY (Hz) FIGURE 3. UNITY GAIN FREQUENCY RESPONSE FIGURE 4. CLOSED LOOP GAIN/PHASE AV = +1000 2 60 200mVP-P 50 -3dB BANDWIDTH (MHz) GAIN (dB) 0 13.241189MHz -3dB -2 -4 -6 -8 10K 4 TYPICAL UNITS 40 30 20 10 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 5. 5VP-P FULL POWER FREQUENCY RESPONSE 4 0 ±3.5 ±4 ±4.5 ±5 SUPPLY VOLTAGE (V) ±5.5 FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE ±6 HA5351 Typical Performance Curves (Continued) 0.5 160 3 TYPICAL UNITS +SLEW RATE -SLEW RATE 3 TYPICAL UNITS 150 140 SLEW RATE (V/µs) DROOP RATE (µV/µs) 0.4 0.3 0.2 UNIT #1 130 120 110 UNIT #3 UNIT #2 100 0.1 90 0 -50 0 50 TEMPERATURE (oC) 80 -50 100 FIGURE 7. DROOP RATE vs TEMPERATURE 100 FIGURE 8. SLEW RATE vs TEMPERATURE 65 9 4 TYPICAL UNITS HOLD MODE SETTLING TIME (ns) 4 TYPICAL UNITS 8 RISE TIME (ns) 0 50 TEMPERATURE (oC) 7 6 5 4 -50 0 50 TEMPERATURE (oC) 60 55 50 45 40 35 30 -50 100 FIGURE 9. RISE TIME vs TEMPERATURE 0 50 TEMPERATURE (oC) 100 FIGURE 10. HOLD MODE SETTLING vs TEMPERATURE 3 0V TO 4V S/H CTRL 0.01 10 1 0 0.00 5 S/H CONTROL 67.25ns -1 0 -0.01 -2 0 10 20 30 40 S/H CONTROL RISE TIME (ns) FIGURE 11. PEDESTAL vs S/H CONTROL RISE TIME 5 50 3.0E-7 TIME (ns) FIGURE 12. ACQUISITION TIME (0.01%, 0V TO 2V STEP) S/H CONTROL (V) OUTPUT OUTPUT (V) PEDESTAL ERROR (mV) 2 HA5351 Typical Performance Curves (Continued) OUTPUT 0.02 0.00 5 -0.02 51.4 ns -0.04 S/H CONTROL (V) OUTPUT (V) 10 0 0 20 40 TIME (ns) 60 80 FIGURE 13. HOLD MODE SETTLING TIME (±200µV) Die Characteristics DIE DIMENSIONS: PASSIVATION: 2530µm x 1760µm x 525µm 100 mils x 69 mils x 19 mils Type: Sandwich Passivation Nitride - 4kÅ, Undoped Si Glass (USG) - 8kÅ, Total - 12kÅ ±2kÅ METALLIZATION: SUBSTRATE POTENTIAL: Type: Metal 1: AlSiCu/TiW Thickness: Metal 1: 6kÅ ±750Å Type: Metal 2: AlSiCu Thickness: Metal 2: 16kÅ ±1.1kÅ VTRANSISTOR COUNT: 156 Metallization Mask Layout GND HA5351 GND GND V+ V+ V+ S/H CONTROL -IN VOUT VOUT +IN V- 6 V- V- HA5351 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 7 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 HA5351 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C A M MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS MIN 0.050 BSC 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 5.80 - H 8 0o 6.20 - 8 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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