STMICROELECTRONICS HCF4034

HCC/HCF4034B
8-STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL
INPUT/OUTPUT BUS REGISTER
..
.
.
.
..
.
..
..
BIDIRECTIONAL PARALLEL DATA INPUT
PARALLEL OR SERIAL INPUTS/PARALLEL
OUTPUTS
ASYNCHRONOUS OR SYNCHRONOUS PARALLEL DATA LOADING
PARALLEL DATA-INPUT ENABLE ON ”A”
DATA LINES (3-state output)
DATA RECIRCULATION FOR REGISTER EXPANSION
MULTIPACKAGE REGISTER EXPANSION
FULLY STATIC OPERATIONAL DC-TO-5MHz
(typ.) AT VDD = 10V
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N° 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Frit Seal Package)
M1
(Micro Package)
ORDER CODES :
HCC4034BF
HCF4034BEY
HCF4034BM1
PIN CONNECTIONS
DESCRIPTION
The HCC4034B (extended temperature range) and
HCF4034B (intermediate temperature range) are
monolithic integrated circuits, available in 24-lead
dual in-line plastic or ceramic package and plastic
micro package. The HCC/HCF4034B is a static
eight-stage parallel-or serial-input parallel-output
register. It can be used to : 1) bidirectionally transfer
parallel information between two buses ; 2) convert
serial data to parallel form and direct the parallel
data to either of twobuses ; 3) store (recirculate) parallel data, or 4) accept parallel data from either of two
buses and convert that data to serial form. Inputs
that control the operations include a single-phase
CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TOB-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/
SERIAL (P/S). Data inputs include 16 bidirectional
parallel data lines of which the eight A data lines are
inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the
A/B input. In addition, an input for SERIAL DATA is
also provided. All register stages are D-type masterslave flip-flops with separate master and slave clock
June 1989
1/16
HCC/HCF4034B
inputs generated internally to allow synchronous or
asynchronous data transfer from master to slave.
Isolation from external noise and the effects of loading is provided by output buffering.
PARALLEL OPERATION – A high P/S input signal
allows data transfer into the register via the parallel
data lines synchronously with the positive transition
of the clock provided the A/S input is low. If the A/S
input is high the transfer is independent of the clock.
The direction of data flow is controlled by the A/B
input. When this signal is high the A data lines are
inputs (and B data lines are outputs) ; a low A/B signal reverses the direction of data flow. The AE-input
is an additional feature which allows many registers
to feed data to a common bus. The A DATA lines are
enabled only when this signal is high. Data storage
through recirculation of data in each register stage
is accomplished by making the A/B signal high and
the AE signal low.
SERIALOPERATION – A low P/S signal allows serial data to transfer into the register synchronously
with the positive transition of the clock. The A/S input
is internally disabled when the register is in the serial
mode (asynchronous serial operation is not
allowed). The serial data appears as output data on
either the B lines (when A/B is high) or the A lines
(when A/B is low and the AE signal is high). Register
expansion can be accomplished by simply cascading HCC/HCF4034B packages.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V DD *
Parameter
Supply Voltage : HCC Types
HCF Types
Vi
Input Voltage
II
Value
Unit
– 0.5 to + 20
– 0.5 to + 18
V
V
– 0.5 to V DD + 0.5
V
DC Input Current (any one input)
± 10
mA
P tot
Total Power Dissipation (per package)
Dissipation per Output Transistor
for Top = Full Package-temperature Range
200
mW
100
mW
T op
Operating Temperature : HCC Types
HCF Types
– 55 to + 125
– 40 to + 85
°C
°C
T s tg
Storage Temperature
– 65 to + 150
°C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device
reliability.
2/16
HCC/HCF4034B
RECOMMENDED OPERATING CONDITIONS
Symbol
V DD
VI
T op
Parameter
Supply Voltage : HCC Types
HCF Types
Input Voltage
Operating Temperature : HCC Types
HCF Types
Value
Unit
3 to 18
3 to 15
V
V
0 to V DD
V
– 55 to + 125
– 40 to + 85
°C
°C
LOGIC DIAGRAMS
STEERING LOGIC
3/16
HCC/HCF4034B
LOGIC DIAGRAM AND TRUTH TABLE
REGISTER STAGE (1 of 8 stages)
INPUTS
CL
▲
M
CL
OUT
▲
S
D
Q
0
0
0
0
0
•
X
0
1
1
1
1
1
•
▲ = LEVEL CHANGE
•
= INVALID CONDI-
FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION
”A”
Enable
P/S
A/B
A/S
0
0
0
X
0
0
1
X
Serial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output
0
1
0
0
Parallel Mode ; ”B” Synch. Parallel Data Inputs, ”A” Parallel Data Outputs
Disabled
0
1
0
1
Parallel Mode ; ”B” Asynch. Parallel Data Inputs, ”A” Parallel Data Outputs
Disabled
0
1
1
0
Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,
Synch. Data Recirculation
0
1
1
1
Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,
Asynch. Data Recirculation
1
0
0
X
Serial Mode ; Synch. Serial Data Input, ”A” Parallel Data Output
1
0
1
X
Serial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output
1
1
0
0
Parallel Mode ; ”B” Synch. Parallel Data Input, ”A” Parallel Data Output
1
1
0
1
Parallel Mode ; ”B” Asynch. Parallel Data Input, ”A” Parallel Data Output
1
1
1
0
Parallel Mode ; ”A” Synch. Parallel Data Input, ”B” Parallel Data Output
1
1
1
1
Parallel Mode ; ”A” Asynch. Parallel Data Input, ”B” Parallel Data Outpu
Operation*
Serial Mode ; Synch. Serial Data Input, ”A” Parallel Data Outputs Disabled
* Outputs change at positive transition of clock in the serial mode and when the A/S control inputs is ”low” in the parallel
mode.
4/16
HCC/HCF4034B
TIMING DIAGRAM
5/16
HCC/HCF4034B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Symbol
IL
V OH
V OL
V IH
V IL
I OH
I OL
IIH , IIL
I OH
CI
Parameter
VI
(V)
0/ 5
HCC 0/10
Types 0/15
0/20
0/ 5
HCF
0/10
Types
0/15
Output High
0/ 5
Voltage
0/10
0/15
Output Low
5/0
Voltage
10/0
15/0
Input High
Voltage
Test Conditions
VO
|IO| V DD
(V)
(µA) (V)
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
5
10
15
5
10
15
5
10
15
18
± 0.1
±10–5 ± 0.1
±1
15
± 0.3
±10–5 ± 0.3
±1
0/18
18
± 0.4
±10–4 ± 0.4
± 12
0/15
15
± 1.0
±10–4 ± 1.0
± 7.5
Quiescent
Current
Input Low
Voltage
Output
Drive
Current
0/ 5
0/ 5
HCC
Types 0/10
0/15
0/ 5
0/ 5
HCF
Types 0/10
0/15
Output
0/ 5
HCC
Sink
0/10
Types
Current
0/15
0/ 5
HCF
0/10
Types
0/15
Input
HCC 0/18
Leakage
Types
Current
HCF
0/15
Types
3-State
HCC 0/18
Output
Types
Leakage HCF
0/15
Current
Types
Input Capacitance
Values
25°C
Min. Typ.
0.04
0.04
0.04
0.08
0.04
0.04
0.04
4.95
9.95
14.95
T Low *
Min. Max.
5
10
20
100
20
40
80
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
–2
– 0.64
– 1.6
– 4.2
– 1.53
– 0.52
– 1.3
– 3.6
0.64
1.6
4.2
0.52
1.3
3.6
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
0.4
0.5
1.5
<
<
<
<
<
<
<
<
<
<
<
<
1
1
1
1
1
1
1
1
1
1
1
1
3.5
7
11
– 1.6
– 0.51
– 1.3
– 3.4
– 1.36
– 0.44
– 1.1
– 3.0
0.51
1.3
3.4
0.44
1.1
3.0
– 3.2
–1
– 2.6
– 6.8
– 3.2
–1
– 2.6
– 6.8
1
2.6
6.8
1
2.6
6.8
T Hi gh *
Min. Max.
150
300
600
3000
150
300
600
4.95
9.95
14.95
0.05
0.05
0.05
0.05
0.05
0.05
3.5
7
11
1.5
1.5
3
3
4
4
– 1.15
– 0.36
– 0.9
– 2.4
– 1.1
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
0.36
0.9
2.4
Max.
5
10
20
100
20
40
80
Any Input
Any Input
5
7.5
* TLo w = – 55°C for HCC device : – 40°C for HCF device.
* THigh = + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5V min. with VDD = 15V.
6/16
Unit
µA
V
V
V
V
mA
mA
µA
µA
pF
HCC/HCF4034B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
tPHL , tPLH
Parameter
Propagation Delay Time :
A (B) Parallel Data in to
B (A) Parallel Data Out
tPLZ , tPHZ
t PZ L, t PZ H
3-state Propagation Delay Time
A/B or AE to ”A” OUT
tTHL, tT LH
Transition Time
ts etup
Data Setup Time Serial Data to
Clock
Parallel Data to Clock
tw
High-level Pulse Width, AE, P/S,
A/S
Test Conditions
Value
V DD (V)
Min.
tW
tr , t f*
Maximum Clock Frequency
Clock Pulse Width
Clock Input Rise or Fall Time
Max.
5
350
700
10
120
240
15
85
170
5
200
400
10
80
160
15
60
120
5
100
200
10
50
100
15
40
80
5
80
160
10
30
60
15
20
40
5
25
50
10
15
30
15
10
20
5
175
350
10
70
140
40
80
15
f CL
Typ.
5
2
4
10
5
10
15
7
ns
ns
ns
ns
ns
ns
MHz
14
5
125
250
10
50
100
15
35
70
5,10,15
Unit
15
ns
µs
* If more than one unit is cascaded. tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the
output of the driving stage for the estimated capacitive load.
7/16
HCC/HCF4034B
Typical Output Low (sink) Current Characteristics.
Minimum Output Low (sink) Current
teristics.
Charac-
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
TYPICAL APPLICATIONS
16-BIT PARALLEL IN/PARALLEL OUT PARALLEL IN/SERIAL OUT, SERIAL IN/PARALLEL OUT, SERIAL
IN/SERIAL OUT REGISTER.
8/16
HCC/HCF4034B
TYPICAL APPLICATIONS (continued)
16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER
FREQUENCY AND PHASE COMPARATOR.
TIMING DIAGRAM
9/16
HCC/HCF4034B
TYPICAL APPLICATIONS (continued)
SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS
A ”High” (”Low”) on the Shift Left/Shift Right input
allows serial data on the Shift Left Input (Shift Right
Input) to enter the register on the positive transition
of the clock signal. A ”high” on the ”A” Enable Input
disables the ”A” parallel data lines on Reg. 1 and 2
and enables the ”A” data lines on registers 3 and 4
and allows parallel data into registers 1 and 2. Other
logic schemes may be used in place of registers 3
and 4 for parallel loading. When parallel inputs are
not used Reg. 3 and 4 and associated logic are not
required.
* Shift Left input must be disabled during parallel
entry.
N-STAGE REGISTER WITH FIXED SERIAL OUTPUT LINE
10/16
HCC/HCF4034B
TYPICAL APPLICATIONS (continued)
SAMPLE AND HOLD REGISTER-SERIAL/PARALLEL IN-PARALLEL OUT
SINGLE-AND DOUBLE-BUS SYSTEMS
The ”A” enable (AE) and A/B signals control all combinations of transfer between the registers and bus systems.
11/16
HCC/HCF4034B
TEST CIRCUITS
Quiescent Device Current.
Input Leakage Current.
12/16
Noise Immunity.
HCC/HCF4034B
Plastic DIP24 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
a1
0.63
0.025
b
0.45
0.018
b1
0.23
b2
0.31
1.27
D
E
0.009
0.012
0.050
32.2
15.2
16.68
1.268
0.598
0.657
e
2.54
0.100
e3
27.94
1.100
F
MAX.
14.1
0.555
I
4.445
0.175
L
3.3
0.130
P043A
13/16
HCC/HCF4034B
Ceramic DIP24 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
32.3
MAX.
1.272
B
13.05
13.36
0.514
0.526
C
3.9
5.08
0.154
0.200
D
3
E
0.5
e3
0.118
1.78
0.020
27.94
0.070
1.100
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
I
1.17
1.52
0.046
0.060
L
0.22
0.31
0.009
0.012
M
1.52
2.49
0.060
0.098
15.8
0.606
0.622
N1
P
Q
4° (min.), 15° (max.)
15.4
5.71
0.225
P058C
14/16
HCC/HCF4034B
SO24 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
a1
MIN.
TYP.
MAX.
2.65
0.10
0.104
0.20
a2
0.004
0.007
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45° (typ.)
D
15.20
15.60
0.598
0.614
E
10.00
10.65
0.393
0.420
e
1.27
0.05
e3
13.97
0.55
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
S
8° (max.)
L
s
e3
b1
e
a1
b
A
a2
C
c1
E
D
13
1
12
F
24
15/16
HCC/HCF4034B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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