ETC HCPL-543K

Hermetically Sealed,
Very High Speed,
Logic Gate Optocouplers
HCPL-540X* HCPL-643X
5962-89570 5962-89571
HCPL-543X
Technical Data
*See matrix for available extensions.
Features
• Dual Marked with Device
Part Number and DSCC
Standard Microcircuit
Drawing
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Three Hermetically Sealed
Package Configurations
• Performance Guaranteed
over -55°C to +125 °C
• High Speed: 40 M bit/s
• High Common Mode
Rejection 500 V/µs
Guaranteed
• 1500 Vdc Withstand Test
Voltage
• Active (Totem Pole) Outputs
• Three Stage Output Available
• High Radiation Immunity
• HCPL-2400/30 Function
Compatibility
• Reliability Data
• Compatible with TTL, STTL,
LSTTL, and HCMOS Logic
Families
Applications
• Military and Space
• High Reliability Systems
• Transportation, Medical, and
Life Critical Systems
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Switching Power Supplies
• Isolated Bus Driver
(Networking Applications)(5400/1/K Only)
• Pulse Transformer
Replacement
• Ground Loop Elimination
• Harsh Industrial
Environments
• High Speed Disk Drive I/O
• Digital Isolation for A/D,
D/A Conversion
Description
These units are single and dual
channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level
H or K testing or from the
appropriate DSCC Drawing. All
devices are manufactured and
tested on a MIL-PRF-38534
certified line and are included in
the DSCC Qualified Manufacturers List, QML-38534 for
Hybrid Microcircuits.
Each channel contains an AlGaAs
light emitting diode which is
optically coupled to an integrated
high gain photon detector. This
combination results in very high
Truth Tables
(Positive Logic)
Multichannel Devices
Input
Output
On (H)
L
Off (L)
H
Single Channel DIP
Input
Enable
On (H)
L
Off (L)
L
On (H)
H
Off (L)
H
Output
L
H
Z
Z
Functional Diagram
Multiple Channel Devices
Available
VCC
VE
VO
GND
The connection of a 0.1 µ F bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
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2
data rate capability. The detector
has a threshold with hysteresis,
which typically provides 0.25 mA
of differential mode noise
immunity and minimizes the
potential for output signal
chatter. The detector in the single
channel units has a three state
output stage which eliminates the
need for a pull-up resistor and
allows for direct drive of a data
bus.
All units are compatible with TTL,
STTL, LSTTL, and HCMOS logic
families. The 35 ns pulse width
distortion specification guarantees a 10 MBd signaling rate at
+125°C with 35% pulse width
distortion. Figures 13 through 16
show recommended circuits for
reducing pulse width distortion
and optimizing the signal rate of
the product. Package styles for
these parts are 8 pin DIP through
hole (case outlines P), and
leadless ceramic chip carrier
(case outline 2). Devices may be
purchased with a variety of lead
bend and plating options. See
Selection Guide Table for details.
Standard Microcircuit Drawing
(SMD) parts are available for
each package and lead style.
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
listed in this data sheet, absolute
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the
figures are similar for all parts.
Occasional exceptions exist due
to package variations and limitations and are as noted. Additionally, the same package assembly
processes and materials are used
in all devices. These similarities
give justification for the use of
data obtained from one part to
represent other part’s performance for die related reliability and
certain limited radiation test
results.
Selection Guide–Package Styles and Lead Configuration Options
Package
Lead Style
Channels
Common Channel
Wiring
Agilent Part # & Options
Commercial
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped
Butt Cut/Gold Plate
Gull Wing/Soldered
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Class K SMD Part #
Prescript for all below
Either Gold of Solder
Gold Plate
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
8 Pin DIP
Through Hole
1
None
8 Pin DIP
Through Hole
2
VCC , GND
20 Pad LCCC
Surface Mount
2
None
HCPL-5400
HCPL-5401
HCPL-540K
Gold Plate
Option #200
Option #100
Option #300
HCPL-5430
HCPL-5431
HCPL-543K
Gold Plate
Option #200
Option #100
Option #300
HCPL-6430
HCPL-6431
HCPL-643K
Solder Pads
59628957001PX
8957001PC
8957001PA
8957001YC
8957001YA
8957001XA
59628957101PX
8957101PC
8957101PA
8957101YC
8957101YA
8957101XA
596289571022X
59628957002KPX
8957002KPC
8957002KPA
8957002KYC
8957002KYA
8957002KXA
59628957103KPX
8957103KPC
8957103KPA
8957103KYC
8957103KYA
8957103KXA
59628957104K2X
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89571022A
8957104K2A
3
Functional Diagrams
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
20 Pad LCCC
Surface Mount
2 Channels
15
VCC
1
VE
2
3
VO
4
GND
8
1
VCC
8
19
VO1
2
7
3
6
4
5
7
VO2
GND
VCC2
6
5
2
13
VO2
20
GND2
VO1
VCC1
12
10
3
GND1
7
8
Note: All DIP devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with
separate VCC and ground connections.
Outline Drawings
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
3.81 (0.150)
MIN.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
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0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
4
Leaded Device Marking
Agilent DESIGNATOR
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
• 50434
Leadless Device Marking
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Agilent CAGE CODE*
Agilent DESIGNATOR
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
• XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent CAGE CODE*
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
100
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead
finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
5° MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
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4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
5
Absolute Maximum Ratings
(No derating required up to +125°C)
Storage Temperature Range, TS .................................. -65°C to +150°C
Operating Temperature, TA ......................................... -55°C to +125°C
Case Temperature, TC ................................................................ +170°C
Junction Temperature, TJ .......................................................... +175°C
Lead Solder Temperature .............................................. 260°C for 10 s
Average Forward Current, IF AVG (each channel) ........................ 10 mA
Peak Input Current, IF PK (each channel) ............................... 20 mA[1]
Reverse Input Voltage, VR (each channel) ....................................... 3 V
Supply Voltage, VCC ............................................. 0.0 V min., 7.0 V max.
Average Output Current, IO ............................ -25 mA min., 25 mA max.
(each channel)
Output Voltage, VO (each channel) ..................... -0.5 V min., 10 V max.
Output Power Dissipation, PO (each channel) ........................... 130 mW
Package Power Dissipation, PD (each channel) ......................... 200 mW
Single Channel Product Only
Three State Enable Voltage, VE ........................... -0.5 V min., 10 V max.
8 Pin Ceramic DIP Single Channel Schematic
ANODE
VE
VO
CATHODE
Note enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must be connected
between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5400/01/0K ............................................................ (∆∆ ), Class 2
HCPL-5430/31/3K and HCPL-6430/31/3K ....................... (Dot), Class 3
Recommended Operating Conditions
Parameter
Input Current (High)
Supply Voltage, Output
Input Voltage (Low)
Fan Out (Each Channel)
Symbol
IF(ON)
VCC
VF(OFF)
N
Single Channel Product Only
High Level Enable Voltage
VEH
Low Level Enable Voltage
VEL
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Min.
6
4.75
–
–
Max.
10
5.25
0.7
5
Units
mA
V
V
TTL Loads
2.0
0
VCC
0.8
V
V
6
Electrical Characteristics
TA = -55°C to +125°C, 4.75 V ≤ VCC ≤ 5.25 V, 6 mA ≤ IF(ON) ≤ 10 mA, 0 V ≤ VF(OFF) ≤ 0.7 V,
unless otherwise specified.
Limits
Group A[10]
Parameter
Sym.
Test Conditions
Subgroups Min. Typ.* Max. Units Fig.
Low Level Output Voltage
VOL IOL = 8.0 mA (5 TTL Loads)
1, 2, 3
0.3
0.5
V
1
High Level Output Voltage VOH IOH = -4.0 mA
1, 2, 3
2.4
V
2
Output Leakage Current
IOHH VO = 5.25 V, VF = 0.7 V
1, 2, 3
100
µA
Logic High Single
ICCH VCC = 5.25 V, VE = 0 V
1, 2, 3
17
26
mA
Supply
Channel
(Single Channel Only)
Current
Dual Channel
34
52
Logic Low
Supply
Current
Single
Channel
Dual Channel
Input Forward Voltage
Input Reverse Breakdown Voltage
Input-Output Insulation
Leakage Current
Propagation Delay Time
Logic Low Output
Propagation Delay Time
Logic High Output
ICCL
1, 2, 3
VF
VR
IF = 10 mA
IR = 10 µA
II-O
VI-O = 1500 Vdc, RH = 45%,
t=5s
1, 2, 3
1, 2, 3
1.0
3.0
19
26
38
1.35
4.8
52
1.85
1
Notes
9
9
9
13
mA
V
V
1.0
µA
tPHL
9, 10, 11
33
60
ns
tPLH
9, 10, 11
30
60
ns
Pulse Width
PWD
Distortion
Logic High Common
|CMH| VCM = 50 VP-P, IF = 0 mA
Mode Transient Immunity
9, 10, 11
3
35
ns
9, 10, 11
500
3000
Logic Low Common
|CML| VCM = 50 VP-P, IF = 6 mA
Mode Transient Immunity
9, 10, 11
500
3000
4
13
9
9
2, 3
5,
6, 7
5,
6, 7
4, 9
4, 9
V/µs
5,
6, 7
11
V/µs
11
4, 9
5, 9,
11
5, 9,
11
Single Channel Product Only
Parameter
Sym.
Test Conditions
Limits
Group A[10]
Subgroups Min. Typ.* Max. Units Fig.
V
Logic High Enable
Voltage
Logic Low Enable
Voltage
Logic High Enable
Current
VEH
1, 2, 3
VEL
1, 2, 3
0.8
V
IEL
1, 2, 3
1, 2, 3
1, 2, 3
-0.28
20
100
-0.4
µA
Logic Low Enable
Current
VE = 2.4 V
VE = 5.25 V
VE = 0.4 V
mA
High Impedance State
Supply Current
High Impedance State
Output Current
ICCZ
VCC = 5.25 V,
VE = 5.25 V
VO = 0.4 V, VE = 2 V
VO = 2.4 V, VE = 2 V
VO = 5.25 V, VE = 2 V
1, 2, 3
22
28
mA
-20
20
100
µA
IEH
IOZL
IOZH
1, 2, 3
*All typical values are at VCC = 5 V, TA = 25°C, I F = 8 mA except where noted.
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2.0
Notes
7
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF = 8 mA, unless otherwise specified.
Parameter
Input Current Hysteresis
Input Diode Temperature
Coefficient
Resistance (Input-Output)
Capacitance (Input-Output)
Logic Low Short Circuit
Output Current
Logic High Short Circuit
Output Current
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Propagation Delay Skew
Power Supply Noise Immunity
Symbol
IHYS
∆VF
∆TA
RI-O
CI-O
IOSL
Typ.
0.25
-1.11
Units
mA
mV/°C
1012
0.6
65
Ω
pF
mA
IOSH
-50
mA
tr
tf
15
10
30
0.5
ns
ns
ns
VP-P
tPSK
PSNI
Single Channel Product Only
Parameter
Input Capacitance
Fig.
3
4
VI-O = 500 V
f = 1 MHz, VI-O = 0 V
VO = VCC = 5.25 V,
IF = 10 mA
VCC = 5.25 V, IF = 0 mA,
VO = GND
6, 9
48 Hz ≤ fac ≤ 50 MHz
Output Enable Time to Logic High
Output Enable Time to Logic Low
Output Disable Time from Logic High
Output Disable Time from Logic Low
tPZH
tPZL
tPHZ
tPLZ
Dual and Quad Channel Product Only
Input Capacitance
Input-Input Leakage Current
Input-Input Resistance
Input-Input Capacitance
CIN
II-I
RI-I
C I-I
15
0.5
1012
1.3
pF
nA
Ω
pF
f = 1 MHz, VO = 0 V
RH = 45%, VI-I = 500 Vdc
VI-I = 500 V
f = 1 MHz, VF = 0 V
Notes
2
2
6, 9
5
5
10
Typ. Units
Test Conditions
15
pF f = 1 MHz, VF = 0 V,
Pins 2 and 3
15
ns
30
ns
20
ns
15
ns
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Symbol
CIN
Test Conditions
VCC = 5 V
IF = 10 mA
12
7
Fig. Notes
8, 9
8, 9
8, 9
8, 9
8
8
8
8
Notes:
1. Not to exceed 5% duty factor, not to exceed 50 µsec pulse width.
2. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads
or terminals shorted together.
3. This is a momentary withstand test, not an operating condition.
4. tPHL propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5 V point on the falling
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the falling edge of the input current pulse to
the 1.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |tPHL - t PLH|.
5. CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state
(VO(MAX) < 0.8 V). CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the
logic high state (VO(MIN) > 2.0 V).
6. Duration of output short circuit time not to exceed 10 ms.
7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and
still remain in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.
8. Measured between adjacent input pairs shorted together for each multichannel device.
9. Each channel.
10. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,
and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
11. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to
limits specified for all lots not specifically tested.
12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of
optocouplers with the same part number that are all switching at the same time under the same operating conditions.
13. The HCPL-6430, HCPL-6431, and HCPL-643K dual channel parts function as two independent single channel units. Use the single
channel parameter limits.
Figure 1. Typical Logic Low Output
Voltage vs. Logic Low Output Current.
Figure 2. Typical Logic High Output
Voltage vs. Logic High Output Current.
Figure 3. Typical Output Voltage vs.
Input Forward Current.
Figure 4. Typical Diode Input Forward
Current Characteristic.
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9
PULSE GEN.
tr = tf = 5 ns
f = 500 kHz
25 % DUTY
CYCLE
VCC
VO
OUTPUT
MONITORING
NODE
D.U.T.
IF
5.0 V
1.3 KΩ
VCC
0.1 µF
INPUT
MONITORING
NODE
30 pF
C2
100 Ω
GND
C1
15 pF
2.5 KΩ
THE PROBE AND JIG CAPACITANCES
ARE REPRESENTED BY C1 AND C2.
ALL DIODES ARE 1N4150 OR EQUIVALENT.
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf .
Figure 6. Typical Propagation Delay
vs. Ambient Temperature.
PULSE
GENERATOR
ZO = 50 Ω
tr = tf = 5 ns
Figure 7. Typical Propagation Delay
vs. Input Forward Current.
VCC
D.U.T.
1
VCC 8
2
7
3
6
5.0 V
S1
0.1 µF
IF
4
GND
5
VO
D1
C1
30 pF
INPUT VE
MONITORING
NODE
1.3 KΩ
D2
2.5 KΩ
D3
D4
S2
Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL . (Single Channel Product Only).
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10
←
Figure 9. Typical Enable Propagation
Delay vs. Ambient Temperature.
(Single Channel Product Only).
IF
→
tK
P
S
Figure 10. Propagation Delay Skew,
tPSK , Waveform.
VCC = 5.0 V
B
D.U.T.
VCC
0.1 µF*
A
OUTPUT VO
MONITORING
NODE
+
VFF
–
GND
† CL
15 pF
VCM
VCC = 5.25 V
+
–
PULSE GEN.
IF
+
D.U.T.*
IO
–
VIN
2.1 V
ICC
VCC
100 Ω TYP.
0.01 µF
100 Ω
GND
CONDITIONS: IF = 10 mA
VDC = 3.0 V
IO = 25 mA
TA = +125 °C
* FOR SINGLE CHANNEL UNITS,
GROUND ENABLE PIN.
Figure 11. Test Diagram for Common Mode
Transient Immunity and Typical Waveforms.
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Figure 12. Operating Circuit for Burn-In and Steady State
Life Tests.
11
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Data Rate and PulseWidth Distortion
Definitions
Agilent Technologies’ Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Classes H
and K. Class H and Class K
devices are also in compliance
with DSCC drawings 596289570, and 5962-89571.
Propagation delay is a figure of
merit which describes the finite
amount of time required for a
system to translate information
from input to output when
shifting logic levels. Propagation
delay from low to high (tPLH)
specifies the amount of time
required for a system’s output to
change from a Logic 0 to a Logic
1, when given a stimulus at the
input. Propagation delay from
high to low (tPHL) specifies the
amount of time required for a
system’s output to change from a
Logic 1 to a Logic 0, when given
a stimulus at the input (see
Figure 5).
Testing consists of 100% screening and quality conformance
inspection to MIL-PRF-38534.
Applications
VCC1 = +5 V
226 Ω
30 pF
HCPL-5400
VCC
DATA
IN
274 Ω
A
VCC2 = 5 V
0.1 µF
TTL
LSTTL
STTL
HCMOS
GND 1
DATA
OUT
Y
GND
1
TOTEM
POLE
OUTPUT GATE
(e.g. 54AS1000)
GND 2
Y=A
Figure 13. Recommended HCPL-5400 Interface Circuit.
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2
When tPLH and tPHL differ in
value, pulse width distortion
results. Pulse width distortion is
defined as |tPHL - tPLH| and
determines the maximum data
rate capability of a distortionlimited system. Maximum pulse
width distortion on the order of
25-35% is typically used when
specifying the maximum data rate
capabilities of systems. The exact
figure depends on the particular
application (RS-232, PCM, T-1,
etc.).
These high performance optocouplers offer the advantages of
specified propagation delay (tPLH,
tPHL), and pulse width distortion
(|tPLH -t PHL|) over temperature
and power supply voltage ranges.
VCC1 = +5 V
HCPL-5400
DATA
IN
A
464 Ω
VCC2 = 5 V
VCC
0.1 µF
STTL
DATA
OUT
Y
TTL
LSTTL
STTL
GND 1
GND
OPEN
COLLECTOR
OUTPUT
GATE
(e.g. 54S05)
1
GND 2
Y=A
2
Figure 14. Alternative HCPL-5400 Interface Circuit.
226 Ω
30 pF
VCC1 = 5 V
HCPL-5430
DATA
IN A
VCC
274 Ω
TOTEM POLE
OUTPUT GATE
(e.g. 54AS1000)
TTL
LSTTL
STTL
HCMOS
DATA
OUT Y
TTL
LSTTL
STTL
HCMOS
274 Ω
DATA
IN A
VCC2 = +5 V
0.1 µF
DATA
OUT Y
GND
Y=A
GND 1
GND 2
226 Ω 30 pF
2
1
Figure 15. Recommended HCPL-5430 and HCPL-6430 Interface Circuit.
464 Ω
VCC1 = +5 V
HCPL-5430
VCC
DATA
IN A
STTL OPEN COLLECTOR
OUTPUT GATE
(e.g. 54AS05)
464 Ω
VCC2 = +5 V
0.1 µF
TTL
LSTTL
HCMOS
STTL
TTL
LSTTL
HCMOS
STTL
DATA
IN A
DATA
OUT Y
DATA
OUT Y
GND
Y=A
GND 2
GND 1
2
1
Figure 16. Alternative HCPL-5430 and HCPL-6430 Interface Circuit.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
Obsoletes 5968-0405E
5968-9403E (4/00)
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