AVAGO HCPL-520X

HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x,
5962-88768 and 5962-88769
Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers
Data Sheet
Description
Features
These units are single, dual and quad channel, hermeti�
cally sealed optocouplers. The products are capable of operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing
or from the appropriate DSCC Drawing. All devices are
manufactured and tested on a MIL-PRF-38534 certified
line and are included in the DSCC Qualified Manufactur�
ers List QML-38534 for Hybrid Microcircuits.
• Dual Marked with Device Part Number and DSCC
Standard Microcircuit Drawing
• �����������������
Manufactured and Tested
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on a MIL-PRF-38534 Certi�
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fied Line
• �����������
QML-38534, Class H and K
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Four Hermetically Sealed
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Package Configurations
• ������������
Performance Guaranteed
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over -55°C
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to +125°C
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• �����
Wide V
�CC Range (4.5 to 20 V)
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350 ns Maximum Propagation Delay
• �����
CMR: > 10,000 V/µs Typical
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• �����
1500 Vdc Withstand Test Voltage
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Three State Output Available
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High Radiation Immunity
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HCPL-2200/31 Function
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Compatibility
• ������������
Reliability Data Available
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Compatible with LSTTL, TTL, and
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CMOS Logic
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Each channel contains an AlGaAs light emitting diode
which is optically coupled to an integrated high gain
photon detector. The detector has a threshold with hys�
teresis which provides differential mode noise immunity and eliminates the potential for output signal chatter.
The detector in the single channel units has a tri-state
output stage which allows for direct connection to data
buses. The output is noninverting. The detector IC has an internal shield that provides a guaranteed common
mode transient immunity of up to 10,000 V/µs. Improved
power supply rejection eliminates the need for special
power supply bypass precautions.
Applications
•
•
•
•
•
•
•
•
•
Military and Space
High Reliability Systems
Transportation and Life Critical Systems
High Speed Line Receiver
Isolated Bus Driver (Single Channel)
Pulse Transformer Replacement
Ground Loop Elimination
Harsh Industrial Environments
Computer-Peripheral Interfaces
Note: A 0.1 mF bypass capacitor must be connected between VCC and GND pins.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
Truth Tables
Multiple Channel Devices Available
(Positive Logic)
Multichannel Devices
V CC
VO
VE
GND
Package styles for these parts are 8 pin DIP through hole
(case outline P), 16 pin DIP flat pack (case outline F), and
leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating
options, see Selection Guide Table for details. Standard
Microcircuit Drawing (SMD) parts are available for each
package and lead style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and perfor�
mance characteristics shown in the figures are identical
for all parts. Occasional exceptions exist due to package
variations and limitations and are as noted. Additionally, the same package assembly processes and materials are
used in all devices. These similarities give justification for
the use of data obtained from one part to represent other
part’s performance for die related reliability and certain
limited radiation test results.
Input
Output
On (H)
H
Off (L)
L
Single Channel Devices
Input
Enable
Output
On (H)
H
Z
Off (L)
H
Z
On (H)
L
H
Off (L)
L
L
Functional Diagrams
1
2
3
4
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
20 Pad LCCC
Through Hole
Through Hole
Unformed Leads
Surface Mount
1 Channel
2 Channels
4 Channels
2 Channels
V CC
VO
VE
GND
8
1
7
2
6
3
5
4
V CC
V O1
V O2
GND
8
7
6
5
15
16
1
V CC2
2
V CC
15
19
3
V O1
14
20
4
V O2
13
5
V O3
12
6
V O4
11
7
GND
10
8
9
13
V O2
GND 2
2
V O1
V CC1
12
10
3
GND 1
7
8
Note: Multichannel DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 6. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground connections.
Selection Guide–Package Styles and Lead Configuration Options
Package
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
20 Pad LCCC
Lead Style
Through Hole
Through Hole
Unformed Leads
Surface Mount
Channels
1
2
4
2
None
VCC GND
VCC GND
None
Commercial
HCPL-5200
HCPL-5230
HCPL-6250
HCPL-6230
MIL-PRF-38534 Class H
HCPL-5201
HCPL-5231
HCPL-6251
HCPL-6231
MIL-PRF-38534 Class K
HCPL-520K
HCPL-523K
HCPL-625K
HCPL-623K
Standard Lead Finish
Gold Plate
Gold Plate
Gold Plate
Solder Pads *
Solder Dipped*
Option 200
Option 200
Butt Joint/Gold Plate
Option 100
Option 100
Gull Wing/Soldered*
Option 300
Option 300
Prescript for all below
5962-
5962-
5962-
5962-
Either Gold or Soldered
8876801PX
8876901PX
8876903FX
88769022X
Gold Plate
8876801PC
8876901PC
8876903FC
Solder Dipped*
8876801PA
8876901PA
Butt Joint/Gold Plate
8876801YC
8876901YC
Butt Joint/Soldered*
8876801YA
8876901YA
Gull Wing/Soldered*
8876801XA
8876901XA
Prescript for all below
5962-
5962-
5962-
5962-
Either Gold or Soldered
8876802KPX
8876904KPX
8876906KFX
8876905K2X
Gold Plate
8876802KPC
8876904KPC
8876906KFC
Solder Dipped*
8876802KPA
8876904KPA
Butt Joint/Gold Plate
8876802KYC
8876904KYC
Butt Joint/Soldered*
8876802KYA
8876904KYA
Gull Wing/Soldered*
8876802KXA
8876904KXA
Common Channel Wiring
Avago Technologies’ Part Numbers and Options
Class H SMD Part Number
88769022A
Class K SMD Part Number
* Solder contains lead
8876905K2A
Outline Drawings
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
3.81 (0.150)
MIN.
0.51 (0.020)
MAX.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
16 Pin Flat Pack, 4 Channels
2.29 (0.090)
MAX.
7.24 (0.285)
6.99 (0.275)
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
2.85 (0.112)
MAX.
0.89 (0.035)
0.69 (0.027)
8.13 (0.320)
MAX.
5.23
(0.206)
MAX.
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.31 (0.012)
0.23 (0.009)
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
Leaded Device Marking
AVAGO Designator
AVAGO P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
AVAGO FSCN*
*QUALIFIED PARTS ONLY
Leadless Device Marking
AVAGO Designator
AVAGO P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
*QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
AVAGO FSCN*
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly.
This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP.
DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder
dipped terminals as a standard feature.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial
and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
5˚ MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Note: Solder contains lead
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature Range
TS
-65°
+150°
C
Operating Ambient Temperature
TA
-55°
+125°
C
Junction Temperature
TJ
+175°
C
Case Temperature
TC
+170°
C
260° for 10 s
C
IF AVG
8
mA
Peak Input Current, each channel
IFPK
20 [1]
mA
Reverse Input Voltage, each channel
VR
3
V
Average Output Current, each channel
IO
15
mA
Lead Solder Temperature
(1.6 mm below seating plane)
Average Forward Current, each channel
Supply Voltage
VCC
0.0
20
V
Output Voltage, each channel
VO
-0.3
20
V
Package Power Dissipation, each channel
PD
200
mW
20
V
Single Channel Product Only
Tri-State Enable Voltage
VE
-0.3
8 Pin Ceramic DIP Single Channel Schematic
Note enable pin 6. An external 0.01 µF to 0.1 µF bypass capacitor is recommended between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5200/01/0K and HCPL-6230/31/3K
(D), Class 1
HCPL-5230/31/3K and HCPL-6250/51/5K
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
VCC
4.5
20
V
Input Current, High Level, each channel
IFH
2
8
mA
Input Voltage, Low Level, each channel
VFL
0
0.8
V
Fan Out (TTL Load), each channel
N
4
Single Channel Product Only
High Level Enable Voltage
VEH
2.0
20
V
Low Level Enable Voltage
VEL
0
0.8
V
Electrical Characteristics
TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 20 V, 2 mA ≤ IF(ON) ≤ 8 mA, 0 V ≤ VF(OFF) ≤ 0.8 V, unless otherwise specified.
Limits
Symbol
Group A,
Sub-groups[11]
Logic Low Output Voltage
VOL
1, 2, 3
IOL = 6.4 mA (4 TTL Loads)
Logic High Output Voltage
VOH
1, 2, 3
IOH = -2.6 mA,
(**VOH = VCC - 2.1 V)
NA
IOH = -0.32 mA
Parameter
Output Leakage
Current (VOUT > VCC)
IOHH
1, 2, 3
Test Conditions
VO = 5.5 V
VO = 20 V
Logic
Low
Supply
Current
Logic
High
Supply Current
Single
Channel
ICCL
1, 2, 3
VCC = 5.5 V
VCC = 20 V
Dual Channel
VCC = 5.5 V
Quad
Channel
VCC = 5.5 V
Single
Channel
VCC = 20 V
VCC = 20 V
ICCH
1, 2, 3
VCC = 5.5 V
VCC = 20 V
Dual
Channel
VCC = 5.5 V
Quad
Channel
VCC = 5.5 V
Logic Low Short Circuit
Output Current
VCC = 20 V
VCC = 20 V
IOSL
1, 2, 3
VO = VCC =
5.5 V
2.4
Typ.*
Max.
Units
Fig.
Notes
0.5
V
1, 3
2
V
2, 3
2
**
3.1
IF = 8 mA
VCC =
4.5 V
100
VF1 = VF2
= 0 V
4.5
6
5.3
7.5
9.0
12
10.6
15
VF1 = VF2
= VF3 =
VF4 =0 V
14
24
17
30
IF = 8mA
VE =
Don’t
Care
2.9
4.5
3.3
6
IF1 = IF2 =
8mA
5.8
9
6.6
12
IF1 = IF2 =
IF3 = IF4 =
8mA
9
18
11
24
VF = 0 V
mA
2
500
VF = 0 V
VE =
Don’t
Care
VO = VCC = 20 V
20
mA
mA
mA
2, 3
mA
2, 3
35
Logic High Short Circuit
Output Current
IOSH
1, 2, 3
Input Forward Voltage
VF
1, 2, 3
IF = 8 mA
1.0
Input Reverse
Breakdown Voltage
BVR
1, 2, 3
IR = 10 mA
3
Input-Output Insulation
Leakage Current
II-O
1
VI-O = 1500 Vdc, t = 5s, RH ≤ 65%, TA = 25°C
Logic High Common Mode
Transient Immunity
|CMH|
9, 10, 11
IF = 2 mA, VCM = 50 VP-P
1000 10,000
V/ms
9
2, 6, 12
Logic Low Common Mode
Transient Immunity
|CML|
9, 10, 11
IF = 0 mA, VCM = 50 VP-P
1000 10,000
V/ms
9
2, 6, 12
Propagation Delay Time to Logic Low
tPHL
9, 10, 11
173
350
ns
5, 6
2, 7
Propagation Delay Time to Logic High
tPLH
9, 10, 11
118
350
ns
5, 6
2, 7
VCC = 5.5V
Min.
VCC = 20 V
IF = 8 mA
VO = GND
-10
-25
1.3
1.8
1.0
V
4
2
V
2
mA
4, 5
Electrical Characteristics - Single Channel Product Only
TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 20 V, 2 mA ≤ IF (ON) ≤ 8 mA, 0 V ≤ VF(OFF) ≤ 0.8 V, 2.0 V ≤ VEH ≤ 20 V, 0 V ≤ VEL ≤ 0.8 V, unless otherwise specified.
Parameter
High Impedance
State Output Current
Limits
Symbol
Group A,
Sub-groups[11]
IOZL
1,2,3
VO = 0.4 V
IOZH
1,2,3
VO = 2.4 V
Max.
Units
VEN = 2 V, VF = 0 V
-20
mA
VEN = 2 V, IF = 8 mA
20
mA
Test Conditions
VO = 5.5 V
Min.
Typ.*
100
VO = 20 V
Logic High Enable Voltage
VEH
1, 2, 3
Logic Low Enable Voltage
VEL
1, 2, 3
Logic High Enable Current
IEH
1, 2, 3
Logic Low Enable Current
IEL
V
0.8
V
VEN = 2.7 V
20
mA
VEN = 5.5 V
100
VEN = 0.4 V
*All typical values are at VCC = 5 V, TA = 25°C, IF(ON) = 5 mA unless otherwise specified.
500
2.0
VEN = 20 V
1, 2, 3
Fig.
0.004
250
-0.32
mA
Notes
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF(ON) = 5 mA unless otherwise specified.
Parameter
Symbol
Test Conditions
Typ.
Units
Fig.
Notes
Input Current Hysteresis
IHYS
VCC = 5 V
0.07
mA
3
2
Input Diode Temperature
Coefficient
DVF
DTA
IF = 8 mA
-1.25
mV/°C
2
Resistance (Input-Output)
RI-O
VI-O = 500 Vdc
1013
W
2, 8
Capacitance (Input-Output)
CI-O
f = 1 MHz
2.0
pF
2, 8
Input Capacitance
CIN
VF = 0 V, f = 1 MHz
20
pF
2, 10
Output Rise Time (10-90%)
tr
45
ns
5, 7
2
Output Fall Time (90-10%)
tf
10
ns
5, 7
2
Output Enable Time to Logic High
tPZH
30
ns
8
Output Enable Time to Logic Low
tPZL
30
ns
8
Output Disable Time from Logic High
tPHZ
45
ns
8
Output Disable Time from Logic Low
tPLZ
55
ns
8
Single Channel Product Only
Multi-Channel Product Only
Input-Input Insulation Leakage Current
II-I
RH ≤ 65%, VI-I = 500 V, t = 5 s
0.5
nA
9
Resistance (Input-Input)
RI-I
VI-I = 500 V
1013
W
9
Capacitance (Input-Input)
CI-I
f = 1 MHz
1.5
pF
9
Notes:
1. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.
2. Each channel of a multichannel device.
3. Duration of output short circuit time not to exceed 10 ms.
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or ter�
minals shorted together.
5. This is a momentary withstand test, not an operating condition.
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V).
7. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the
trailing edge of the output pulse.
8. Measured between each input pair shorted together and all output connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each multichannel device.
10.Zero-bias capacitance measured between the LED anode and cathode.
11.Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125, and –55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
12.Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits speci�
fied for all lots not specifically tested.
10
Figure 1. Typical Logic Low Output Voltage vs. Temperature.
Figure 2. Typical Logic High Output Current vs. Temperature.
Figure 3. Output Voltage vs. Forward Input Current.
Figure 4. Typical Diode Input Forward Characteristic.
V CC
PULSE GEN.
t r = t f = 5 ns
t = 100 kHz
10 % DUTY
CYCLE
OUTPUT VO
MONITORING
NODE
D.U.T.
V CC
IF
INPUT
MONITORING
NODE
Rf
D1
VO
VE
5V
D2
CL=
15 pF
GND
619 Ω
5K
D3
D4
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C L .
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
11
Figure 6. Typical Propagation Delay vs. Temperature.
Figure 7. Typical Rise, Fall Time vs. Temperature.
C L = 15 pF INCLUDING PROBE
AND JIG CAPACITANCE.
PULSE
GENERATOR
Z O = 50 Ω
t r = t f = 5 ns
+5 V
V CC
VO
D.U.T.
V CC
619 Ω
D1
VO
IF
S1
D2
CL
VE
GND
5 KΩ
D3
D4
INPUT VO
MONITORING
NODE
S2
Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL.
A
VCC
D.U.T.
B
VCC
R IN
VO
VE
V FF
OUTPUT VO
MONITORING
NODE
0.1 µF
BYPASS
GND
V CM
+
PULSE GEN.
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
12
V CC1
(+5 V)
V CC2
(4.5 TO 20 V)
665 Ω
V CC1
(+5 V)
750 Ω
D.U.T.
VCC
RL
VO
DATA
INPUT
TTL OR
LSTTL
CMOS
V CC
DATA
INPUT
VE
GND
TOTEM
POLE
OUTPUT
GATE
V CC2
5V
10 V
15 V
20 V
1
RL
1.1 K
2.37 K
3.83 K
5.11 K
D.U.T.
DATA
OUTPUT
TTL OR
LSTTL
TOTEM
POLE
OUTPUT
GATE
GND
2
Figure 11. Recommended LED Drive Circuit.
Figure 10. LSTTL to CMOS Interface Circuit.
V CC1
(+5 V)
619 Ω
D.U.T.
V CC
4.02 KΩ
DATA
INPUT
TTL OR
LSTTL
GND
OPEN
COLLECTOR
GATE
Figure 12. Series LED Drive with Open Collector Gate
(4.02 kΩ Resistor Shunts IOH from the LED).
V CC2
(+5 V)
DATA
OUTPUT
V CC1
(+5 V)
665 Ω
665 Ω
V CC
DATA
INPUT
TOTEM
POLE
OUTPUT
GATE
TTL OR
LSTTL
DATA
INPUT
UP TO 16 LSTTL
LOADS
OR 4 TTL LOADS
D.U.T.
0.1
µF
DATA
OUTPUT
TTL OR
LSTTL
GND
1
TOTEM
POLE
OUTPUT
GATE
1
Figure 13. Recommended LSTTL to LSTTL Circuit.
UP TO 16 LSTTL
LOADS
OR 4 TTL LOADS
2
V CC + 20 V
D.U.T.*
V CC
IF
IO
+V IN
1.90 V
100 Ω
VE
0.01 µF
1200 Ω
GND
CONDITIONS: I F = 8 mA
IO = -14 mA
MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in com�
pliance with MIL-PRF-38534 Classes H and K. Class H and Class K devices are also in compliance with DSCC
drawings 5962-88768 and 5962-88769.
Testing consists of 100% screening and quality confor�
mance inspection to MIL-PRF-38534.
T A = +125 ˚C
*ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 14. Single Channel Operating Circuit for Burn-in and Steady State
Life Tests.
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved.
5989-2666EN - April 4, 2007