6N134,* 81028, HCPL-563X, HCPL-663X, HCPL-565X, 5962-98001, HCPL-268K, HCPL-665X, 5962-90855, HCPL-560X Hermetically Sealed, High Speed, High CMR, Logic Gate Optocouplers Data Sheet *See matrix for available extensions. Description Features These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropriate DLA Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DLA Qualified Manufacturers List QML-38534 for Hybrid Microcircuits. Quad channel devices are available by special order in the 16 pin DIP through hole packages. Dual marked with device part number and DLA drawing number Manufactured and tested on a MIL-PRF-38534 Certified Line QML-38534, Class H and K Five hermetically sealed package configurations Performance guaranteed over full military temperature range: -55°C to +125°C High speed: 10 Mbd typical CMR: > 10,000 V/μs typical 1500 Vdc withstand test voltage 2500 Vdc withstand test voltage for HCPL-565X High radiation immunity 6N137, HCPL-2601, HCPL-2630/31 function compatibility Reliability data TTL circuit compatibility Functional Diagram VCC VE VOUT GND Applications Multiple channel devices available Truth Table (Positive Logic) Multichannel Devices Input Output On (H) L Off (L) H Single Channel DIP Input Enable Output On (H) H L Off (L) H H On (H) L H Off (L) L H Military and aerospace High reliability systems Transportation, medical, and life critical systems Line receiver Voltage level shifting Isolated input line receiver Isolated output line driver Logic ground isolation Harsh industrial environments Isolation for computer, communication, and test equipment systems The connection of a 0.1 μF bypass capacitor between VCC and GND is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Each channel contains a GaAsP light emitting diode which is optically coupled to an integrated high speed photon detector. The output of the detector is an open collector Schottky clamped transistor. Internal shields provide a guaranteed common mode transient immunity specification of 1000 V/μs. For Isolation Voltage applications requiring up to 2500 Vdc, the HCPL-5650 family is also available. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P and E respectively), and 16 pin surface mount DIP flat pack (case outline F), leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Table for details. Standard Microcircuit Drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations, and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other parts’ performance for reliability and certain limited radiation test results. Selection Guide–Package Styles and Lead Configuration Options Package 16 Pin DIP 8 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC Lead Style Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface Mount Channels 2 1 2 2 4 2 Common Channel Wiring VCC, GND None VCC, GND VCC, GND VCC, GND None Withstand Test Voltage 1500 Vdc 1500 Vdc 1500 Vdc 2500 Vdc 1500 Vdc 1500 Vdc Commercial 6N134[1] HCPL-5600 HCPL-5630 HCPL-5650 HCPL-6650 HCPL-6630 MIL-PRF-38534, Class H 6N134/883B HCPL-5601 HCPL-5631 HCPL-5651 HCPL-6651 HCPL-6631 MIL-PRF-38534, Class K HCPL-268K HCPL-560K HCPL-563K HCPL-665K HCPL-663K Standard Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Gold Plate Solder Pads* Solder Dipped* Option #200 Option #200 Option #200 Option #200 Butt Cut/Gold Plate Option #100 Option #100 Option #100 Gull Wing/Soldered* Option #300 Option #300 Option #300 Prescript for all below None 5962- None None None None Gold Plate 8102801EC 9085501HPC 8102802PC 8102805PC 8102804FC Solder Dipped* 8102801EA 9085501HPA 8102802PA 8102805PA Butt Cut/Gold Plate 8102801UC 9085501HYC 8102802YC Butt Cut/Soldered* 8102801UA 9085501HYA 8102802YA Gull Wing/Soldered* 8102801TA 9085501HXA 8102802ZA Prescript for all below 5962- 5962- 5962- 5962- Gold Plate 9800101KEC 9085501KPC 9800102KPC 9800104KFC Solder Dipped* 9800101KEA 9085501KPA 9800102KPA Butt Cut/Gold Plate 9800101KUC 9085501KYC 9800102KYC Butt Cut/Soldered* 9800101KUA 9085501KYA 9800102KYA Gull Wing/Soldered* 9800101KTA 9085501KXA 9800102KZA Avago Part # & Options Class H SMD Part # 81028032A Class K SMD Part # *Solder contains lead. Note: 1. JEDEC registered part. 2 59629800103K2A Functional Diagrams 16 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC Through Hole Through Hole Through Hole Unformed Leads Surface Mount 2 Channels 1 Channel 2 Channels 4 Channels 2 Channels 1 2 V CC 15 3 V O1 14 4 5 VE 2 13 V O2 11 GND V OUT 3 12 6 7 V CC 1 4 10 GND 8 1 7 2 VCC VO1 VO2 3 6 4 5 GND 7 6 5 2 V CC 15 3 V O1 14 4 V O2 13 5 V O3 12 6 V O4 11 7 GND 10 8 9 8 8 15 16 1 16 VCC2 19 VO2 20 2 GND 2 VO1 VCC1 3 GND 1 7 8 9 Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.” Outline Drawings ;;;;; 16 Pin DIP Through Hole, 2 Channels 20.06 (0.790) 20.83 (0.820) 8.13 (0.320) MAX. 0.89 (0.035) 1.65 (0.065) 0.51 (0.020) MIN. 3.81 (0.150) MIN. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Leaded Device Marking Avago LOGO Avago P/N DLA SMD [1] DLA SMD [1] PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX * 50434 COMPLIANCE INDICATOR, [1] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE [1] * QUALIFIED PARTS ONLY Leadless Device Marking A QYYWWZ XXXXXX * XXXX XXXXXX XXX 50434 Avago LOGO Avago P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. * QUALIFIED PARTS ONLY Notes 1. Qualified parts only 3 4.45 (0.175) MAX. COMPLIANCE INDICATOR, [1] DATE CODE, SUFFIX (IF NEEDED) DLA SMD [1] DLA SMD [1] Avago CAGE CODE [1] 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 13 12 10 Outline Drawings (continued) 8 Pin DIP Through Hole, 1 and 2 Channels 8 Pin DIP Through Hole, 2 Channels 2500 Vdc Withstand Test Voltage 9.40 (0.370) 9.91 (0.390) 8.13 (0.320) MAX. 9.40 (0.370) 9.91 (0.390) 8.13 (0.320) MAX. 0.76 (0.030) 1.27 (0.050) 7.16 (0.282) 7.57 (0.298) 0.76 (0.030) 1.27 (0.050) 7.16 (0.282) 7.57 (0.298) 4.32 (0.170) MAX. 3.81 (0.150) MIN. 0.51 (0.020) MIN. 0.51 (0.020) MAX. 5.08 (0.200) MAX. 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MIN. 3.81 (0.150) MIN. 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 2.29 (0.090) 2.79 (0.110) 2.29 (0.090) 2.79 (0.110) 7.36 (0.290) 7.87 (0.310) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 16 Pin Flat Pack, 4 Channels 20 Terminal LCCC Surface Mount, 2 Channels 7.24 (0.285) 6.99 (0.275) 8.70 (0.342) 9.10 (0.358) 2.29 (0.090) MAX. 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 11.13 (0.438) 10.72 (0.422) 1.27 (0.050) REF. 0.46 (0.018) 0.36 (0.014) 8.13 (0.320) MAX. 2.85 (0.112) MAX. 0.31 (0.012) 0.23 (0.009) 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 0.88 (0.0345) MIN. 9.02 (0.355) 8.76 (0.345) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 4 TERMINAL 1 IDENTIFIER 2.16 (0.085) METALLIZED CASTILLATIONS (20 PLCS) 1.78 (0.070) 2.03 (0.080) 0.64 (0.025) (20 PLCS) 0.51 (0.020) 1.52 (0.060) 2.03 (0.080) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX. Hermetic Optocoupler Options Option Description 100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MAX. 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and 16 pin DIP. DLA Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped leads. 4.57 (0.180) MAX. 0.51 (0.020) MIN. 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) MAX. 5° MAX. 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Solder contains lead. 5 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) 1.07 (0.042) 1.32 (0.052) Absolute Maximum Ratings No derating required up to +125°C. Parameter Symbol Min. Max. Units Storage Temperature TS -65 +150 °C Operating Temperature TA -55 +125 °C Case Temperature TC +170 °C Junction Temperature TJ +175 °C 260 for 10 sec °C Lead Solder Temperature Peak Forward Input Current (each channel, ≤1 ms duration) IF(PEAK) 40 mA Average Input Forward Current (each channel) IF(AVG) 20 mA 35 mW Reverse Input Voltage (each channel VR 5 V Supply Voltage (1 minute maximum) VCC 7.0 V Output Current (each channel) IO 25 mA Output Voltage (each channel) VO 7* V Output Power Dissipation (each channel) PO 40 mW Package Power Dissipation (each channel) PD 200 mW VE 5.5 V Input Power Dissipation (each channel) *Selection for higher output voltages up to 20 V is available Single Channel Product Only Enable Input Voltage 8 Pin Ceramic DIP Single Channel Schematic Note enable pin 7. An external 0.01 μF to 0.1 μF bypass capacitor must be connected between VCC and ground for each package type. ESD Classification (MIL-STD-883, Method 3015) HCPL-5600/01/0K (), Class 1 6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51, HCPL-6630/31/3K and HCPL-6650/51/5K (Dot), Class 3 Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level, Each Channel IFL 0 250 μA Input Current, High Level, Each Channel* IFH 10 20 mA Supply Voltage, Output VCC 4.5 5.5 V Fan Out (TTL Load) Each Channel N *Meets or exceeds DLA SMD and JEDEC requirements. 6 6 Recommended Operating Conditions (cont’d.) Single Channel Product Only[10] Parameter Symbol Min. Max. Units High Level Enable Voltage VEH 2.0 VCC V Low Level Enable Voltage VEL 0 0.8 V Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified) Parameter Symbol Test Conditions High Level Output Current IOH* VCC = 5.5 V, VO = 5.5 V, IF = 250 μA Low Level Output Voltage VOL* Current Transfer Ratio Logic High Supply Current Logic low Supply Current Single Channel Group A[13] Subgroups Limits Min. Typ.** Max. Units Fig. Note 1, 2, 3 20 250 μA 1 1 VCC = 5.5 V, IF = 10 mA, IOL (Sinking) = 10 mA 1, 2, 3 0.3 0.6 V 2 1, 9 hF CTR VO = 0.6 V, IF = 10 mA, VCC = 5.5 V 1, 2, 3 ICCH* VCC = 5.5 V, IF = 0 mA 1, 2, 3 100 1 9 14 mA 1 6 Dual Channel VCC = 5.5 V, IF1 = IF2 = 0 mA 18 28 mA Quad Channel VCC = 5.5 V, IF1 = IF2 = IF3 = IF4 = 0 mA 25 42 mA 13 18 mA 1 6 Single Channel ICCL* VCC = 5.5 V, IF = 20 mA 1, 2, 3 Dual Channel VCC = 5.5 V, IF1 = IF2 = 20 mA 26 36 mA Quad Channel VCC = 5.5 V, IF1 = IF2 = IF3 = IF4 = 20 mA 33 50 mA 1, 2, 3 1.5 1.9 V 3 1, 15 1, 2 1.55 1.75 V 3 1, 16 Input Forward Voltage VF* IF = 20 mA 3 Input Reverse Breakdown Voltage BVR* IR = 10 μA Input-Output Leakage Current II-O* RH ≤ 65% TA = 25°C t=5s Capacitance Between Input/ Output CI-O 1, 2, 3 1.85 5 V 1 VI-O = 1500 Vdc 1 1.0 μA 2, 8, 17 VI-O = 2500 Vdc 1 1.0 μA 18 4.0 pF 1, 3, 14 f = 1 MHz, TC = 25°C *Identified test parameters for JEDEC registered parts. **All typical values are at VCC = 5 V, TA = 25°C. 7 % 4 1.0 Electrical Characteristics, (cont’d) TA = -55°C to +125°C unless otherwise specified Limits Group A[13] Subgroups Parameter Symbol Test Conditions Propagation Delay Time to High Output Level tPLH* VCC = 5 V, RL = 510 Ω, CL = 50 pF, IF = 13 mA Propagation Delay Time to Low Output Level tPHL* Min. 9 Typ.** Max. Units Fig. Note 60 100 ns 4, 5, 6 1, 5 10, 11 140 9 55 10, 11 100 ns 120 RL = 510 Ω, CL = 50 pF, IF = 13 mA 9, 10, 11 |CMH| VCM = 50 V (PEAK), VCC = 5 V, VO (min.) = 2 V, RL = 510 Ω, IF = 0 mA 9, 10, 11 1000 >10000 V/μs 7 1, 7, 14 |CML| VCM = 50 V (PEAK), VCC = 5 V, VO (max.) = 0.8 V, RL = 510 Ω, IF = 10 mA 9, 10, 11 1000 >10000 V/μs 7 1, 7, 14 1, 2, 3 -2.0 -1.45 mA 2.0 Output Rise Time tLH Output Fall Time tHL Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level 35 90 35 40 ns 1 Single Channel Product Only Low Level Enable Current IEL VCC = 5.5 V, VE = 0.5 V High Level Enable Voltage VEH 1, 2, 3 Low Level Enable Voltage VEL 1, 2, 3 V 0.8 10 V *Identified test parameters for JEDEC registered part. **All typical values are at VCC = 5 V, TA = 25°C. Typical Characteristics, TA = 25°C, VCC = 5 V Parameter Sym. Typ. Units Test Conditions Fig. Note Input Capacitance CIN 60 pF VF = 0 V, f = 1 MHz 1 Input Diode Temperature Coefficient ΔVF ΔTA -1.5 mV/°C IF = 20 mA 1 Resistance (Input-Output) RI-O 1012 Ω VI-O = 500 V 2 Propagation Delay Time of Enable from VEH to VEL tELH 35 ns Propagation Delay Time of Enable from VEL to VEH tEHL 35 ns RL = 510 Ω, CL = 50 pF IF = 13 mA, VEH = 3 V, VEL = 0V Input-Input Leakage Current II-I 0.5 nA Relative Humidity ≤ 65% VI-I = 500 V, t = 5 s 4 Resistance (Input-Input) RI-I 1012 Ω VI-I = 500 V 4 Capacitance (Input-Input) CI-I 0.55 pF f = 1 MHz 4 Single Channel Product Only 8, 9 1, 11 1, 12 Dual and Quad Channel Product Only 8 Notes: 1. Each channel. 2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 3. Measured between each input pair shorted together and all output connections for that channel shorted together. 4. Measured between adjacent input pairs shorted together for each multichannel device. 5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single channel parameter limits for each channel. 7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 8. This is a momentary withstand test, not an operating condition. 9. It is essential that a bypass capacitor (0.01 to 0.1 μF, ceramic) be connected from VCC to ground. Total lead length between both ends of this external capacitor and the isolator connections should not exceed 20 mm. 10. No external pull up is required for a high logic state on the enable input. 11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on the trailing edge of the output pulse. 12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on the leading edge of the output pulse. 13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. 15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types. 16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types. 17. Not required for HCPL-5650, HCPL-5651 and 8102805 types. 18. Required for HCPL-5650, HCPL-5651 and 8102805 types only. Figure 1. High Level Output Current vs. Temperature. 9 Figure 2. Input-Output Characteristics. Figure 3. Input Diode Forward Characteristics. D.U.T. PULSE GENERATOR ZO = 50Ω tH = 5 ns INPUT MONITORING NODE 5V VCC RL IF VO 0.01 μF BYPASS VO CL* GND Rm * CLINCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 5. Propagation Delay, tPHL and tPLH vs. Pulse Input Current, IFH. Figure 4. Test Circuit for tPHL and tPLH.* D.U.T. B II VCC A +5 V 510 Ω OUTPUT VO MONITORING 0.01 μF NODE BYPASS GND VFF VCM + PULSE GEN. Figure 6. Propagation Delay vs. Temperature. 10 Figure 7. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. PULSE GENERATOR ZO = 50 Ω tr = 5 ns OUTPUT VE MONITORING NODE +5 V D.U.T. VCC VE IF = 13 mA RL VOUT 0.01 μF BYPASS OUTPUT VO MONITORING CL* NODE GND * CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 9. Enable Propagation Delay vs. Temperature. Figure 8. Test Circuit for tEHL and tELH. VCC +5.5 V VOC +5.5 V D.U.T.* VCC (EACH INPUT) + VIN 0.01 μF 200 Ω 5.3 V (EACH OUTPUT) GND 200 Ω (EACH OUTPUT) CONDITIONS: IF = 20 mA IO = 25 mA TA = +125 oC * ALL CHANNELS TESTED SIMULTANEOUSLY. Figure 10. Operating Circuit for Burn-In and Steady State Life Tests. 11 MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program Avago’s Hi-Rel Optocouplers are in compliance with MILPRF-38534 Classes H and K. Class H and Class K devices are also in compliance with DLA drawings 81028, 596290855 and 5962-98001. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies Limited. All rights reserved. Obsoletes 5968-9407E AV02-1336EN - October 2, 2012