HD74HC673 16-bit Shift Register Description The HD74HC673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A threestate input/output (data I/O) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon command. A high logic level at the chip-select (CS) input disables both the shift-register clock and the storage register clock and places the data I/O in the high-impedance state. The store-clear function is not disabled by the chip select. Caution must be exercised to prevent false clocking of either the shift register or the storage register via the chip-select input. The shift clock should be low during the low-to-high transition of chip select and the store clock should be low during the high-to-low transition of chip select. Features • • • • • High Speed Operation: tpd (MODE/STRCLK to Y) = 23 ns typ (C L = 50 pF) High Output Current: Fanout of 15 LSTTL Loads (Q15 output) Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC673 Function Table Inputs Shift Register Functions Mode/ SER/ Read from Storage Register Write into Parallel Functions CS R/W SHCLK STRCLR STRCLK Q15 Shift Serial Output Serial Input Load H X X X X Z No X X X L X L L X X Z L H X X Q15 L H X L L H L L H H L L X X H No No No Load No Yes Yes No Yes No Yes No Q14n Yes Yes No H L No Yes Yes Yes No H Y15n No Yes Yes No No No No No Yes Z No No Pin Arrangement CS 1 24 VCC SH CLK 2 23 Y15 R/W 3 22 Y14 STRCLR 4 21 Y13 Mode/STRCLK 5 20 Y12 SER/Q15 6 19 Y11 Y0 7 18 Y10 Y1 8 17 Y9 Y2 9 16 Y8 Y3 10 15 Y7 Y4 11 14 Y6 GND 12 13 Y5 (Top view) 2 Clear No HD74HC673 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage range VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC + 0.5 V Output voltage VOUT –0.5 to VCC + 0.5 V Output current I OUT ±35 mA DC current drain per VCC, GND I CC, I GND ±75 mA DC input diode current I IK ±20 mA DC output diode current I OK ±20 mA Power dissipation per package PT 500 mW Storage temperature Tstg –65 to +150 °C Logic Diagram SER Q15 IN PE SCK P Q D CK CLR Y Y0 Y1 Y2 Y13 X12 Y14 Y15 CS SHCLK RW VCC MS STRCLR 3 HD74HC673 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –6 mA 6.0 5.68 — — 5.63 — I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 6 mA 6.0 — — 0.26 — 0.33 I OL = 7.8 mA 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Output voltage VOH VOL Test Conditions V V Q15 I OH = –20 µA Vin = VIH or VIL V Q15 I OL = 20 µA Vin = VIH or VIL V Y0 to Y 15 I OH = –20 µA Vin = VIH or VIL V Y0 to Y 15 I OL = 20 µA Vin = VIH or VIL Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 4 — HD74HC673 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 5 — 4 MHz 4.5 — — 27 — 21 6.0 — — 32 — 25 Propagation delay t PLH 2.0 — — 200 — 250 time 4.5 — 23 40 — 50 6.0 — — 34 — 43 t PLH 2.0 — — 200 — 250 t PHL 4.5 — 23 40 — 50 6.0 — — 34 — 43 t PLH 2.0 — — 200 — 250 t PHL 4.5 — 19 40 — 50 6.0 — — 34 — 43 frequency t PHL Output enable t ZH 2.0 — — 150 — 190 time t ZL 4.5 — — 30 — 38 6.0 — — 26 — 33 Output disable t HZ 2.0 — — 150 — 190 time t LZ 4.5 — — 30 — 38 6.0 — — 26 — 33 2.0 80 — — 100 — 4.5 16 6 — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — 4.5 20 1 — 25 — 6.0 17 — — 21 — 2.0 100 — — 125 — 4.5 20 7 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 0 — 5 — 6.0 5 — — 5 — Pulse width Setup time tw t su t su Hold time th Test Conditions ns STRCLR to Y ns Mode/STRCLK to Y ns SHCLK to SER/Q 15 ns ns ns ns SER/Q15 to SH CLK ns CS to R/W ns SH CLK to SER/Q15 5 HD74HC673 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions Output rise/fall t TLH 2.0 — — 60 — 75 ns 6 Pin time t THL 4.5 — 4 12 — 15 6.0 — — 10 — 13 t TLH 2.0 — — 75 — 95 ns Other Pins t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance 6 Cin pF Unit: mm 13 13.4 15.0 Max 24 31.6 32.5 Max 12 1.2 15.24 0.48 ± 0.10 0.51 Min 2.54 ± 0.25 5.70 Max 2.13 Max 2.54 Min 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-24 Conforms Conforms 3.1 g Cautions 1. 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