HD74LV574A Octal D-type Flip-Flops with 3-state Outputs REJ03D0520–0100 Rev.1.00 Feb. 01, 2005 Description The HD74LV574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LV574AFPEL SOP–20 pin (JEITA) PRSP0020DD–B (FP–20DAV) FP EL (2,000 pcs/reel) HD74LV574ATELL TSSOP–20 pin PTSP0020JB–A (TTP–20DAV) T ELL (2,000 pcs/reel) Function Table Inputs OE CLK D Output Q H X X Z L ↑ L L L ↑ H H L ↓ X Q0 Note: H: High level L: Low level X: Immaterial Z: High impedance Q0: Output level before the indicated steady state input conditions were established. Rev.1.00 Feb. 01, 2005 page 1 of 7 HD74LV574A Pin Arrangement 20 VCC OE 1 1D 2 D Q 2D 3 D Q 18 2Q 3D 4 D Q 17 3Q 4D 5 D Q 16 4Q 5D 6 D Q 15 5Q 6D 7 D Q 14 6Q 7D 8 D Q 13 7Q 8D 9 D Q 12 8Q GND 10 19 1Q 11 CLK (Top view) Absolute Maximum Ratings Item Supply voltage range Symbol Ratings Unit VCC –0.5 to 7.0 V 1 Input voltage range* VI –0.5 to 7.0 V Output voltage range*1, 2 VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Conditions Output: H or L VCC: OFF or Output: Z Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC VO = 0 to VCC Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 Storage temperature IO ±35 mA ICC or IGND ±70 mA PT 835 mW 757 Tstg –65 to 150 SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.1.00 Feb. 01, 2005 page 2 of 7 HD74LV574A Recommended Operating Conditions Item Supply voltage range Symbol Min Max Unit VCC 2.0 5.5 V Conditions Input voltage range VI 0 5.5 V Output voltage range VO 0 VCC V 0 5.5 — –50 µA VCC = 2.0 V — –2 mA VCC = 2.3 to 2.7 V Output current IOH IOL ∆t /∆v Input transition rise or fall rate Operating free-air temperature Ta H or L High impedance state — –8 VCC = 3.0 to 3.6 V — –16 VCC = 4.5 to 5.5 V — 50 µA VCC = 2.0 V — 2 mA VCC = 2.3 to 2.7 V — 8 VCC = 3.0 to 3.6 V — 16 VCC = 4.5 to 5.5 V 0 200 0 100 0 20 –40 85 ns/V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V °C Note: Unused or floating inputs must be held high or low. DC Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VCC (V)* Min Typ Max Unit 2.0 1.5 — — V 2.3 to 2.7 VCC × 0.7 — — VIH 3.0 to 3.6 VCC × 0.7 — — 4.5 to 5.5 VCC × 0.7 — — 2.0 — — 0.5 2.3 to 2.7 — — VCC × 0.3 3.0 to 3.6 — — VCC × 0.3 4.5 to 5.5 — — VCC × 0.3 Min to Max VCC – 0.1 — — 2.3 2.0 — — IOH = –2 mA VIL Output voltage VOH VOL Test Conditions V IOH = –50 µA 3.0 2.48 — — IOH = –8 mA 4.5 3.8 — — IOH = –16 mA Min to Max — — 0.1 IOL = 50 µA 2.3 — — 0.4 IOL = 2 mA 3.0 — — 0.44 IOL = 8 mA 4.5 — — 0.55 IOL = 16 mA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Off-state output current IOZ 5.5 — — ±5 µA VO = VCC or GND Quiescent supply current ICC 5.5 — — 20 µA VIN = VCC or GND, IO = 0 Output leakage current IOFF 0 — — 5 µA VI or VO = 0 to 5.5 V Input capacitance CIN 3.3 — 2.9 — pF VI = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.1.00 Feb. 01, 2005 page 3 of 7 HD74LV574A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Item Ta = –40 to 85°C Test Conditions FROM (Input) TO (Output) Symbol Min Typ Max Min Max Unit Maximum clock frequency tmax 60 105 — 50 — MHz 50 85 — 40 — Propagation delay time tPLH tPHL — 9.7 16.6 1.0 20.0 — 11.8 19.6 1.0 23.0 Enable time tZH tZL — 8.9 16.1 1.0 19.0 — 10.9 19.0 1.0 22.0 Disable time tHZ tLZ — 6.3 12.8 1.0 15.0 — 8.2 17.5 1.0 20.0 Setup time tSU 5.5 — — 5.5 — ns Data before CLK ↑ Hold time th 2.0 — — 2.0 — ns Data after CLK ↑ Pulse width tw 7.0 — — 7.0 — ns CLK: "H" or "L" CL = 15 pF CL = 50 pF ns CL = 15 pF CLK Q OE Q OE Q CL = 50 pF ns CL = 15 pF ns CL = 15 pF CL = 50 pF CL = 50 pF VCC = 3.3 ± 0.3 V Ta = 25°C Item Symbol Maximum clock frequency tmax Propagation delay time Min Typ Ta = –40 to 85°C Max Min Max Unit Test Conditions 80 150 — 70 — MHz CL = 15 pF 55 110 — 50 — CL = 50 pF tPLH tPHL — 6.8 13.2 1.0 15.5 — 8.3 16.7 1.0 19.0 Enable time tZH tZL — 6.3 12.8 1.0 15.0 — 7.7 16.3 1.0 18.5 Disable time tHZ tLZ — 4.7 13.0 1.0 15.0 — 5.9 15.0 1.0 17.0 ns CL = 15 pF ns CL = 15 pF ns CL = 15 pF FROM (Input) TO (Output) CLK Q OE Q OE Q CL = 50 pF CL = 50 pF CL = 50 pF Setup time tSU 3.5 — — 3.5 — ns Data before CLK ↑ Hold time th 1.5 — — 1.5 — ns Data after CLK ↑ Pulse width tw 5.0 — — 5.0 — ns CLK: "H" or "L" VCC = 5.0 ± 0.5 V Ta = 25°C Item Ta = –40 to 85°C Test Conditions Symbol Min Typ Max Min Max Unit Maximum clock frequency tmax 130 205 — 110 — MHz CL = 15 pF 85 170 — 75 — Propagation delay time tPLH tPHL — 4.9 8.6 1.0 10.0 ns CL = 15 pF — 5.9 10.6 1.0 12.0 Enable time tZH tZL — 4.6 9.0 1.0 10.5 ns CL = 15 pF — 5.5 11.0 1.0 12.5 tHZ tLZ — 3.4 9.0 1.0 10.5 — 4.0 10.1 1.0 11.5 tSU 3.5 — — 3.5 — Disable time Setup time FROM (Input) TO (Output) CL = 50 pF CLK Q OE Q OE Q CL = 50 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns Data before CLK ↑ Hold time th 1.5 — — 1.5 — ns Data after CLK ↑ Pulse width tw 5.0 — — 5.0 — ns CLK: "H" or "L" Rev.1.00 Feb. 01, 2005 page 4 of 7 HD74LV574A Output-skew Characteristics CL = 50 pF Ta = 25°C Item Ta = –40 to 85°C Symbol VCC = (V) Min Max Min Max Unit tsk (O) 2.3 to 2.7 — 2.0 — 2.0 ns 3.0 to 3.6 — 1.5 — 1.5 4.5 to 5.5 — 1.0 — 1.0 Output skew Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC = (V) Min Typ Max Unit Power dissipation capacitance CPD 3.3 — 21.1 — pF 5.0 — 22.8 — Test Conditions f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Symbol VCC = (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.6 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.5 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 2.9 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic input voltage VIL (D) 3.3 — — 0.99 V Item Test Circuit Output 1 kΩ S2 OPEN GND CL VCC TEST t PLH /t PHL S2 OPEN t ZH/t HZ t ZL /t LZ GND VCC Note: C L includes the probe and jig capacitance. Rev.1.00 Feb. 01, 2005 page 5 of 7 Test Conditions HD74LV574A • Waveform − 1 Input CLK tf tr VCC 90 % 90 % 50 %VCC 10 % tr 50 %VCC 10 % tf 90 % Input D GND VCC 90 % 10 % 10 % GND t PHL t PLH VOH Output Q 50 %VCC 50 %VCC VOL • Waveform − 2 tf tr Input CLK 10 % tsu 90 % 90 % 50 % 50 % VCC VCC tw th VCC 50 %VCC 10 % tw GND VCC 50 %VCC Input D 50 %VCC GND • Waveform − 3 Input OE tf tr 90 % 50 %VCC 10 % VCC 90 % 50 %VCC 10 % t LZ t ZL GND VCC Waveform − A 50 %VCC VOL + 0.3 V t ZH Waveform − B t HZ 50 %VCC VOH − 0.3 V VOL VOH GND Notes: 1. tr ≤ 3 ns, tf ≤ 3 ns 2. Input waveform: PRR ≤ 1 MHZ, duty cycle 50% 3. Waveform−A is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Waveform−B is for an output with internal conditions such that the output is high except when disabled by the output control. Rev.1.00 Feb. 01, 2005 page 6 of 7 HD74LV574A Package Dimensions JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 *3 Nom Max D 12.60 13.0 E 5.50 A2 10 e Z A1 bp x Dimension in Millimeters Min M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c 1 q 0° HE A1 q y L Detail F x 0.12 y 0.15 Z L RENESAS Code PTSP0020JB-A *1 Previous Code TTP-20DAV 0.80 0.50 0.70 0.90 1.15 1 MASS[Typ.] 0.07g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 20 8° 1.27 e L JEITA Package Code P-TSSOP20-4.4x6.5-0.65 7.50 11 c HE *2 E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Index mark Dimension in Millimeters Min Nom Max D 6.50 6.80 E 4.40 A2 A1 10 1 Z e *3 bp 0.03 0.07 0.10 0.15 0.20 0.25 0.10 0.15 0.20 6.40 6.60 A L1 x 1.10 bp M b1 c c1 A q 0° HE A1 q L y Detail F 8° 0.65 e x 0.13 y 0.10 Z 0.65 L L Rev.1.00 Feb. 01, 2005 page 7 of 7 6.20 0.4 1 0.5 1.0 0.6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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