HI-3182, HI-3183, HI-3184 HI-3185, HI-3186, HI-3188 March 2008 ARINC 429 Differential Line Driver GENERAL DESCRIPTION The HI-3182, HI-3183, HI-3184, HI-3185, HI-3186 and HI-3188 bus interface products are silicon gate CMOS devices designed as a line driver in accordance with the ARINC 429 bus specifications. In addition to being functional upgrades of Holt's HI-8382 & HI-8383 products, they are also alternate sources for the HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon) and a variety of similar line driver products from other manufacturers. Inputs are provided for clocking and synchronization. These signals are AND'd with the DATA inputs to enhance system performance and allow the HI-318X series of products to be used in a variety of applications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL and CMOS compatibility. The differential outputs of the HI-318X series of products are programmable to either the high speed or low speed ARINC 429 output rise and fall time specifications through the use of two external capacitors. The output voltage swing is also adjustable by the application of an external voltage to the VREF input. Products with 0, 13 or 37.5 ohm resistors in series with each ARINC output are available. In addition, the HI-3182 and HI-3184 products also have a fuse in series with each output. PIN CONFIGURATION (Top View) 14 V1 VREF 1 13 CLOCK GND (See Note * ) 2 12 DATA (B) SYNC 3 11 CB DATA (A) 4 10 BOUT CA 5 9 +V AOUT 6 8 GND -V 7 HI-3184PS, HI-3185PS & HI-3186PS 14 - PIN PLASTIC SMALL OUTLINE (ESOIC)** NB Notes: * Pin 2 may be left floating ** Thermally Enhanced SOIC Package (See Page 6 for additional package pin configurations) FUNCTION The HI-318X series of line drivers are intended for use where logic signals must be converted to ARINC 429 levels such as when using an ASIC, the HI-3282/HI-8282A ARINC 429 Serial Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or the HI-8783 ARINC Interface Device. Holt products are readily available for both industrial and military applications. Please contact the Holt Sales Department for additional information. + _ FEATURES ARINC 429 DIFFERENTIAL LINE DRIVER ! Low power CMOS TRUTH TABLE ! TTL and CMOS compatible inputs ! Programmable output voltage swing ! Adjustable ARINC rise and fall times ! Plastic 14 & 16-pin thermally enhanced SOIC packages available SYNC CLOCK DATA(A) DATA(B) AOUT BOUT COMMENTS X L X X 0V 0V NULL L X X X 0V 0V NULL ! Pin-for-Pin alternative for Intersil/Fairchild applications H H L L 0V 0V NULL ! Operates at data rates up to 100 Kbits H H L H -VREF +VREF LOW ! Overvoltage protection H H H L +VREF -VREF HIGH ! Industrial and extended temperature ranges H H H H 0V 0V NULL (Ds3182 Rev. K ) HOLT INTEGRATED CIRCUITS www.holtic.com 03/09 HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 FUNCTIONAL DESCRIPTION The SYNC and CLOCK inputs establish data synchronization utilizing two AND gates, one for each data input (figure 2). Each logic input, including the power enable (STROBE) input, are TTL/CMOS compatible. Figure 1 illustrates a typical ARINC 429 bus application. Three power supplies are necessary to operate the HI-3182; typically +15V, -15V and +5V. The chip also works with ±12V supplies. The +5V supply can also provide a reference voltage that determines the output voltage swing. The differential output voltage swing will equal 2VREF. If a value of VREF other than +5V is needed, a separate +5V power supply is required for pin V1. With the DATA (A) input at a logic high and DATA (B) input at a logic low, AOUT will switch to the +VREF rail and BOUT will switch to the -VREF rail (ARINC HIGH state). With both data input signals at a logic low state, the outputs will both switch to 0V (ARINC NULL state). The driver output impedance, ROUT, is nominally 75, 26 or 0 ohms depending on the option chosen. The rise and fall times of the outputs can be calibrated through the selection of two external capacitor values that are connected to the CA and CB input pins. Typical values for high-speed operation (100KBPS) are CA = CB = 75pF and for low-speed operation (12.5 to 14KBPS) CA = CB = 500pF. function is not available in the 14 & 16-pin SOIC package configurations where the pin is internally connected to ground. The ARINC outputs of the HI-3182 and HI-3184 are protected by internal fuses capable of sinking between 800 - 900 mA for short periods of time (125ms). The Vref pin has an internal pull-up resistor to V+, allowing the use of a simple external zener diode to set the reference voltage. POWER SUPPLY SEQUENCING The power supplies should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is +V followed by V1, always ensuring that +V is the most positive supply. The -V supply is not critical and can be asserted at any time. +5V +15V VREF V1 SYNC CLOCK DATA (A) AOUT +V INPUTS TO ARINC BUS DATA (B) CA CB STROBE GND -V BOUT The CA and CB pins swing between +5V and ground allowing the switching of capacitor values with an external singlesupply analog switch. The ARINC outputs can be put in a tri-state mode by applying a logic high to the STROBE input pin. If this feature is not being used, the pin should be tied to ground. The STROBE VREF +V CA -15V Figure 1. ARINC 429 BUS APPLICATION Shorted on HI-3186, HI-3188 A OUT DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) CLOCK 24.5W 13W FA OUTPUT DRIVER (A) CL SYNC LEVEL SHIFTER AND SLOPE CONTROL (B) DATA (B) V1 24.5W STROBE GND -V FB OUTPUT DRIVER (B) Shorted on HI-3183, HI-3186 HI-3188 CURRENT REGULATOR 13W Shorted on HI-3183, HI-3185 HI-3186, HI-3188 B OUT CB Figure 2. FUNCTIONAL BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 2 RL HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 PIN DESCRIPTIONS SYMBOL FUNCTION DESCRIPTION VREF ANALOG Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference. STROBE INPUT A logic high tri-states the ARINC outputs. Not available in the 14-pin SOIC package (tied to GND internally). SYNC INPUT Synchronizes data inputs DATA (A) INPUT Data input terminal A CA INPUT Connection for DATA (A) slew-rate capacitor AOUT OUTPUT ARINC output terminal A -V POWER -12V to -15V GND POWER 0.0V +V POWER +12V to +15V BOUT OUTPUT ARINC output terminal B CB INPUT Connection for DATA (B) slew-rate capacitor DATA (B) INPUT Data input terminal B CLOCK INPUT Synchronizes data inputs V1 POWER +5V ±5% ABSOLUTE MAXIMUM RATINGS All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified) PARAMETER Differential Voltage Supply Voltage Voltage Reference Input Voltage Range SYMBOL VDIF CONDITIONS For ARINC 429 For Applications other than ARINC See Note: 1 Output Overvoltage Protection See Note: 2 Storage Temperature Range TA TSTG Lead Temperature Junction Temperature UNIT 40 V +10.8 to +16.5 -10.8 to -16.5 +5 ±5% +7 V V V +5 ±5% 1.5 to 6 6 6 V V > GND -0.3 < V1 +0.3 V V VIN Output Short-Circuit Duration Operating Temperature Range MAXIMUM Voltage between +V and -V terminals +V -V V1 VREF OPERATING RANGE Industrial Extended -40 to +85 -55 to +125 °C °C Ceramic & Plastic -65 to +150 °C Soldering, 10 seconds TJ +275 °C +175 °C Note 1. Heatsinking may be required for continuous Output Short Circuit at +125°C and for 100KBPS at +125°C. Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater than ±12.0V with respect to GND. (HI-3182 & 3184 only) NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HOLT INTEGRATED CIRCUITS 3 HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 DC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL Output Voltage High (Output to Ground) ICCOP (+V) ICCOP (-V) ICCOP (V1) ICCOP (VREF) ISC (+V) ISC (-V) IOHSC IOLSC IIH IIL VIH VIL VOH Output Voltage Low (Output to Ground) Supply Current +V (Operating) Supply Current -V (Operating) Supply Current V1 (Operating) Reference Pin Current VREF (Operating) Supply Current +V (During Short Circuit Test) Supply Current -V (During Short Circuit Test) Output Short Circuit Current (Output High) Output Short Circuit Current (Output Low) Input Current (Input High) Input Current (Input Low) Input Voltage High Input Voltage Low Output Voltage Null Input Capacitance CONDITION No Load MIN TYP (0 - 100KBPS) No Load (0 - 100KBPS) No Load (0 - 100KBPS) No Load, VREF = 5V (0 - 100KBPS) Short to Ground (See Note: 1) Short to Ground (See Note: 1) Short to Ground VMIN=0 (See Note: 2) VMIN=0 (See Note: 2) Short to Ground MAX UNITS +16 -16 -1.0 mA mA -0.4 500 µA -0.15 mA 150 mA -150 mA -80 +80 mA mA 1.0 -1.0 µA µA 2.0 V 0.5 V No Load (0 -100KBPS) +VREF -.25 +VREF +.25 V VOL No Load (0 -100KBPS) -VREF -.25 -VREF +.25 V VNULL CIN No Load (0-100KBPS) -250 +250 mV 15 See Note 1 pF Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter. Note 2. Interchangeability of force and sense is acceptable. AC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Rise Time ( A OUT , B OUT ) tR C A = C B = 75pF See Figure 3. 1.0 2.0 µs Fall Time ( A OUT , B OUT ) tF C A = C B = 75pF See Figure 3. 1.0 2.0 µs Propagtion Delay Input to Output t PLH C A = C B = 75pF See Figure 3. 3.0 µs Propagtion Delay Input to Output t PHL C A = C B = 75pF See Figure 3. 3.0 µs DATA (B) 0V VREF AOUT 0V 2.0V 0.5V 50% DATA (A) 0V 50% 2.0V 0.5V ADJUST BY CA +4.75V to +5.25V ADJUST BY CA -VREF t PHL +VREF BOUT 0V -VREF 50% 50% t PLH -4.75V to -5.25V ADJUST BY CB -4.75V to -5.25V 2VREF tR +4.75V to +5.25V ADJUST BY CB HIGH DIFFERENTIAL OUTPUT 0V +9.5V to +10.5V NULL (AOUT - BOUT) NOTE: OUTPUTS UNLOADED tF -2VREF LOW Figure 3. SWITCHING WAVEFORMS HOLT INTEGRATED CIRCUITS 4 -9.5V to -10.5V HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 HI-318X PACKAGE THERMAL CHARACTERISTICS MAXIMUM ARINC LOAD 3, 6, 7 JUNCTION TEMPERATURE, Tj HEAT SINK ØJA (°C/W) SUPPLY CURRENT 14-pin Thermally Enhanced Plastic SOIC (ESOIC) Unsoldered 82 20 mA 57°C 117°C 157°C Soldered 65 20 mA 51°C 111°C 151°C 14-pin Thermally Enhanced Plastic SOIC (ESOIC) Unsoldered 51 20 mA 45°C 105°C 145°C Soldered 28 20 mA 36°C 96°C 136°C N/A 70 25 mA 56°C 110°C 150°C PACKAGE STYLE 1 28-pin Plastic AOUT and BOUT Shorted to Ground 2 TA = 25°C TA = 85°C TA = 125°C 3, 4, 5, 6, 7 JUNCTION TEMPERATURE, Tj HEAT SINK ØJA (°C/W) SUPPLY CURRENT 14-pin Thermally Enhanced Plastic SOIC (ESOIC) Unsoldered 82 36 mA 57°C 147°C 187°C Soldered 65 36 mA 78°C 138°C 178°C 14-pin Thermally Enhanced Plastic SOIC (ESOIC) Unsoldered 51 40 mA 64°C 124°C 164°C Soldered 28 40 mA 53°C 113°C 153°C N/A 70 63 mA 100°C 150°C 182°C PACKAGE STYLE 28-pin Plastic 1 2 TA = 25°C TA = 85°C TA = 125°C Notes: 1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062"). 2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8. 3. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this is considered unrealistic for high speed operation. 4. Similar results would be obtained with AOUT shorted to BOUT. 5. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended. 6. Data will vary depending on air flow and the method of heat sinking employed. 7. Current values listed are for each of the +V and -V supplies. HEAT SINK - ESOIC PACKAGES Both the 14-pin and 16-pin thermally enhanced SOIC packages are used for HI-318X products. These ESOIC packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and can be soldered to any ground or power plane. However, since the chip’s substrate is at +V, connecting the heat sink to this power plane is recommended to avoid coupling noise into the circuit. HOLT INTEGRATED CIRCUITS 5 HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 SYNC STROBE N/C VREF V1 N/C N/C ADDITIONAL PIN CONFIGURATIONS (See page 1 for 14-Pin Small Outline SOIC) HI-3182PS, HI-3183PS, HI-3188PS VREF - 1 16 - V1 GND (See Note * ) - 2 4 15 - N/C SYNC - 3 14 - CLOCK DATA(A) - 4 13 - DATA(B) CA - 5 12 - CB AOUT - 6 11 - BOUT -V - 7 10 - N/C GND - 8 N/C DATA (A) N/C N/C CA N/C N/C 3 2 1 28 27 26 5 25 6 24 7 9 HI-3182PJ 23 22 HI-3183PJ 21 10 20 8 19 11 9 - +V CLOCK N/C DATA (B) CB N/C N/C N/C 16 - PIN PLASTIC SMALL OUTLINE (ESOIC)** 28 - PIN PLASTIC PLCC N/C N/C N/C N/C DATA(B) CB N/C N/C BOUT SYNC STROBE N/C VREF V1 N/C N/C Notes: * Pin 2 may be left floating ** Thermally Enhanced SOIC package N/C AOUT -V GND +V BOUT N/C 12 13 14 15 16 17 18 4 29 28 27 26 25 24 23 22 21 CLOCK V1 N/C VREF STROBE SYNC N/C 30 20 31 19 32 HI-3182CJ HI-3183CJ 1 2 18 17 16 3 15 4 14 8 9 10 11 12 13 3 2 1 28 27 26 5 25 6 24 7 8 9 HI-3182CL HI-3183CL 23 22 21 10 20 11 19 12 13 14 15 16 17 18 CLOCK N/C DATA (B) CB N/C N/C N/C N/C AOUT -V GND +V BOUT N/C 7 N/C DATA (A) N/C N/C CA N/C N/C N/C N/C N/C DATA(A) CA N/C N/C N/C AOUT 5 6 N/C N/C +V GND N/C -V N/C 32 - PIN CERQUAD 28 - PIN CERAMIC LCC VREF 1 STROBE 2 HI-3182CD HI-3183CD 16 - PIN CERAMIC SIDE BRAZED DIP SYNC 3 DATA(A) 4 CA 5 AOUT 6 -V 7 GND 8 16 V1 VREF 1 15 N/C 14 CLOCK 13 DATA(B) 12 CB 11 BOUT STROBE 2 HI-3182CR HI-3183CR 16 - PIN CERDIP 10 N/C 9 +V HOLT INTEGRATED CIRCUITS 6 SYNC 3 DATA(A) 4 CA 5 AOUT 6 -V 7 GND 8 16 V1 15 N/C 14 CLOCK 13 DATA(B) 12 CB 11 BOUT 10 N/C 9 +V HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 ORDERING INFORMATION HI - 318x x x - xx (Ceramic) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No M -55°C TO +125°C M Yes PART NUMBER PACKAGE DESCRIPTION LEAD FINISH (Note 1) CD 16 PIN CERAMIC SIDE BRAZED DIP (16C) Gold (’M’ Flow: Solder) CJ 32 PIN J-LEAD CERQUAD (32U) not available with ‘M’ flow Solder CL 28 PIN CERAMIC LEADLESS CHIP CARRIER (LCC) (28S) Gold (’M’ Flow: Solder) CR 16 PIN CERDIP (16D) not available with ‘M’ flow Solder PART NUMBER OUTPUT SERIES RESISTANCE FUSE 3182 37.5 Ohms Yes 3183 13 Ohms No HI - 318xxx x x (Plastic) PART NUMBER Blank F LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No M (Note 2) -55°C TO +125°C M Yes PART NUMBER PACKAGE DESCRIPTION OUTPUT SERIES RESISTANCE FUSE 3182PJ 28 PIN PLASTIC J-LEAD PLCC (28J) 37.5 Ohms Yes 3182PS 16 PIN PLASTIC SMALL OUTLINE - WB ESOIC (16HWE) 37.5 Ohms Yes 3183PJ 28 PIN PLASTIC J-LEAD PLCC (28J) 13 Ohms No 3183PS 16 PIN PLASTIC SMALL OUTLINE - WB ESOIC (16HWE) 13 Ohms No 3184PS 14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE) 37.5 Ohms Yes 3185PS 14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE) 37.5 Ohms No 3186PS 14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE) 0 Ohms No 3188PS 16 PIN PLASTIC SMALL OUTLINE - NB ESOIC (16HNE) 0 Ohms No Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC with built-in heat sink) NB - Narrow Body WB - Wide Body (1) Gold terminal finish is Pb-Free, RoHS compliant. (2) Only available with ‘3182PJ’. HOLT INTEGRATED CIRCUITS 7 HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188 REVISION HISTORY Revision Date Description of Change DS3182, Rev. K 03/19/09 Clarified the temperature ranges, and Note (2) in the Ordering Information. HOLT INTEGRATED CIRCUITS 8 HI-318X PACKAGE DIMENSIONS 14-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced) Top View Package Type: 14HNE .0085 ± .001 (.220 ± .029) .341 ± .004 (8.65 ± .10) .236 ± .008 (6.00 ± .20) inches (millimeters) .270 typ (6.86) Bottom View .100 typ (2.54) .153 ± .003 (3.87 ± .06) See Detail A .0165 ± .003 (.419 ± .089) Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. .055 ± .005 (1.397 ± .13) .050 BSC (1.27) 0°° to 8°° .0025 ± .0015 (.0635 ± .04) .033 ± .017 (.838 ± .43) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Detail A 16-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced) .0086 ± .0015 .390 ± .004 (9.90 ± .10) .236 ±.008 (5.99 ±.20) Top View BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Package Type: 16HNE .270 typ (6.86) .10 typ (2.54) .1525 ± .003 (2.87 ± .06) Bottom View See Detail A .0165 ± .003 (.419 ± .09) .050 BSC (1.27) inches (millimeters) .061 ± .007 (1.55 ± .18) 0°° to 8°° .033 ± .017 (.838 ± .43) Detail A HOLT INTEGRATED CIRCUITS 9 Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. .0025 ± .0015 (.0635 ± .04) HI-318X PACKAGE DIMENSIONS 16-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) Package Type: 16HWE .0105 ± .0015 (.2667 ± .038) .405 ± .008 (10.287 ± .20) .407 ± .013 (10.34 ± .32) inches (millimeters) .240 (6.10) typ .295 ± .004 (7.49 ± .10) Top View .190 typ (4.83) Bottom View See Detail A .090 ± .010 (2.286 ± .254) .050 BSC (1.27) .0165 ± .003 (.419 ± .089) 0° to 8° Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. .0025 ± .002 (.064 ± .038) .033 ± .017 (.838 ± .432) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Detail A 16-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 16C .810 max (20.574) .295 ±.010 (7.493 ±.254) PIN 1 .200 max (5.080) .050 ±.005 (1.270 ±.127) .035 ± .010 (.889 ±.254) BASE PLANE .125 min (3.175) .018 ± .002 (.457 ±.051) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .010 ±.002 (.254 ±.051) SEATING PLANE .100 BSC (2.54) HOLT INTEGRATED CIRCUITS 10 .300 ± .010 (7.620 ±.254) HI-318X PACKAGE DIMENSIONS 16-PIN CERDIP inches (millimeters) Package Type: 16D .050 max (1.27 max) .790 max (20.006 max) .005 min (.127 min) .288 ±.005 (7.315 ±.125) .100 BSC (2.54) .056 typ (1.422 typ) .310 ±.010 (7.874 ±.254) .180 max (4.572 max) .200 max (5.080 max) .015 min (.381 min) .018 ±.003 (.457 ±.760) .125 min (3.175 min) 0° to 15° .010 ±.002 (.254 ±.051) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 28-PIN PLASTIC PLCC inches (millimeters) Package Type: 28J PIN NO. 1 PIN NO. 1 IDENT .045 x 45° .045 x 45° .050 (1.27) BSC .453 ± .003 (11.506 ±.076) SQ. .490 ± .005 (12.446 ±.127) SQ. .031 ±.005 (.787 ±.127) .017 ±.004 (.432 ±.102) See Detail A .010 ± .001 (.254 ± .03) .173 ±.008 (4.394 ±.203) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .020 (.508) min .410 ±.020 (10.414 ±.508) HOLT INTEGRATED CIRCUITS 11 DETAIL A R .035 .889 HI-318X PACKAGE DIMENSIONS 28-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters) Package Type: 28S .020 INDEX (.508) .080 ±.020 (2.032 ±.508) PIN 1 PIN 1 .050 ±.005 (1.270 ±.127) .451 ±.009 (11.455 ±.229) SQ. .050 BSC (1.270) .025 ±.003 (.635 ±.076) .008R ± .006 (.203R ±.152) .040 x 45° 3PLS (1.016 x 45° 3PLS) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 32-PIN J-LEAD CERQUAD inches (millimeters) Package Type: 32U 31 32 1 2 .450 ±.008 (11.430 ±.203) .488 ±.008 (12.395 ±.203) .420 ±.012 (10.668 ±.305) .588 ±.008 (14.935 ±.203) .550 ± .009 (13.970 ± .229) .190 max (4.826) .040 typ (1.016) .050 .019 ± .003 BSC (1.270) (.483 ± .076) .520 ±.012 (13.208 ±.305) .083 ±.009 (2.108 ±.229) HOLT INTEGRATED CIRCUITS 12 BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95)