HI3026A CT ODU ODUCT 46 R P PR , HI32 TE O LE UT E 6 OBS UBSTIT R HI302 S E B E L M NU SI B POS IL PART S R INTE ® March 2003 8-Bit, 140 MSPS, Flash A/D Converter Features Description • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB The HI3026A is an 8-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 140 MSPS encode rate capability and full-power analog bandwidth of 150MHz, this component is ideal for applications requiring the highest possible dynamic performance. • Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Compensation Circuit • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . 21pF • Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz • Low Power Consumption . . . . . . . . . . . . . . . . . 790mW • Internal 1/2 Frequency Divider Circuit (With Reset Function) • CLK/2 Clock Output Pin • Compatible with ECL, PECL and TTL Digital Input Levels • 1:2 Demultiplexed Output To minimize system cost and power dissipation, only a +5V power supply is required. The HI3026A’s clock input interfaces directly to TTL, ECL, or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single-channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 140 MSPS conversion rate. Fabricated with an advanced bipolar process, the HI3026A is provided in a space-saving 48-lead MQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range. • Direct Replacement for Sony CXA3026A Applications • RGB Graphics Processing (LCD, PDP) Part Number Information • Digital Oscilloscopes PART NUMBER • Digital Communications (QPSK, QAM) • Magnetic Recording (PRML) TEMPT. RANGE (oC) HI3026AJCQ -20 to 75 HI3026AEVAL 25 PACKAGE PKG. NO. 48 Ld MQFP Q48.12x12-S Evaluation Board Pinout P1D4 P1D7 P1D6 P1D5 DVCC2 DGND2 CLKOUT RESET/T P1D0 DGND2 DVCC2 30 29 DVCC1 6 7 8 9 28 27 10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 P1D3 P1D1 DGND1 P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 CLK/E DGND3 33 32 31 P2D0 P2D1 VRT 4 5 NC VRM3 AGND P1D2 DVCC2 DGND2 AVCC 2 3 35 34 NC AVCC VIN VRM2 48 47 46 45 44 43 42 41 40 39 38 37 36 CLK/T NC VRB AGND VRM1 1 CLKN/E DVEE3 SELECT INV RESETN/E RESET/E HI3026A (MQFP) TOP VIEW FN4246.1 HI3026A Block Diagram AVCC 5 VRT 8 INV DVCC1 44 30 DVCC2 DGND3 19 31 42 12 11 R1 R/2 R (MSB) 40 P1D7 1 R 39 P1D6 . . . 6 BITS 38 P1D5 63 VRM3 9 8 BITS R 64 37 P1D4 TTLOUT R LATCHA 2 36 P1D3 R 35 P1D2 65 R . . . 6 BITS 34 P1D1 6-BIT LATCH + ENCODER 126 ENCODER R 127 VRM2 7 VIN 6 R 128 R 129 R . . . 33 P1D0 (LSB) 8 BITS (MSB) 28 P2D7 6 BITS 27 P2D6 191 4 R 26 P2D5 LATCHB 192 R 193 R . . . TTLOUT VRM1 25 P2D4 24 P2D3 6 BITS 23 P2D2 254 R 22 P2D1 255 VRB 21 P2D0 (LSB) R/2 2 R2 CLK/T 15 CLK/E 13 DELAY 16 17 NC 18 CLKN/E 14 D Q 43 CLKOUT SELECT RESETN/T 46 RESETN/E 48 RESET/E 47 Q 3 10 45 AGND 29 SELECT DGND1 2 20 32 41 1 DGND2 DVEE3 HI3026A Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage AVCC , DVCC1 , DVCC2 . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V DGND3 - DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . VRT - 2.7V to AVCC Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to AVCC VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AVCC |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DVEE3 to 0.5V PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3 TTL (***/T, INV) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1 VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Recommended Operating Conditions WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (VIN) . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage ECL (***/E) VIH DGND3 . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V ECL (***/E) VIL DGND3. . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (VIN) . . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 +2.6V |VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . 1.5 2.1V Digital Input Voltage PECL (***/E) VIH . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V PECL (***/E) VIL . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . . 2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . . 0.8V Other (SELECT) VIH . . . . . . . . . . . . . . . . . DVCC1 Other (SELECT) VIL . . . . . . . . . . . . . . . . . DGND1 VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . . 0.4 0.8 Max Conversion Rate (fC , Straight Mode) . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Max Conversion Rate (fC , DMUX Mode) . . . . 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. ***/E and ***T indicate CLK/E and CLK/T, etc. for the pin name. 3. VID : Input Voltage Differential. Electrical Specifications PARAMETER DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC SYMBOL TEST CONDITIONS Resolution MIN TYP MAX UNITS - 8 - Bits - - ±0.5 LSB - - ±0.5± LSB DC CHARACTERISTICS Integral Linearity Error EIL Differential Linearity Error EDL VIN = 2VP-P, fC = 5 MSPS 3 HI3026A Electrical Specifications DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 21 - pF ANALOG INPUT VIN = +3.0V + 0.07VRMS Analog Input Capacitance CIN Analog Input Resistance RIN 4 - 50 kΩ Analog Input Current IIN 0 - 500 µA REFERENCE INPUT Reference Resistance (Note 4) RREF 75 115 155 Ω Reference Current (Note 5) IREF 9.7 17.4 28 mA Offset Voltage, VRT Side EOT 2 - 15 mV Offset Voltage, VRB Side EOB 2 - 10 mV VIH DGND3 - 1.05 - DGND3 - 0.5 V Digital Input Voltage: Low VIL DGND3 - 3.2 - DGND3 - 1.4 V Threshold Voltage VTH - DGND3 - 1.2 - V DIGITAL INPUT (ECL, PECL) Digital Input Voltage: High Digital Input Current: High IIH VIH = DGND3 - 0.8V -50 - +50 µA Digital Input Current: Low IIL VIL = DGND3 - 1.6V -75 - 0 µA - - 5 pF VIH 2.0 - - V Digital Input Voltage: Low VIL - - 0.8 V Threshold Voltage VTH - 1.5 - V Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Voltage: High Digital Input Current: High IIH VIH = 3.5V -50 - 0 µA Digital Input Current: Low IIL VIL = 0.2V -500 - 0 µA - - 5 pF Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High VOH IOH = -2mA 2.4 - - V Digital Output Voltage: Low VOL IOL = 1mA - - 0.5 V SWITCHING CHARACTERISTICS Maximum Conversion Rate fC 140 - - MSPS Aperture Jitter tAJ - 10 - ps Sampling Delay tDS 3 4.5 6 ns DMUX Mode Clock High Pulse Width tPW1 CLK 2.8 - - ns Clock Low Pulse Width tPW0 CLK 2.8 - - ns Reset Pulse Width (Note 6) tPWR RESETN tx2 - - ns RESETN_CLK Setup t_RST RESETN-CLK 3.5 - - ns CLKOUT Output Delay tDCLK (CL = 5pF) 3.5 7 9 ns Data Output Delay (Note 6) tDO1 DMUX Mode (CL = 5pF) t t+1 t+2 ns tDO2 (CL = 5pF) 4.5 8 10 ns Output Rise Time tr 0.8V to 2.0V (CL = 5pF) - 2 - ns Output Fall Time tf 0.8V to 2.0V (CL = 5pF) - 2 - ns 150 - - MHz DYNAMIC CHARACTERISTICS Input Bandwidth VIN = 2VP-P , -3dB S/N Ratio fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode - 46 - dB fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode - 40 - dB 4 HI3026A Electrical Specifications DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) PARAMETER SYMBOL Error Rate TEST CONDITIONS MIN TYP MAX UNITS fC = 140 MSPS, fIN = 1kHz Full Scale, DMUX Mode, Error > 16 LSB - - 10-12 TPS fC = 140 MSPS, fIN = 34.999MHz Full Scale, DMUX Mode, Error > 16 LSB - - 10-9 TPS fC = 100 MSPS, fIN = 24.999MHz Full Scale, Straight Mode, Error > 16 LSB - - 10-9 TPS (Note 7) mA POWER SUPPLY Supply Current ICC 130 150 190 Supply Current IEE 0.4 0.6 0.8 mA Power Consumption (Note 8) PD 690 790 990 mW NOTES: 4. RREF: Resistance value between VRT and VRB . V RT – V RB -. 5. I REF = ---------------------------R REF 16. t = ---. fC 7. TPS = Times Per Sample. ( V RT – V RB ) 2 -. 8. P D = ( I CC + I EE ) • V CC + -----------------------------------V REF Timing Waveforms N-1 VIN N+2 N+3 tDS 4.5ns N N+1 t CLK tPW1 tDO2 tPW0 8ns 2.0V N-2 P1D0 TO D7 N N+2 N-1 N+1 0.8V P2D0 TO D7 2.0V N-3 tDO1 tDCLK T + 1ns 7ns CLK OUT 0.8V 2.0V 2.0V 0.8V 0.8V RESET PULSE tPWR FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC) 5 HI3026A Timing Waveforms (Continued) N+2 N-1 N+3 N+1 VIN tDS N t CLK tPW1 tPW0 P1D0 TO D7 N-4 2.0V 0.8V N-3 N-2 N-1 N P2D0 TO D7 N-5 2.0V 0.8V N-4 N-3 N-2 N-1 tDO2 2.0V CLK OUT (CLK IS INVERTED AND OUTPUT) 0.8V tDCLK RESET PULSE FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND) DGND3 VIH (MAX) VIL VTH (DGND3 -1.2V) VID VIH VIL (MIN) FIGURE 3. ECL AND PECL SWITCHING LEVEL Pin Descriptions I/O TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION PIN NO SYMBOL 3, 10 AGND GND Analog Ground. Separated from the digital ground. 5, 8 AVCC +5V (Typ) Analog Power Supply. Separated from the digital power supply. 20, 29 32, 41 DGND1 DGND2 GND Digital Ground. 19, 30 31, 42 DVCC1 DVCC2 +5V (Typ) Digital Power Supply. 6 HI3026A Pin Descriptions PIN NO SYMBOL 12 DGND3 I/O (Continued) TYPICAL VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION Digital Power Supply. Ground for ECL input. +5V for PECL and TTL input. +5V (Typ) (With a Single Power Supply) GND (With Dual Power Supplies) 1 DVEE3 GND (With a Single Power Supply) Digital Power Supply. -5V for ECL input. Ground for PECL and TTL Input -5V (Typ) (With Dual Power Supplies) 16, 17, 18 NC No Connect pin. Not connected with the internal circuits. 13 CLK/E I 14 CLKN/E I ECL/PECL Clock Input. DGND3 R 48 RESETN/E I 47 RESET/E I 13 48 14 47 R Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 1.2V R R DVEE3 15 CLK/T I 46 RESETN/T I CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. TTL RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. Clock Input. DVCC1 R/2 15 46 R Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 1.5V DGND1 DVEE3 44 INV I TTL Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1, I/O Correspondence Table.) DVCC1 44 DGND1 DVEE3 7 HI3026A Pin Descriptions PIN NO SYMBOL 45 SELECT I/O (Continued) TYPICAL VOLTAGE LEVEL VCC or GND EQUIVALENT CIRCUIT DESCRIPTION Data Output Mode Selection. (See Table 2, Operating Mode Table.) DVCC1 45 DGND1 DVEE3 11 VRT I 4.0V (Typ) Top Reference Voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. R1 11 R/2 9 VRM3 VRB + 3 --- (VRT - VRB) 4 R COMPARATOR 1 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. R 7 VRM2 VRB + 2 --- (VRT - VRB) 4 COMPARATOR 63 9 R Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. COMPARATOR 64 COMPARATOR 127 4 2 VRM1 VRB VRB + 1 --- (VRT - VRB) 4 I 2.0V (Typ) R 7 COMPARATOR 128 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. COMPARATOR 191 4 R COMPARATOR 192 R Bottom Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. COMPARATOR 255 R2 2 R2 6 VIN I VRT to VRB AVCC Analog Input. COMPARATOR AVCC VREF 6 AGND DVEE3 33 to 40 P1D0 to P1D7 O 21 to 28 P2D0 to P2D7 O CLKOUT O Port 1 Side Data Output. DVCC1 DVCC2 Port 2 Side Data Output. 21 TO 28 33 TO 40 100K 43 TTL 43 DGND2 DVEE3 DGND1 8 Clock Output. (See Table 2, Operating Mode Table.) HI3026A patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins to the DGND pattern.) - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1µF tantal capacitor and, 0.1µF capacitor as short as possible. • When the digital input level is ECL or PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and III/E pins left open. TABLE 1. A/D CODE TABLE INV 1 0 VIN STEP VRT 255 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 254 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D7 D0 • • • 128 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 127 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 • • • • • • • • • VRB D0 • • • • • • VRM2 D7 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Notes On Operation • The HI3026A is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground Test Circuits +V 4V 1.95V VRT 5V 5V A ICC A AVCC DVCC1 DVCC2 VIN S2 IEE - + -V A<B A>B COMPARATOR 5MHz PECL VIN 2V VRB S1: ON WHEN A < B S2: ON WHEN A > B DGND3 CLK/E DGND2 DGND1 AGND S1 HI3026A 8 DVEE3 “0” A8 TO A1 B8 TO B1 A0 B0 DVM CONTROLLER FIGURE 4. CURRENT CONSUMPTION MEASUREMENT CIRCUIT 8 BUFFER “1” 000...00 TO 111..10 FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT 9 HI3026A Test Circuits SIGNAL SOURCE fC (Continued) 8 VIN HI3026A CLK -1kHz 4 A LATCH COMPARATOR A>B PULSE COUNTER B CLK + LATCH 2VP-P SINE WAVE SIGNAL SOURCE 1/ 16 LSB 8 fC FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT VRT VIN 100MHz VRM2 VRB AMP CLK OSC1 φ: VARIABLE fR VIN 8 HI3026A ∆V 129 ∆t 128 127 VIN LOGIC ALALYZER σ (LSB) 126 CLK 125 1024 SAMPLES CLK OSC2 ECL BUFFER SAMPLING TIMING FLUCTUATION (= APERTURE JITTER) NOTE: Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter, tAJ is: σ/∆V 256 t AJ = -------------- = σ/ ---------- x 2πf . ∆t 2 100MHz FIGURE 7. SAMPLING DELAY/APERTURE JITTER MEASUREMENT CIRCUIT FIGURE 8. APERTURE JITTER MEASUREMENT METHOD Operating Modes The HI3026A has two types of operating modes which are selected with Pin 45 (SELECT). TABLE 2. OPERATING MODE TABLE OPERATING MODE SELECT MAXIMUM CONVERSION RATE DATA OUTPUT DMUX Mode VCC 140 MSPS Demultiplexed Output 70 Mbps The input clock is 1/2 frequency divided and output at 70MHz. Straight Mode GND 100 MSPS Straight Output 100 Mbps The input clock is inverted and output at 100MHz. DMUX Mode (See Application Circuits, Figures 18, 19, 20) CLOCK OUTPUT countermeasure, the HI3026A is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 140 MSPS in this mode. Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When using multiple HI3026A units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in the figure below. As a Straight Mode (See Application Circuits, Figures 21, 22, 23) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the 10 HI3026A clock applied to the A/D converter as the system clock. TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS The A/D converter can operate at fC (Min) = 100 MSPS in this mode. Digital Input Level and Supply Voltage Settings The logic input level for the HI3026A supports ECL, PECL and TTL levels. The power supplies (DVEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. DIGITAL INPUT LEVEL DVEE3 DGND3 SUPPLY VOLTAGE ECL -5V 0V ±5V (18) (21) PECL 0V +5V +5V (19) (22) TTL 0V +5V +5V (20) (23) CLK HI3026A CLK CLK A CLKOUT 8 BITS DATA RESETN HI3026A CLK B CLKOUT 8 BITS DATA RESETN FIGURE 9. WHEN THE RESET PULSE IS NOT USED CLK RESET PULSE HI3026A CLK CLK A CLKOUT 8 BITS DATA RESETN HI3026A CLK RESET PULSE B RESETN CLKOUT 8 BITS DATA FIGURE 10. WHEN THE RESET PULSE IS USED 11 APPLICATION CIRCUITS (FIGURE) HI3026A Typical Performance Curves 170 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) 170 160 150 140 160 150 fIN = 140 fCLK -1kHz 4 DMUX MODE CL = 5pF 130 130 -25 25 0 75 70 AMBIENT TEMPERATURE (oC) 140 CONVERSION RATE (MSPS) FIGURE 11. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS RESPONSE 200 20 VRB = 2V REFERENCE CURRENT (mA) ANALOG INPUT CURRENT (µA) VRT = 4V 100 0 2 3 15 10 -25 4 25 75 AMBIENT TEMPERATURE (oC) ANALOG INPUT VOLTAGE (V) FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS FIGURE 14. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS 50 10-6 fC = 140 MSPS fIN = ERROR RATE (TPS) 10-7 SNR (dB) 40 30 1 3 5 10 30 50 -1kHz 4 ERROR > 16 LSB 10-8 10-9 10-10 140 20 fCLK 160 CONVERSION RATE (MSPS) INPUT FREQUENCY (MHz) FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATE vs CONVERSION RATE CHARACTERISTICS 12 180 HI3026A Typical Performance Curves (Continued) MAXIMUM CONVERSION (MSPS) 180 fIN = 170 fCLK -1kHz 4 ERROR > 16 LSB ERROR RATE: 10-9 TPS 160 150 140 -25 25 75 AMBIENT TEMPERATURE (Co) FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS Typical Application Circuits +5V (D) DG ECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 -5V (D) 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 5 32 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 1 AG AG 2V +5V (A) AG +5V (A) DG 4V 12 13 14 15 16 17 18 19 20 21 22 23 24 ECL - CLK DG +5V (D) FIGURE 18. DMUX ECL INPUT 13 LATCH DG +5V (D) DG 8-BIT DIGITAL DATA LATCH HI3026A Typical Application Circuits (Continued) +5V (D) DG PECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 5 32 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 1 AG AG 2V +5V (A) AG +5V (A) +5V (D) 4V 12 LATCH DG +5V (D) DG 8-BIT DIGITAL DATA LATCH 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK DG +5V (D) FIGURE 19. DMUX PECL INPUT +5V (D) DG TTL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 1 AG AG 2V +5V (A) +5V (D) 4V 12 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK DG +5V (D) FIGURE 20. DMUX TTL INPUT 14 LATCH DG +5V (D) DG 8-BIT DIGITAL DATA LATCH HI3026A Typical Application Circuits (Continued) DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 -5V (D) AG AG 2V +5V (A) AG +5V (A) AG AG DG 4V 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 1 LATCH DG +5V (D) DG 25 12 13 14 15 16 17 18 19 20 21 22 23 24 ECL - CLK ECL - TTL DG +5V (D) FIGURE 21. STRAIGHT ECL INPUT DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 1 AG AG 2V +5V (A) 4V +5V(D) DG +5V (D) DG 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK PECL - TTL DG +5V (D) FIGURE 22. STRAIGHT PECL INPUT 15 LATCH HI3026A Typical Application Circuits (Continued) DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 AG 1 2V AG +5V (A) +5V(D) 4V LATCH DG +5V (D) DG 25 12 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK DG +5V (D) FIGURE 23. STRAIGHT TTL INPUT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 HI3026A Typical Application Circuits (Continued) AG ANALOG INPUT AG + - AG + +5V (A) 1µF + DG + + 1µF AG + SHORT 11 10 9 8 7 6 5 4 3 2 VRT AGND VRM3 AVCC VRM2 VIN AVCC VRM1 AGND VRB 1 RESETN/E 48 13 CLK/E 14 CLKN/E 15 CLK/T 16 NC SELECT 45 17 NC INV 44 18 NC CLKOUT 43 19 DVCC2 DVCC2 42 20 DGND2 DGND2 41 21 P2D0 P1D7 40 22 P2D1 P1D6 39 23 P2D2 P1D5 38 24 P2D3 P1D4 37 RESET/E 47 P2D5 P2D6 (MSB) P2D7 P1D3 31 32 33 34 35 36 P1D3 DVCC2 30 P1D2 DVCC1 29 P1D2 DGND1 28 P1D1 P2D7 27 P1D1 P2D6 26 P1D0 P2D5 25 (LSB) P1D0 P2D4 RESETN/T 46 P2D4 P2D2 P2D3 (LSB) P2D0 P2D1 12 DGND3 SHORT TTL CLK AG 10µF SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION. IS THE CHIP CAPACITOR OF 0.1µF. FIGURE 24. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED) 17 P1D6 (MSB) P1D7 + DGND2 10µF 2V - - P1D4 P1D5 +5V (D) DVEE3 4V