HI1396 ® CT UCT OD U E P R OD t R P ra TE UT OLE UBSTIT rt Cente tsc S B O uppo .com/ LE S SSIB hnical S .intersil O P w A ec FOR act our T IL or ww 8-Bit, S t n ER co T N I 8 1-88 September 2000 Features 125 MSPS, Flash A/D Converter Description • Differential Linearity Error ±0.5 LSB (Typ) or Less The HI1396 is an 8-bit, ultra high speed flash analog-to-digital converter IC capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K. • Integral Linearity Error ±0.5 LSB (Typ) or Less • Built-In Integral Linearity Compensation Circuit • Ultra High Speed Operation with Maximum Conversion Rate of 125 MSPS (Min) Part Number Information • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 18pF PART NUMBER • Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 200MHz TEMP. RANGE (oC) PACKAGE PKG. NO. • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V HI1396JCJ -20 to 75 42 Ld SBDIP D42.6 • Low Power Consumption (Typ) . . . . . . . . . . . . . 870mW HI1396AIL -20 to 100 68 Ld CLCC J68.A • Low Error Rate • Operable at 50% Clock Duty Cycle • Capable of Driving 50Ω Loads • Direct Replacement for Sony CXA1396 Applications • Video Digitizing • Communication Systems • HDTV (High Definition TV) • Radar Systems • Direct RF Down-Conversion • Digital Oscilloscopes Pinouts 6 37 NC 7 36 NC D1 8 35 AGND D2 9 34 VIN D3 10 33 AGND D4 11 32 VRM D5 12 31 AGND D6 13 30 VIN (MSB) D7 14 29 AGND DGND2 15 28 NC DGND2 16 27 NC DVEE 17 26 AVEE MINV 18 25 AVEE NC 19 23 VRB CLK 21 22 NC NC NC 10 60 NC 11 12 59 AVEE 58 AVEE 13 57 NC 14 15 56 VRB 55 NC 16 54 NC 17 53 NC 18 52 CLK 19 51 CLK 20 50 NC 21 49 MINV 22 48 NC 23 24 47 DVEE 46 NC 25 45 NC 44 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 24 NC CLK 20 1 68 67 66 65 64 63 62 61 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 NC DGND2 (LSB) D0 2 NC NC 38 AVEE 3 DGND2 DGND1 NC 5 4 AGND NC DGND1 NC AVEE AVEE NC VRT NC AVEE NC NC NC LINV NC DVEE NC DGND1 DGND2 NC 5 VIN 39 AVEE 6 D6 4 7 (MSB) D7 NC DVEE 8 9 VIN AGND VRM AGND 40 NC D1 D2 D3 D4 D5 3 NC NC AGND 41 VRT LINV NC NC (LSB) D0 2 NC 42 NC NC NC NC AVEE 1 HI1396 (CLCC) TOP VIEW NC NC HI1396 (SBDIP) TOP VIEW File Number 3576.4 HI1396 Functional Block Diagram MINV VRT R1 COMPARATOR R/2 R 1 R D7 (MSB) 2 R D6 63 D5 R 64 VIN R D4 65 OUTPUT D3 R 126 D2 R VRM 127 R2 ENCODE LOGIC R D1 128 R D0 (LSB) 129 R 191 R 192 VIN R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 2 HI1396 Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bits fC = 125 MSPS - ±0.3 ±0.5 LSB fC = 125 MSPS - - ±0.5 LSB 200 - - MHz - 17 - pF SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL HI1396JCJ, HI1396AIL Differential Linearity Error, DNL HI1396JCJ, HI1396AIL ANALOG INPUT Input Bandwidth VIN = 2VP-P Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS Analog Input Resistance, RIN VIN = -1V Input Bias Current, IIN 50 190 - kΩ 20 130 400 µA 75 110 155 Ω REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT VRT 8 19 32 mV EOB VRB 0 15 24 mV -1.13 - - V DIGITAL INPUTS Logic H Level, VIH - - -1.50 V Logic H Current, IIH Input Connected to -0.8V 0 - 50 µA Logic L Current, IIL Input Connected to -1.6V 0 - 50 µA - 7 - pF Logic L Level, VIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 50Ω to -2V -1.10 - - V Logic L Level, VOL RL = 50Ω to -2V - - -1.62 V TIMING CHARACTERISTICS Output Rise Time, tr RL = 50Ω to -2V, 20% to 80% 0.5 0.9 1.2 ns Output Fall Time, tf RL = 50Ω to -2V, 20% to 80% 0.5 1.0 1.3 ns Output Delay, tOD 3.0 3.6 4.2 ns H Pulse Width of Clock, tPW1 4.0 - - ns L Pulse Width of Clock, tPW0 4.0 - - ns DYNAMIC CHARACTERISTICS Maximum Conversion Rate, fC Error Rate 10-9 TPS (Note 2) Aperture Jitter, tAJ 125 - - MSPS - 10 - ps - 1.5 - ns Input = 1MHz, Full Scale fC = 125 MSPS - 46 - dB Input = 31.5MHz, Full Scale fC = 125 MSPS - 40 - dB Error Rate Input = 31.249MHz, Full Scale Error > 16 LSB, fC = 125 MSPS - - 10-9 TPS (Note 2) Differential Gain Error, DG NTSC 40 IRE Mod. Ramp, fC = 125 MSPS - 1.0 - % - 0.5 - Degree -230 -160 - mA - 870 - mW Sampling Delay, tDS Signal to Noise Ratio (SINAD) RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion Differential Phase Error, DP POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption Note 3 3 HI1396 TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 2 3. ( V RT – V RB ) PD = IEE • V EE + ------------------------------------R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram ANALOG IN N+1 N N+2 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 20% tOD 80% tr N 20% N+1 80% tf FIGURE 1. Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 29, 31, 33, 35 49, 51, 53, 55 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. 1, 25, 26, 38, 39 41, 42, 62, 63, 67 AV EE - -5.2V Analog VEE -5.2V (Typ). Internally connected to DV EE (Resistance: 4Ω to 6Ω). Bypass with 0.1µF to AGND. EQUIVALENT CIRCUIT 4 DESCRIPTION HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 21 35 CLK I ECL 20 34 CLK (Continued) EQUIVALENT CIRCUIT DESCRIPTION CLK Input. DGND1 Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. R R R R CLK CLK R DVEE R 5, 16 7, 24 DGND1 - 0V Digital GND for internal circuits. 6, 15 8, 23 DGND2 - 0V Digital GND for output transistors. 4, 17 5, 30 DV EE - -5.2V Digital VEE . Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1µF to DGND 7 14 D0 O ECL 8 15 D1 9 16 D2 10 17 D3 11 18 D4 12 19 D5 13 20 D6 14 21 D7 DGND2 DI DVEE 5 LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required. MSB of data outputs. External pull-down resistor is required. HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 3 3 LINV I ECL 18 32 MINV I ECL (Continued) EQUIVALENT CIRCUIT DESCRIPTION Input pin for D0 (LSB) to D6 output polarity inversion (see A/D Output Code Table). Pulled low when left open. DGND1 Input pin for D7 (MSB) output polarity inversion (see A/D Output Code Table). Pulled low when left open. R R 30, 34 50, 54 V IN I LINV OR MINV R DVEE R -1.3V VRT to VRB AGND Analog input pins. These two pins must be connected externally, since they are not internally connected. VIN VIN AVEE 23 39 VRB I -2V 32 52 VRM I VRB/2 41 65 V RT I 0V VRT Reference voltage (bottom). Typically -2V. Bypass with a 0.1µF and 10µF to AGND. R1 R/2 R COMPARATOR 1 R COMPARATOR 2 R VRM COMPARATOR 127 R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 6 R/2 Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically 0V. When a voltage different from AGND is applied to this pin, bypass with a 0.1µF and 10µF to AGND. HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 1, 2, 4, 6, 9-13, 25-29, 31, 33, 36-38, 40, 43-48, 56-61, 64, 66, 68 NC - - (Continued) EQUIVALENT CIRCUIT DESCRIPTION Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended. A/D OUTPUT CODE TABLE MINV 1, LINV 1 VIN (Note 5) STEP D7 0V -1V D0 0, 1 D7 1, 0 D0 D7 0, 0 D0 D7 D0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 1 000 • • • • • 01 100 • • • • • 01 011 • • • • • 10 111 • • • • • 10 • • • • • • • • • • • • 127 011 • • • • • 11 111 • • • • • 11 000 • • • • • 00 100 • • • • • 00 128 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 • • • • • • • • • • • • 254 111 • • • • • 10 011 • • • • • 10 100 • • • • • 01 000 • • • • • 01 255 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 -2V NOTE: 5. VRT = 0V, VRB = -2V. Test Circuits SIGNAL SOURCE fCLK 4 -1kHz VIN HI1396 CLK 8 A ECL LATCH B CLK + ECL LATCH 2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK/4 fCLK FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT 7 COMPARATOR A>B PULSE COUNTER Test Circuits (Continued) HI20201 VIN AMP 8 DUT HI1396 CLK 8 ECL LATCH 10 BIT D/A CLK NTSC SIGNAL SOURCE DELAY SG (CW) 50 VBB VECTOR SCOPE DG/DP FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT +V S2 - S1 : A < B : ON S2 : A > B : ON S1 + -V A<B VIN A>B COMPARATOR DUT HI1396 8 “0” DVM A8 B8 A1 A0 B1 B0 8 BUFFER “1” 8 CLK (125 MSPS) CONTROLLER 00000000 TO 11111110 FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 8 Test Circuits (Continued) IIN 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 11 A -1V -2V A IIN 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 33 HI1396JCJ 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 -1V 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 HI1396AIL 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 -2V A I EE -5.2V A IEE -5.2V FIGURE 5A. FIGURE 5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS 0V -1V VIN -2V 67.5MHz OSC1 φ: VARIABLE fR AMP CLK VIN HI1396 CLK LOGIC ANALYZER VIN OSC2 67.5MHz 8 ∆υ ∆t t 1024 SAMPLES ECL BUFFER CLK 129 128 127 126 125 σ (LSB) APERTURE JITTER Aperture jitter is defined as follows: 256 ∆υ tAJ = σ ⁄ ------- = σ ⁄ ---------- × 2πf 2 ∆t Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 9 HI1396 10